PHILIPS BUK9MLL

BUK9MLL-55PLL
Dual TrenchPLUS logic level FET
Rev. 01 — 14 May 2009
Product data sheet
1. Product profile
1.1 General description
Dual N-channel enhancement mode field-effect power transistor in SO20. Device is
manufactured using NXP High-Performance (HPA) TrenchPLUS technology, featuring
very low on-state resistance, integrated current sensing transistors and over temperature
protection diodes.
1.2 Features and benefits
„ Integrated current sensors
„ Integrated temperature sensors
1.3 Applications
„ Lamp switching
„ Power distribution
„ Motor drive systems
„ Solenoid drivers
1.4 Quick reference data
Table 1.
Quick reference
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics, FET1 and FET2
RDSon
drain-source
on-state resistance
VGS = 5 V; ID = 5 A;
Tj = 25 °C; see Figure 16;
see Figure 17
-
42.5
50
mΩ
ID/Isense
ratio of drain current
to sense current
Tj = 25 °C; VGS = 5 V; see
Figure 18
2430
2700
2970
A/A
Tj = 25 °C; VGS = 0 V;
ID = 250 µA
55
-
-
V
V(BR)DSS drain-source
breakdown voltage
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
2. Pinning information
Table 2.
Pinning information
Pin
Symbol
Description
Simplified outline
1
G1
gate 1
2
IS1
current sense 1
3
D1
drain 1
4
A1
anode 1
5
C1
cathode 1
6
G2
gate 2
7
IS2
current sense 2
8
D2
drain 2
9
A2
anode 2
10
C2
cathode 2
11
D2
drain 2
12
KS2
Kelvin source 2
13
S2
source 2
14
S2
source 2
15
D2
drain 2
16
D1
drain 1
17
KS1
Kelvin source 1
18
S1
source 1
19
S1
source 1
20
D1
drain 1
Graphic symbol
11
20
D1
A1
FET1
D2
A2
FET2
10
1
SOT163-1
(SO20)
G1
IS1 S1 KS1 C1 G2
IS2 S2 KS2 C2
003aaa745
3. Ordering information
Table 3.
Ordering information
Type number
BUK9MLL-55PLL
Package
Name
Description
Version
SO20
plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
2 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Conditions
Min
Max
Unit
Limiting values, FET1 and FET2
VDS
drain-source voltage
25 °C < Tj < 150 °C
-
55
V
VDGR
drain-gate voltage
RGS = 20 kΩ; 25 °C < Tj < 150 °C
-
55
V
VGS
gate-source voltage
-15
15
V
ID
drain current
Tsp = 25 °C; VGS = 5 V; see Figure 2; see Figure 3; [1][2]
-
5.9
A
Tsp = 100 °C; VGS = 5 V; see Figure 2;
-
3.7
A
IDM
peak drain current
Tsp = 25 °C; tp ≤ 10 µs; pulsed; see Figure 3
-
61.3
A
Ptot
total power dissipation
Tsp = 25 °C; see Figure 1
-
3.3
W
Tstg
storage temperature
-55
150
°C
Tj
junction temperature
-55
150
°C
-
100
V
-
4.7
A
-
61.3
A
-
72
mJ
HBM; C = 100 pF; R = 1.5 kΩ; pins 3, 16 and 20 to
pins 1, 2, 17, 18 and 19 shorted
-
4
kV
HBM; C = 100 pF; R = 1.5 kΩ; pins 8, 11 and 15 to
pins 6, 7, 12, 13 and 14 shorted
-
4
kV
HBM; C = 100 pF; R = 1.5 kΩ; all pins
-
0.15
kV
[1][2]
Visol(FET-TSD) FET to temperature
sense diode isolation
voltage
Source-drain diode, FET1 and FET2
IS
source current
Tsp = 25 °C;
ISM
peak source current
tp ≤ 10 µs; pulsed; Tsp = 25 °C
[1][2]
Avalanche ruggedness, FET1 and FET2
EDS(AL)S
non-repetitive
ID = 5.9 A; Vsup ≤ 55 V; VGS = 5 V; Tj(init) = 25 °C;
drain-source avalanche unclamped; see Figure 4;
energy
[3][4]
[5]
Electrostatic discharge, FET1 and FET2
VESD
electrostatic discharge
voltage
[1]
Single device conducting.
[2]
Current is limited by chip power dissipation rating.
[3]
Single-pulse avalanche rating limited by maximum junction temperature of 150 °C.
[4]
Repetitive rating defined in avalanche rating figure.
[5]
Refer to application note AN10273 for further information.
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
3 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aab388
120
003aac541
8
ID
(A)
Pder
(%)
6
80
4
40
2
0
0
0
50
100
150
Tsp
0
200
(°C)
Fig 2.
Fig 1.
Normalized total power dissipation as a
function of solder point temperature, FET1 and
FET2
50
100
150
Tsp (°C)
200
Continuous drain current as a function of
solder point temperature, FET1 and FET2
003aac404
102
ID
(A)
Limit R DS on = VDS / ID
tp = 10 ms
10
100 ms
1 ms
1
10 ms
DC
100 ms
10
-1
10-2
10-1
Fig 3.
1
10
VDS (V)
102
Safe operating area; continuous and peak drain currents as a function of drain-source voltage, FET1 and
FET2
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
4 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac530
10
IAL
(A)
(1)
1
(2)
(3)
10-1
10-2
10-3
Fig 4.
10-2
10-1
1
tAL (ms)
10
Single-pulse and repetitive avalanche rating; avalanche current as a function of avalanche time, FET1 and
FET2
5. Thermal characteristics
Table 5.
Thermal characteristics
Symbol
Parameter
Min
Typ
Max
Unit
Rth(j-sp)
thermal resistance from FET1
junction to solder point FET2
-
27
37
K/W
-
27
37
K/W
thermal resistance from mounted on printed-circuit board; Both
junction to ambient
channel conducting; zero heat sink area;
see Figure 5; see Figure 6
-
73
-
K/W
mounted on printed-circuit board; Both
channel conducting; 200 mm2 copper heat
sink area; see Figure 5; see Figure 7
-
60
-
K/W
mounted on printed-circuit board; Both
channel conducting; 400 mm2 copper heat
sink area; see Figure 5; see Figure 8
-
51
-
K/W
mounted on printed-circuit board; One
channel conducting; zero heat sink area;
see Figure 5; see Figure 6
-
105
-
K/W
mounted on printed-circuit board; One
channel conducting; 200 mm2 copper heat
sink area; see Figure 5; see Figure 7
-
90
-
K/W
mounted on printed-circuit board; One
channel conducting; 400 mm2 copper heat
sink area; see Figure 5; see Figure 8
-
78
-
K/W
Rth(j-a)
Conditions
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
5 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac472
120
Rth(j-a)
(K/W)
(1)
80
(2)
001aae478
40
Fig 6.
PCB used for thermal tests; zero heat sink area
0
0
Fig 5.
100
200
300
A (mm2)
400
Thermal resistance from junction to ambient as
a function of printed-circuit board (PCB) heat
sink area
001aae479
Fig 7.
001aae480
PCB used for thermal tests; heat sink area
200 mm2
Fig 8.
PCB used for thermal tests; heat sink area
400 mm2
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
6 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aad200
102
Zth(j-mb)
(K/W)
δ = 0.5
0.2
10
0.1
0.05
0.02
1
δ=
P
tp
T
10-1
t
tp
single shot
T
10-2
10-6
Fig 9.
10-5
10-4
10-3
10-2
10-1
1
102
10
103
4
t p (s) 10
Transient thermal impedance from junction to ambient as a function of pulse duration, FET1 and FET2(PCB
used for thermal tests;heat sink area 400mm2)
6. Characteristics
Table 6.
Symbol
Characteristics
Parameter
Conditions
Min
Typ
Max
Unit
Static characteristics, FET1 and FET2
V(BR)DSS
VGS(th)
IDSS
drain-source
breakdown voltage
ID = 250 µA; VGS = 0 V; Tj = 25 °C
55
-
-
V
ID = 250 µA; VGS = 0 V; Tj = -55 °C
50
-
-
V
gate-source threshold
voltage
ID = 1 mA; VDS = VGS; Tj = 25 °C; see
Figure 14; see Figure 15
1
1.5
2
V
ID = 1 mA; VDS = VGS; Tj = 150 °C; see
Figure 14; see Figure 15
0.5
-
-
V
ID = 1 mA; VDS = VGS; Tj = -55 °C; see
Figure 14; see Figure 15
-
-
2.3
V
VDS = 40 V; VGS = 0 V; Tj = 25 °C
-
0.02
3
µA
VDS = 40 V; VGS = 0 V; Tj = 150 °C
-
-
125
µA
drain leakage current
IGSS
gate leakage current
VDS = 0 V; VGS = 15 V; Tj = 25 °C
-
2
300
nA
RDSon
drain-source on-state
resistance
VGS = 5 V; ID = 5 A; Tj = 25 °C; see Figure
16; see Figure 17
-
42.5
50
mΩ
VGS = 5 V; ID = 5 A; Tj = 150 °C; see
Figure 16; see Figure 17
-
-
97
mΩ
VGS = 4.5 V; ID = 5 A; Tj = 25 °C; see
Figure 16; see Figure 17
-
47.5
55.8
mΩ
VGS = 10 V; ID = 5 A; Tj = 25 °C; see
Figure 16; see Figure 17
-
41
45.3
mΩ
Tj = 25 °C; VGS = 5 V; see Figure 18
2430
2700
2970
A/A
ID/Isense
ratio of drain current to
sense current
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
7 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
Table 6.
Characteristics …continued
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
SF(TSD)
temperature sense
diode temperature
coefficient
IF = 250 µA; 25 °C < Tj < 150 °C; see
Figure 19
-5.4
-5.7
-6
mV/K
VF(TSD)
temperature sense
diode forward voltage
IF = 250 µA; Tj = 25 °C; see Figure 19
2.855
2.9
2.945
V
Dynamic characteristics, FET1 and FET2
QG(tot)
total gate charge
QGS
gate-source charge
ID = 5 A; VDS = 44 V; VGS = 5 V; see
Figure 20
QGD
gate-drain charge
Ciss
input capacitance
Coss
output capacitance
Crss
reverse transfer
capacitance
td(on)
turn-on delay time
tr
rise time
-
26
-
ns
td(off)
turn-off delay time
-
42
-
ns
tf
fall time
-
22
-
ns
LD
internal drain
inductance
From pin to centre of die
-
0.85
-
nH
LS
internal source
inductance
From source lead to source bonding pad
-
1.9
-
nH
VGS = 0 V; VDS = 25 V; f = 1 MHz;
Tj = 25 °C; see Figure 21
VDS = 30 V; RL = 3 Ω; VGS = 5 V;
RG(ext) = 10 Ω
-
8.3
-
nC
-
3.14
-
nC
-
3.67
-
nC
-
670
893
pF
-
112
134
pF
-
60
82
pF
-
16
-
ns
Source-drain diode, FET1 and FET2
VSD
source-drain voltage
IS = 5 A; VGS = 0 V; Tj = 25 °C; see Figure
22
-
0.85
1.2
V
trr
reverse recovery time
-
40.6
-
ns
Qr
recovered charge
IS = 5 A; dIS/dt = -100 A/µs; VGS = -10 V;
VDS = 30 V
-
57
-
nC
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
8 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac400
60
RDS on
(mΩ)
10
ID
(A)
003aac403
100
80
5
40
4.5
60
4
40
3.5
20
3
20
VGS (V) =2.5
0
0
0
2
4
VDS (V)
Fig 10. Output characteristics: drain current as a
function of drain-source voltage; typical values,
FET1 and FET2
003aac399
25
gfs
(S )
2
6
4
6
8
VGS (V)
10
Fig 11. Drain-source on-state resistance as a function
of gate-source voltage; typical values, FET1 and
FET2
003aac405
30
ID
(A)
20
20
15
Tj = 150 °C
10
25 °C
10
5
0
0
0
5
10
15
20 I D (A) 25
Fig 12. Forward transconductance as a function of
drain current; typical values, FET1 and FET2
0
2
3
4
VGS (V)
5
Fig 13. Transfer characteristics; drain current as a
function of gate-source voltage; typical values,
FET1 and FET2
BUK9MLL-55PLL_1
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
9 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac894
10−1
003aac895
2.5
ID
(A)
VGS(th)
(V)
10−2
2.0
min
typ
max
10−3
1.5
10−4
1.0
10−5
0.5
10−6
0
1
2
0
−60
3
VGS (V)
Fig 14. Sub-threshold drain current as a function of
gate-source voltage, FET1 and FET2
typ
min
0
60
120
180
Tj (°C)
Fig 15. Gate-source threshold voltage as a function of
junction temperature, FET1 and FET2
003aac402
120
RDS on
(mΩ)
max
001aae823
2.0
a
44
100
2.5
3
3.5
4.5
5
1.5
80
1.0
60
VGS (V) = 10
0.5
40
20
0
15
30
45
I D (A) 60
Fig 16. Drain-source on-state resistance as a function
of drain current; typical values, FET1 and FET2
0
−60
60
120
180
Tj (°C)
Fig 17. Normalized drain-source on-state resistance
factor as a function of junction temperature,
FET1 and FET2
BUK9MLL-55PLL_1
Product data sheet
0
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
10 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac398
3500
001aae485
3.0
I D/I sense
VF(TSD)
(V)
3000
2.5
2500
2.0
1.5
2000
2
4
6
8
Fig 18. Ratio of drain current to sense current as a
function of gate-source voltage; typical values,
FET1 and FET2
003aac401
5
VGS
(V)
4
0
VGS(V) 10
40
80
120
160
Tj (°C)
Fig 19. Temperature sense diode forward voltage as a
function of junction temperature; typical values,
FET1 and FET2
003aac397
104
C
(pF)
VDS = 14 V
VDS = 44 V
103
Cis s
3
2
Cos s
102
Crs s
1
0
0
3
6
9
QG (nC)
12
Fig 20. Gate-source voltage as a function of turn-on
gate charge; typical values, FET1 and FET2
10
10-1
10
VDS (V)
102
Fig 21. Input, output and reverse transfer capacitances
as a function of drain-source voltage; typical
values, FET1 and FET2
BUK9MLL-55PLL_1
Product data sheet
1
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
11 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
003aac406
50
IS
(A)
40
30
150 °C
Tj = 25 °C
20
10
0
0
0.5
1
1.5 V (V) 2
SD
Fig 22. Source (diode forward) current as a function of source-drain (diode forward) voltage; typical values, FET1
and FET2
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
12 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
7. Package outline
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A
X
c
HE
y
v M A
Z
20
11
Q
A2
A
(A 3)
A1
pin 1 index
θ
Lp
L
10
1
e
detail X
w M
bp
0
5
10 mm
scale
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
UNIT
A
max.
A1
A2
A3
bp
c
D (1)
E (1)
e
HE
L
Lp
Q
v
w
y
mm
2.65
0.3
0.1
2.45
2.25
0.25
0.49
0.36
0.32
0.23
13.0
12.6
7.6
7.4
1.27
10.65
10.00
1.4
1.1
0.4
1.1
1.0
0.25
0.25
0.1
0.01
0.019 0.013
0.014 0.009
0.51
0.49
0.30
0.29
0.05
0.419
0.043
0.055
0.394
0.016
inches
0.1
0.012 0.096
0.004 0.089
0.043
0.039
0.01
0.01
Z
(1)
0.9
0.4
0.035
0.004
0.016
θ
8o
o
0
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
SOT163-1
075E04
MS-013
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
99-12-27
03-02-19
Fig 23. Package outline SOT163-1
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
13 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
8. Revision history
Table 7.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BUK9MLL-55PLL_1
20090514
Product data sheet
-
-
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
14 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
9. Legal information
9.1
Data sheet status
Document status [1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term 'short data sheet' is explained in section "Definitions".
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product
status information is available on the Internet at URL http://www.nxp.com.
9.2
Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
9.3
Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors accepts no liability for inclusion and/or use of
NXP Semiconductors products in such equipment or applications and
therefore such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Quick reference data — The Quick reference data is an extract of the
product data given in the Limiting values and Characteristics sections of this
document, and as such is not complete, exhaustive or legally binding.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control — This document as well as the item(s) described herein may
be subject to export control regulations. Export might require a prior
authorization from national authorities.
9.4
Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
TrenchMOS — is a trademark of NXP B.V.
10. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BUK9MLL-55PLL_1
Product data sheet
© NXP B.V. 2009. All rights reserved.
Rev. 01 — 14 May 2009
15 of 16
BUK9MLL-55PLL
NXP Semiconductors
Dual TrenchPLUS logic level FET
11. Contents
1
1.1
1.2
1.3
1.4
2
3
4
5
6
7
8
9
9.1
9.2
9.3
9.4
10
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1
General description . . . . . . . . . . . . . . . . . . . . . .1
Features and benefits . . . . . . . . . . . . . . . . . . . . .1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Quick reference data . . . . . . . . . . . . . . . . . . . . .1
Pinning information . . . . . . . . . . . . . . . . . . . . . . .2
Ordering information . . . . . . . . . . . . . . . . . . . . . .2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . .3
Thermal characteristics . . . . . . . . . . . . . . . . . . .5
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Package outline . . . . . . . . . . . . . . . . . . . . . . . . .13
Revision history . . . . . . . . . . . . . . . . . . . . . . . . .14
Legal information. . . . . . . . . . . . . . . . . . . . . . . .15
Data sheet status . . . . . . . . . . . . . . . . . . . . . . .15
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Contact information. . . . . . . . . . . . . . . . . . . . . .15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2009.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 14 May 2009
Document identifier: BUK9MLL-55PLL_1