ETC CY7C1347D

327
CY7C1347D
128K x 36 Synchronous-Pipelined Cache SRAM
Features
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Fast access times: 2.5 and 3.5 ns
Fast clock speed: 250, 225, 200, and 166 MHz
1.5 ns set-up time and 0.5 ns hold time
Fast OE access times: 2.5 ns and 3.5 ns
Optimal for depth expansion (one cycle chip deselect
to eliminate bus contention)
3.3V –5% and +10% power supply
3.3V or 2.5V I/O supply
5V tolerant inputs except I/Os
Clamp diodes to VSS at all inputs and outputs
Common data inputs and data outputs
Byte Write Enable and Global Write control
Three chip enables for depth expansion and address
pipeline
Address, data, and control registers
Internally self-timed Write Cycle
Burst control pins (interleaved or linear burst sequence)
Automatic power-down for portable applications
JTAG boundary scan
JEDEC standard pinout
Low profile 119-lead, 14-mm x 22-mm BGA (Ball Grid
Array) and 100-pin TQFP packages
Functional Description
This Cypress Synchronous Burst SRAM employs high-speed,
low-power CMOS designs using advanced triple-layer
polysilicon, double-layer metal technology. Each memory cell
consists of four transistors and two high-valued resistors.
The CY7C1347D SRAM integrate 131,072 x 36 SRAM cells
with advanced synchronous peripheral circuitry and a 2-bit
counter for internal burst operation. All synchronous inputs are
gated by registers controlled by a positive-edge-triggered
clock input (CLK). The synchronous inputs include all addresses, all data inputs, address-pipelining Chip Enable (CE),
depth-expansion Chip Enables (CE2 and CE2), Burst Control
Inputs (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
BWc, BWd, and BWE), and Global Write (GW).
Asynchronous inputs include the Output Enable (OE) and
Burst Mode Control (MODE). The data outputs (Q), enabled
by OE, are also asynchronous.
Addresses and chip enables are registered with either Address Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be internally generated as controlled by the Burst Advance pin (ADV).
Address, data inputs, and write controls are registered on-chip
to initiate self-timed Write cycle. Write cycles can be one to
four bytes wide as controlled by the write control inputs. Individual byte write allows individual byte to be written. BWa controls DQa. BWb controls DQb. BWc controls DQc. BWd controls DQd. BWa, BWb, BWc, and BWd can be active only with
BWE being LOW. GW being LOW causes all bytes to be written.
Four pins are used to implement JTAG test capabilities: Test
Mode Select (TMS), Test Data-in (TDI), Test Clock (TCK), and
Test Data-out (TDO). The JTAG circuitry is used to serially shift
data to and from the device. JTAG inputs use LVTTL/LVCMOS
levels to shift data during this testing mode of operation.
The CY7C1347D operates from a +3.3V power supply. All inputs and outputs are LVTTL compatible
Selection Guide
CY7C1347D-250
CY7C1347D-225
CY7C1347D-200
CY7C1347D-166
Maximum Access Time (ns)
2.5
2.5
2.5
3.5
Maximum Operating Current (mA)
450
400
360
300
Maximum CMOS Standby Current (mA)
10
10
10
10
Cypress Semiconductor Corporation
Document #: 38-05022 Rev. *A
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3901 North First Street
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San Jose
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CA 95134 • 408-943-2600
Revised June 6, 2001
CY7C1347D
Functional Block Diagram—CY7C1347D[1]
BYTE a WRITE
BWa#
BWE#
D
Q
CLK
BYTE b WRITE
BWb#
D
Q
GW#
BYTE c WRITE
BWc#
D
Q
BYTE d WRITE
ENABLE
D
CE2
Q
D
Q
byte b write
byte a write
CE#
Q
byte c write
D
byte d write
BWd#
CE2#
OE#
Power Down Logic
Input
Register
ADSP#
15
Address
Register
ADSC#
CLR
ADV#
A1-A0
Binary
Counter
& Logic
OUTPUT
REGISTER
D
Q
Output Buffers
A
128K x 9 x 4
SRAM Array
ZZ
DQa,DQb
DQc,DQd
MODE
Note:
1. The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing diagrams for detailed information.
Document #: 38-05022 Rev. *A
Page 2 of 24
CY7C1347D
Pin Configurations
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
A
A
CE
CE2
BWd
BWc
BWb
BWa
CE2
VCC
VSS
CLK
GW
BWE
OE
ADSC
ADSP
ADV
A
A
100-Pin TQFP
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
CY7C1347D
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
DQb
DQb
DQb
VCCQ
VSS
DQb
DQb
DQb
DQb
VSS
VCCQ
DQb
DQb
VSS
NC
VCC
ZZ
DQa
DQa
VCCQ
VSS
DQa
DQa
DQa
DQa
VSS
VCCQ
DQa
DQa
DQa
MODE
A
A
A
A
A1
A0
TMS
TDI
VSS
VCC
TDO
TCK
A
A
A
A
A
A
A
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
DQc
DQc
DQc
VCCQ
VSS
DQc
DQc
DQc
DQc
VSS
VCCQ
DQc
DQc
NC
VCC
NC
VSS
DQd
DQd
VCCQ
VSS
DQd
DQd
DQd
DQd
VSS
VCCQ
DQd
DQd
DQd
Document #: 38-05022 Rev. *A
Page 3 of 24
CY7C1347D
Pin Configurations (continued)
119-Ball BGA
Top View
1
2
3
4
5
6
7
A
VCCQ
A
A
ADSP
A
A
VCCQ
B
NC
CE2
A
ADSC
A
CE2
NC
C
NC
A
A
VCC
A
A
NC
D
DQc
DQc
VSS
NC
VSS
DQb
DQb
E
DQc
DQc
VSS
CE
VSS
DQb
DQb
F
VCCQ
DQc
VSS
OE
VSS
DQb
VCCQ
G
DQc
DQc
BWc
ADV
BWb
DQb
DQb
H
DQc
DQc
VSS
GW
VSS
DQb
DQb
J
VCCQ
VCC
NC
VCC
NC
VCC
VCCQ
K
DQd
DQd
VSS
CLK
VSS
DQa
DQa
L
DQd
DQd
BWd
NC
BWa
DQa
DQa
M
VCCQ
DQd
VSS
BWE
VSS
DQa
VCCQ
N
DQd
DQd
VSS
A1
VSS
DQa
DQa
P
DQd
DQd
VSS
A0
VSS
DQa
DQa
R
NC
A
MODE
VCC
NC
A
NC
T
NC
NC
A
A
A
NC
ZZ
U
VCCQ
TMS
TDI
TCK
TDO
NC
VCCQ
Document #: 38-05022 Rev. *A
Page 4 of 24
CY7C1347D
CY7C1347D Pin Descriptions
BGA Pins
QFP Pins
Name
Type
Description
4P
4N
2A, 3A, 5A, 6A,
3B, 5B, 2C, 3C,
5C, 6C, 2R, 6R,
3T, 4T, 5T
37
36
35, 34, 33, 32,
100, 99, 82, 81,
44, 45, 46, 47,
48, 49, 50
A0
A1
A
InputSynchronous
Addresses: These inputs are registered and must meet the
set-up and hold times around the rising edge of CLK. The burst
counter generates internal addresses associated with A0 and
A1, during burst cycle and wait cycle.
5L
5G
3G
3L
93
94
95
96
BWa
BWb
BWc
BWd
InputSynchronous
Byte Write: A byte write is LOW for a Write cycle and HIGH for
a Read cycle. BWa controls DQa. BWb controls DQb. BWc
controls DQc. BWd controls DQd. Data I/O are high impedance
if either of these inputs are LOW, conditioned by BWE being
LOW.
4M
87
BWE
InputSynchronous
Write Enable: This active LOW input gates byte write operations and must meet the set-up and hold times around the
rising edge of CLK.
4H
88
GW
InputSynchronous
Global Write: This active LOW input allows a full 36-bit Write
to occur independent of the BWE and BWn lines and must
meet the set-up and hold times around the rising edge of CLK.
4K
89
CLK
InputSynchronous
Clock: This signal registers the addresses, data, chip enables,
write control and burst control inputs on its rising edge. All
synchronous inputs must meet set-up and hold times around
the clock’s rising edge.
4E
98
CE
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device and to gate ADSP.
6B
92
CE2
InputSynchronous
Chip Enable: This active LOW input is used to enable the
device.
2U
38
TMS
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS.
2U
39
TDI
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VCC.
3U
43
TCK
Input
IEEE 1149.1 test inputs. LVTTL-level inputs. If JTAG feature is
not utilized, this pin can be disconnected or connected to VSS
or VCC.
5U
42
TDO
Output
IEEE 1149.1 test output. LVTTL-level output. If JTAG feature is
not utilized, this pin should be disconnected.
1B, 7B, 1C, 7C,
4D, 3J, 5J, 4L,
1R, 5R, 7R, 1T,
2T, 6T, 6U
14, 16, 66
NC
-
Burst Address Table (MODE = NC/VCC)
No Connect: These signals are not internally connected.
Burst Address Table (MODE = GND)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
First
Address
(external)
Second
Address
(internal)
Third
Address
(internal)
Fourth
Address
(internal)
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A01
A...A00
A...A11
A...A10
A...A01
A...A10
A...A11
A...A00
A...A10
A...A11
A...A00
A...A01
A...A10
A...A11
A...A00
A...A01
A...A11
A...A10
A...A01
A...A00
A...A11
A...A00
A...A01
A...A10
Document #: 38-05022 Rev. *A
Page 5 of 24
CY7C1347D
Truth Table[2, 3, 4, 5, 6, 7]
Operation
Address
Used
CE
ADSC
ADV
WRITE
OE
CLK
DQ
Deselected Cycle, Power Down
None
H
X
X
X
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
L
X
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
X
L
H
L
X
X
X
L-H
High-Z
Deselected Cycle, Power Down
None
L
H
X
H
L
X
X
X
L-H
High-Z
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
L
X
X
X
H
L-H
High-Z
WRITE Cycle, Begin Burst
External
L
L
H
H
L
X
L
X
L-H
D
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
L
L-H
Q
READ Cycle, Begin Burst
External
L
L
H
H
L
X
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
X
X
X
H
H
L
H
H
L-H
High-Z
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
L
L-H
Q
READ Cycle, Continue Burst
Next
H
X
X
X
H
L
H
H
L-H
High-Z
WRITE Cycle, Continue Burst
Next
X
X
X
H
H
L
L
X
L-H
D
WRITE Cycle, Continue Burst
Next
H
X
X
X
H
L
L
X
L-H
D
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
X
X
X
H
H
H
H
H
L-H
High-Z
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
L
L-H
Q
READ Cycle, Suspend Burst
Current
H
X
X
X
H
H
H
H
L-H
High-Z
WRITE Cycle, Suspend Burst
Current
X
X
X
H
H
H
L
X
L-H
D
WRITE Cycle, Suspend Burst
Current
H
X
X
X
H
H
L
X
L-H
D
CE2 CE2 ADSP
Partial Truth Table for READ/WRITE
FUNCTION
GW
BWE
BWa
BWb
BWc
BWd
READ
H
H
X
X
X
X
READ
H
L
H
H
H
H
WRITE one byte
H
L
L
H
H
H
WRITE all bytes
H
L
L
L
L
L
WRITE all bytes
L
X
X
X
X
X
Note:
2. X means “Don’t Care.” H means logic HIGH. L means logic LOW.
WRITE = L means [BWE + BWa*BWb*BWc*BWd]*GW equals LOW. WRITE = H means [BWE + BWa*BWb*BWc*BWd]*GW equals HIGH.
BWa enables write to DQa. BWb enables write to DQb. BWc enables write to DQc. BWd enables write to DQd.
3. All inputs except OE must meet set-up and hold times around the rising edge (LOW to HIGH) of CLK.
4. Suspending burst generates wait cycle.
5. For a write operation following a read operation, OE must be HIGH before the input data required set-up time plus High-Z time for OE and staying HIGH
throughout the input data hold time.
6. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
7. ADSP LOW along with chip being selected always initiates a READ cycle at the L-H edge of CLK. A WRITE cycle can be performed by setting WRITE LOW
for the CLK L-H edge of the subsequent wait cycle. Refer to WRITE timing diagram for clarification.
Document #: 38-05022 Rev. *A
Page 6 of 24
CY7C1347D
IEEE 1149.1 Serial Boundary Scan (JTAG)
Overview
This device incorporates a serial boundary scan access port
(TAP). This port is designed to operate in a manner consistent
with IEEE Standard 1149.1-1990 (commonly referred to as
JTAG), but does not implement all of the functions required for
IEEE 1149.1 compliance. Certain functions have been modified or eliminated because their implementation places extra
delays in the critical speed path of the device. Nevertheless,
the device supports the standard TAP controller architecture
(the TAP controller is the state machine that controls the TAPs
operation) and can be expected to function in a manner that
does not conflict with the operation of devices with IEEE Standard 1149.1 compliant TAPs. The TAP operates using
LVTTL/LVCMOS logic level signaling.
Disabling the JTAG Feature
It is possible to use this device without using the JTAG feature.
To disable the TAP controller without interfering with normal
operation of the device, TCK should be tied LOW (VSS) to
prevent clocking the device. TDI and TMS are internally pulled
up and may be unconnected. They may alternately be pulled
up to VCC through a resistor. TDO should be left unconnected.
Upon power-up the device will come up in a reset state which
will not interfere with the operation of the device.
Test Access Port (TAP)
TCK - Test Clock (INPUT)
Clocks all TAP events. All inputs are captured on the rising
edge of TCK and all outputs propagate from the falling edge
of TCK.
TMS - Test Mode Select (INPUT)
The TMS input is sampled on the rising edge of TCK. This is
the command input for the TAP controller state machine. It is
allowable to leave this pin unconnected if the TAP is not used.
The pin is pulled up internally, resulting in a logic HIGH level.
TDI - Test Data In (INPUT)
The TDI input is sampled on the rising edge of TCK. This is the
input side of the serial registers placed between TDI and TDO.
The register placed between TDI and TDO is determined by
the state of the TAP controller state machine and the instruction that is currently loaded in the TAP instruction register (refer to Figure 1). It is allowable to leave this pin unconnected if
it is not used in an application. The pin is pulled up internally,
resulting in a logic HIGH level. TDI is connected to the most
significant bit (MSB) of any register (See Figure 2).
TDO - Test Data Out (OUTPUT)
The TDO output pin is used to serially clock data-out from the
registers. The output that is active depending on the state of
the TAP state machine (refer to Figure 1). Output changes in
response to the falling edge of TCK. This is the output side of
the serial registers placed between TDI and TDO. TDO is connected to the least significant bit (LSB) of any register (See
Figure 2).
Performing a TAP Reset
The TAP circuitry does not have a reset pin (TRST, which is
optional in the IEEE 1149.1 specification). A RESET can be
Document #: 38-05022 Rev. *A
performed for the TAP controller by forcing TMS HIGH (VCC)
for five rising edges of TCK and pre-loads the instruction register with the IDCODE command. This type of reset does not
affect the operation of the system logic. The reset affects test
logic only.
At power-up, the TAP is reset internally to ensure that TDO is
in a High-Z state.
Test Access Port (TAP) Registers
Overview
The various TAP registers are selected (one at a time) via the
sequences of ones and zeros input to the TMS pin as the TCK
is strobed. Each of the TAPs registers are serial shift registers
that capture serial input data on the rising edge of TCK and
push serial data out on subsequent falling edge of TCK. When
a register is selected, it is connected between the TDI and
TDO pins.
Instruction Register
The instruction register holds the instructions that are executed by the TAP controller when it is moved into the run test/idle
or the various data register states. The instructions are three
bits long. The register can be loaded when it is placed between
the TDI and TDO pins. The parallel outputs of the instruction
register are automatically preloaded with the IDCODE instruction upon power-up or whenever the controller is placed in the
test-logic reset state. When the TAP controller is in the Capture-IR state, the two least significant bits of the serial instruction register are loaded with a binary “01” pattern to allow for
fault isolation of the board-level serial test data path.
Bypass Register
The bypass register is a single-bit register that can be placed
between TDI and TDO. It allows serial test data to be passed
through the device TAP to another device in the scan chain
with minimum delay. The bypass register is set LOW (VSS)
when the BYPASS instruction is executed.
Boundary Scan Register
The Boundary scan register is connected to all the input and
bidirectional I/O pins (not counting the TAP pins) on the device.
This also includes a number of NC pins that are reserved for
future needs. There are a total of 70 bits for x36 device and 51
bits for x18 device. The boundary scan register, under the control of the TAP controller, is loaded with the contents of the
device I/O ring when the controller is in Capture-DR state and
then is placed between the TDI and TDO pins when the controller is moved to Shift-DR state. The EXTEST, SAMPLE/
PRELOAD and SAMPLE-Z instructions can be used to capture the contents of the I/O ring.
The Boundary Scan Order table describes the order in which
the bits are connected. The first column defines the bit’s position in the boundary scan register. The MSB of the register is
connected to TDI, and LSB is connected to TDO. The second
column is the signal name and the third column is the bump
number. The third column is the TQFP pin number and the
fourth column is the BGA bump number.
Identification (ID) Register
The ID Register is a 32-bit register that is loaded with a device
and vendor specific 32-bit code when the controller is put in
Capture-DR state with the IDCODE command loaded in the
Page 7 of 24
CY7C1347D
instruction register. The register is then placed between the
TDI and TDO pins when the controller is moved into Shift-DR
state. Bit 0 in the register is the LSB and the first to reach TDO
when shifting begins. The code is loaded from a 32-bit on-chip
ROM. It describes various attributes of the device as described
in the Identification Register Definitions table.
TAP Controller Instruction Set
Overview
default instruction loaded in the instruction upon power-up and
at any time the TAP controller is placed in the test-logic reset
state.
SAMPLE-Z
If the High-Z instruction is loaded in the instruction register, all
output pins are forced to a High-Z state and the boundary scan
register is connected between TDI and TDO pins when the
TAP controller is in a Shift-DR state.
There are two classes of instructions defined in the IEEE Standard 1149.1-1990; the standard (public) instructions and device specific (private) instructions. Some public instructions
are mandatory for IEEE 1149.1 compliance. Optional public
instructions must be implemented in prescribed ways.
SAMPLE/PRELOAD
Although the TAP controller in this device follows the IEEE
1149.1 conventions, it is not IEEE 1149.1 compliant because
some of the mandatory instructions are not fully implemented.
The TAP on this device may be used to monitor all input and
I/O pads, but can not be used to load address, data, or control
signals into the device or to preload the I/O buffers. In other
words, the device will not perform IEEE 1149.1 EXTEST, INTEST, or the preload portion of the SAMPLE/PRELOAD command.
When the SAMPLE/PRELOAD instruction is loaded in the instruction register and the TAP controller is in the Capture-DR
state, a snap shot of the data in the device’s input and I/O
buffers is loaded into the boundary scan register. Because the
device system clock(s) are independent from the TAP clock
(TCK), it is possible for the TAP to attempt to capture the input
and I/O ring contents while the buffers are in transition (i.e., in
a metastable state). Although allowing the TAP to sample
metastable inputs will not harm the device, repeatable results
can not be expected. To guarantee that the boundary scan
register will capture the correct value of a signal, the device
input signals must be stabilized long enough to meet the TAP
controller’s capture setup plus hold time (tCS plus tCH). The
device clock input(s) need not be paused for any other TAP
operation except capturing the input and I/O ring contents into
the boundary scan register.
When the TAP controller is placed in Capture-IR state, the two
least significant bits of the instruction register are loaded with
01. When the controller is moved to the Shift-IR state the instruction is serially loaded through the TDI input (while the
previous contents are shifted out at TDO). For all instructions,
the TAP executes newly loaded instructions only when the
controller is moved to Update-IR state. The TAP instruction
sets for this device are listed in the following tables.
EXTEST
EXTEST is an IEEE 1149.1 mandatory public instruction. It is
to be executed whenever the instruction register is loaded with
all 0s. EXTEST is not implemented in this device.
The TAP controller does recognize an all-0 instruction. When
an EXTEST instruction is loaded into the instruction register,
the device responds as if a SAMPLE/PRELOAD instruction
has been loaded. There is one difference between two instructions. Unlike SAMPLE/PRELOAD instruction, EXTEST places
the device outputs in a High-Z state.
IDCODE
The IDCODE instruction causes a vendor-specific, 32-bit code
to be loaded into the ID register when the controller is in Capture-DR mode and places the ID register between the TDI and
TDO pins in Shift-DR mode. The IDCODE instruction is the
Document #: 38-05022 Rev. *A
SAMPLE/PRELOAD is an IEEE 1149.1 mandatory instruction.
The PRELOAD portion of the command is not implemented in
this device, so the device TAP controller is not fully IEEE
1149.1-compliant.
Moving the controller to Shift-DR state then places the boundary scan register between the TDI and TDO pins. Because the
PRELOAD portion of the command is not implemented in this
device, moving the controller to the Update-DR state with the
SAMPLE/PRELOAD instruction loaded in the instruction register has the same effect as the Pause-DR command.
BYPASS
When the BYPASS instruction is loaded in the instruction register and the TAP controller is in the Shift-DR state, the bypass
register is placed between TDI and TDO. This allows the board
level scan path to be shortened to facilitate testing of other
devices in the scan path.
Reserved
Do not use these instructions. They are reserved for future
use.
Page 8 of 24
CY7C1347D
1
TEST-LOGIC
RESET
0
0
REUN-TEST/
IDLE
1
1
1
SELECT
DR-SCAN
SELECT
IR-SCAN
0
0
1
1
CAPTURE-IR
CAPTURE-DR
0
0
0
SHIFT-DR
0
SHIFT-IR
1
1
1
EXIT1-DR
1
EXIT1-IR
0
0
PAUSE-DR
0
0
PAUSE-IR
1
1
0
0
EXIT2-IR
EXIT2-DR
1
1
UPDATE-DR
1
0
UPDATE-IR
1
0
Figure 1. TAP Controller State Diagram[8]
Note:
8. The 0/1 next to each state represents the value at TMS at the rising edge of TCK.
Document #: 38-05022 Rev. *A
Page 9 of 24
CY7C1347D
0
Bypass Register
Selection
Circuitry
2
TDI
1
0
1
0
1
0
Selection
Circuitry
TDO
Instruction Register
31 30
29
.
.
2
Identification Register
x
.
.
.
.
2
Boundary Scan Register [9]
TDI
TAP Controller
TDI
Figure 2. TAP Controller Block Diagram
Document #: 38-05022 Rev. *A
Page 10 of 24
CY7C1347D
TAP DC Electrical Characteristics (20°C < Tj < 110°C; VCC = 3.3V –0.2V and +0.3V unless otherwise noted)
Parameter
Min.
Max.
Unit
Input High (Logic 1)
Voltage: Inputs[10, 11]
VCCQ = 3.3 V
2.0
4.6
V
VCCQ = 2.5V
1.7
4.6
V
Input High (Logic 1)
Voltage: Data[10, 11]
VCCQ = 3.3 V
2.0
VCCQ + 0.3
V
VCCQ = 2.5V
1.7
VCCQ + 0.3
Input Low (Logic 0) Voltage: Inputs
and Data[10, 11]
VCCQ = 3.3 V
–0.5
0.8
V
VCCQ = 2.5V
–0.3
0.7
V
ILI
Input Leakage Current
0V < VIN < VCC
–5.0
5.0
µA
ILI
TMS and TDI Input Leakage Current
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output disabled,
0V < VIN < VCCQ
–5.0
5.0
µA
VOLC
LVCMOS Output Low Voltage[10, 12]
IOLC = 100 µA
0.2
V
VOHC
LVCMOS Output High Voltage[10, 12]
IOHC = 100 µA
VIH
VIL
VOLT
VOHT
Description
Test Conditions
[10]
LVTTL Output Low Voltage
LVTTL Output High Voltage[10]
VCCQ – 0.2
V
VCC = Min. VCCQ = 3.3 V,
IOLT = 8.0 mA
0.4
V
VCC = Min. VCCQ = 2.5V,
IOLT = 2.0 mA
0.7
V
VCC = Min. VCCQ = 2.5V,
IOLT = 1.0 mA
0.4
V
VCC = Min. VCCQ = 3.3 V,
IOH = –4.0 mA
2.4
V
VCC = Min, VCCQ = 2.5V,
IOH = –2.0 mA
2.0
V
Notes:
9. X = 69.
10. All Voltage referenced to VSS (GND).
11. Overshoot: VIH(AC)<VCC+1.5V for t<tKHKH/2, Undershoot: VIL(AC)<–0.5V for t<tKHKH/2, Power-up: VIH<3.6V and VCC<3.135V and VCCQ<1.4V for t<200 ms.
During normal operation, VCCQ must not exceed 3.6V. Control input signals (such as R/W, ADV/LD, etc.) may not have pulse widths less than tKHKL (min.).
12. This parameter is sampled.
Document #: 38-05022 Rev. *A
Page 11 of 24
CY7C1347D
TAP AC Switching Characteristics Over the Operating Range[13, 14]
Parameter
Description
Min.
Max
Unit
Clock
tTHTH
Clock Cycle Time
20
ns
fTF
Clock Frequency
tTHTL
Clock HIGH Time
8
ns
tTLTH
Clock LOW Time
8
ns
tTLQX
TCK LOW to TDO Unknown
0
tTLQV
TCK LOW to TDO Valid
tDVTH
TDI Valid to TCK HIGH
5
ns
tTHDX
TCK HIGH to TDI Invalid
5
ns
tMVTH
TMS Set-up
5
ns
tCS
Capture Set-up
5
ns
tTHMX
TMS Hold
5
ns
tCH
Capture Hold
5
ns
50
MHz
Output Times
ns
10
ns
Set-up Times
Hold Times
Notes:
13. tCS and tCH refer to the set-up and hold time requirements of latching data from the boundary scan register.
14. Test conditions are specified using the load in TAP AC Test Conditions.
Document #: 38-05022 Rev. *A
Page 12 of 24
CY7C1347D
TAP Timing and Test Conditions
ALL INPUT PULSES
3.3V / 2.5V
TDO
Z0 = 50
Ω
50Ω
20 pF
for 3.3V VCCQ or
Vt = 1.5V
1.5V
VSS
1.5 ns
1.5 ns
VCCQ/2 for 2.5V VCCQ
(a)
t
t
THTH
THTL
t
TLTH
TEST CLOCK
(TCK)
tMVTH
tTHMX
tDVTH
tTHDX
TEST MODE SELECT
(TMS)
TEST DATA IN
(TDI)
tTLQV
tTLQX
TEST DATA OUT
(TDO)
Document #: 38-05022 Rev. *A
Page 13 of 24
CY7C1347D
Identification Register Definitions
Instruction Field
128K x 36
Description
REVISION NUMBER
(31:28)
XXXX
Reserved for revision number.
DEVICE DEPTH
(27:23)
00111
Defines depth of words.
DEVICE WIDTH
(22:18)
00011
Defines width of bits.
RESERVED
(17:12)
XXXXXX
CYPRESS JEDEC ID CODE (11:1)
00011100100
ID Register Presence
Indicator (0)
1
Reserved for future use.
Allows unique identification of DEVICE vendor.
Indicates the presence of an ID register.
Scan Register Sizes
Register Name
Bit Size (x36)
Instruction
3
Bypass
1
ID
32
Boundary Scan
51
Instruction Codes
Instruction
Code
Description
EXTEST
000
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state. This instruction is not
IEEE 1149.1-compliant.
IDCODE
001
Preloads ID register with vendor ID code and places it between TDI and
TDO. This instruction does not affect device operations.
SAMPLE-Z
010
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. Forces all device outputs to High-Z state.
RESERVED
011
Do not use these instructions; they are reserved for future use.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI
and TDO. This instruction does not affect device operations. This instruction
does not implement IEEE 1149.1 PRELOAD function and is therefore not
1149.1-compliant.
RESERVED
101
Do not use these instructions; they are reserved for future use.
RESERVED
110
Do not use these instructions; they are reserved for future use.
BYPASS
111
Places the bypass register between TDI and TDO. This instruction does not
affect device operations.
Document #: 38-05022 Rev. *A
Page 14 of 24
CY7C1347D
Boundary Scan Order (continued)
Boundary Scan Order
Bit#
Signal Name
TQFP
Bump ID
Bit#
Signal Name
TQFP
Bump ID
1
A
44
2R
36
CE2
92
6B
2
A
45
3T
37
BWa
93
5L
3
A
46
4T
38
BWb
94
5G
BWc
95
3G
4
A
47
5T
39
5
A
48
6R
40
BWd
96
3L
6
A
49
3B
41
CE2
97
2B
7
A
50
5B
42
CE
98
4E
A
99
3A
8
DQa
51
6P
43
9
DQa
52
7N
44
A
100
2A
10
DQa
53
6M
45
DQc
1
2D
11
DQa
56
7L
46
DQc
2
1E
DQc
3
2F
12
DQa
57
6K
47
13
DQa
58
7P
48
DQc
6
1G
14
DQa
59
6N
49
DQc
7
2H
15
DQa
62
6L
50
DQc
8
1D
DQc
9
2E
16
DQa
63
7K
51
17
ZZ
64
7T
52
DQc
12
2G
18
DQb
68
6H
53
DQc
13
1H
19
DQb
69
7G
54
NC
14
5R
DQd
18
2K
20
DQb
72
6F
55
21
DQb
73
7E
56
DQd
19
1L
22
DQb
74
6D
57
DQd
22
2M
23
DQb
75
7H
58
DQd
23
1N
DQd
24
2P
24
DQb
78
6G
59
25
DQb
79
6E
60
DQd
25
1K
26
DQb
80
7D
61
DQd
28
2L
27
A
81
6A
62
DQd
29
2N
DQd
30
1P
28
A
82
5A
63
29
ADV
83
4G
64
MODE
31
3R
30
ADSP
84
4A
65
A
32
2C
31
ADSC
85
4B
66
A
33
3C
A
34
5C
32
OE
86
4F
67
33
BWE
87
4M
68
A
35
6C
34
GW
88
4H
69
A1
36
4N
35
CLK
89
4K
70
A0
37
4P
Document #: 38-05022 Rev. *A
Page 15 of 24
CY7C1347D
Maximum Ratings
Power Dissipation.......................................................... 1.0W
Short Circuit Output Current........................................ 50 mA
(Above which the useful life may be impaired. For user guidelines, not tested.)
Operating Range
Voltage on VCC Supply Relative to VSS ......... –0.5V to +4.6V
VIN ...........................................................–0.5V to VCC+0.5V
Range
Storage Temperature (plastic) .......................–55°C to +150°
Ambient
Temperature[15]
VCC
0°C to +70°C
3.3V −5%/+10%
Com’l
Junction Temperature ..................................................+150°
Electrical Characteristics Over the Operating Range
Parameter
VIH
Description
Test Conditions
Min.
Max.
Unit
Input High (Logic 1)
Voltage: Inputs[10, 11]
VCCQ = 3.3 V
2.0
4.6
V
VCCQ = 2.5V
1.7
4.6
V
Input High (Logic 1)
Voltage: Data[10, 11]
VCCQ = 3.3 V
2.0
VCCQ + 0.3
V
VCCQ = 2.5V
1.7
VCCQ + 0.3
VIL
Input Low (Logic 0) Voltage: Inputs
and Data[10, 11]
VCCQ = 3.3 V
–0.5
0.8
VCCQ = 2.5V
–0.3
0.7
V
ILI
Input Leakage Current
0V < VIN < VCC
–5
5
µA
ILI
MODE and ZZ Input Leakage
Current[17]
0V < VIN < VCC
–30
30
µA
ILO
Output Leakage Current
Output(s) disabled, 0V < VOUT < VCC
–5
5
µA
VCC = Min, VCCQ = 3.3 V, IOH = –4.0 mA
2.4
V
VCC = Min, VCCQ = 2.5V, IOH = –2.0 mA
2.0
V
VOH
VOL
VCC
VCCQ
Parameter
Output High Voltage
Output Low Voltage
Supply Voltage
[10]
[10]
VCC = Min, VCCQ = 3.3V, IOL = 8.0 mA
0.4
V
VCC = Min, VCCQ = 2.5V, IOH = 2.0 mA
0.7
V
VCC = Min, VCCQ = 2.5V, IOH = 1.0 mA
0.4
V
3.135
3.6
V
3.3 V Range
3.135
3.6
V
2.5 V Range
2.375
2.9
V
[10]
I/O Supply Voltage
[10]
Description
V
Conditions
Typ.
-4
-4.4
-5
-6
Unit
Device selected; all inputs < VILor > VIH;
cycle time > tKC min.; VCC = Max.;
outputs open
150
450
400
360
300
mA
ICC
Power Supply
Current:
Operating[18, 19, 20]
ISB2
CMOS Standby[19, 20] Device deselected; VCC = Max.;
all inputs < VSS + 0.2 or >VCC – 0.2;
all inputs static; CLK frequency = 0
5
10
10
10
10
mA
ISB3
TTL Standby[19, 20]
Device deselected; all inputs < VIL
or > VIH; all inputs static;
VCC = Max.; CLK frequency = 0
10
20
20
20
20
mA
ISB4
Clock Running[19, 20]
Device deselected;
all inputs < VIL or > VIH; VCC = Max.;
CLK cycle time > tKC min.
40
140
125
110
90
mA
Notes:
15. TA is the case temperature.
16. Overshoot: VIH ≤ +6.0V for t ≤ tKC /2.
Undershoot:VIL ≤ –2.0V for t ≤ tKC /2.
17. Output loading is specified with CL = 5 pF as in AC Test Loads.
18. ICC is given with no output current. ICC increases with greater output loading and faster cycle times.
19. “Device Deselected” means the device is in Power-Down mode as defined in the truth table. “Device Selected” means the device is active.
20. Typical values are measured at 3.3V, 25°C, and 20-ns cycle time.
Document #: 38-05022 Rev. *A
Page 16 of 24
CY7C1347D
Capacitance[12]
Parameter
Description
Test Conditions
CI
Input Capacitance
CO
Input/Output Capacitance (DQ)
Typ.
Max.
Unit
5
7
pF
7
8
pF
TA = 25°C, f = 1 MHz,
VCC = 3.3V
Thermal Resistance
Description
Test Conditions
Thermal Resistance (Junction to Ambient) Still Air, soldered on a 4.25 x
1.125 inch, 4-layer PCB
Thermal Resistance (Junction to Case)
Symbol
TQFP Typ.
BGA Typ.
Unit
ΘJA
25
50
°C/W
ΘJC
9
8
°C/W
AC Test Loads and Waveforms
317Ω / 225Ω
3.3V / 2.5V
DQ
DQ
Z0 =50Ω
50Ω
ALL INPUT PULSES
3.3V / 2.5V
10%
5 pF
351Ω
/ 225Ω
V
= 1.5Vfor 3.3V VCCQ
or VCCQ/2 for 2.5V VCCQ
t
(a)
Document #: 38-05022 Rev. *A
(b)
90%
10%
90%
0V
≤ 1.5 ns
≤ 1.5 ns
(c)
Page 17 of 24
CY7C1347D
Switching Characteristics Over the Operating Range[21]
250 MHz
Parameter
Description
Min.
Max.
225 MHz
Min.
Max.
200 MHz
Min.
Max.
166 MHz
Min.
Max.
Unit
Clock
tKC
Clock Cycle Time
4.0
4.4
5.0
6.0
ns
tKH
Clock HIGH Time
1.6
1.7
2.0
2.4
ns
tKL
Clock LOW Time
1.6
1.7
2.0
2.4
ns
Output Times
tKQ
Clock to Output Valid
tKQX
Clock to Output Invalid
tKQLZ
tKQHZ
2.4
Clock to Output in Low-Z
3.5
ns
1.25
1.25
ns
[12, 17, 22]
0
0
0
0
ns
[12, 17, 22]
1.25
Clock to Output in High-Z
[23]
OE to Output Valid
tOELZ
OE to Output in Low-Z[12, 17, 22]
OE to Output in High-Z
3.0
1.25
tOEQ
tOEHZ
2.5
1.25
3.0
1.25
2.5
0
[12, 17, 22]
3.0
1.25
2.5
0
2.5
3.0
1.25
2.5
0
2.5
4.0
ns
3.5
ns
0
2.5
ns
3.5
ns
Set-up Times
tS
Address, Controls, and Data In[24]
1.5
1.5
1.5
1.5
ns
Address, Controls, and Data In[24]
0.5
0.5
0.5
0.5
ns
Hold Times
tH
Notes:
21. Test conditions as specified with the output loading as shown in part (a) of AC Test Loads unless otherwise noted.
22. At any given temperature and voltage condition, tKQHZ is less than tKQLZ and tOEHZ is less than tOELZ.
23. OE is a “Don’t Care” when a byte write enable is sampled LOW.
24. This is a synchronous device. All synchronous inputs must meet specified set-up and hold time, except for “don’t
care” as defined in the truth table.
Document #: 38-05022 Rev. *A
Page 18 of 24
CY7C1347D
Typical Output Buffer Characteristics
Output High Voltage
Pull-Up Current
Output Low Voltage
Pull-Down Current
IOL (mA) Min. IOL(mA) Max.
VOH (V)
IOH (mA) Min.
IOH (mA) Max.
VOL (V)
–0.5
–38
–105
–0.5
0
0
0
–38
–105
0
0
0
0.8
–38
–105
0.4
10
20
1.25
–26
–83
0.8
20
40
1.5
–20
–70
1.25
31
63
2.3
0
–30
1.6
40
80
2.7
0
–10
2.8
40
80
2.9
0
0
3.2
40
80
3.4
0
0
3.4
40
80
Switching Waveforms
Read Timing[25, 26]
tKC
tKL
CLK
tKH
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
A2
tH
tS
CE#
tS
ADV#
tH
OE#
tKQ
DQ
tKQLZ
tOELZ
Q(A1)
tOEQ
tKQ
Q(A2)
Q(A2+1)
SINGLE READ
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
BURST READ
Notes:
25. CE active in this timing diagram means that all chip enables CE, CE2, and CE2 are active.
26. For X18 product, there are only BWa and BWb for byte write control.
Document #: 38-05022 Rev. *A
Page 19 of 24
CY7C1347D
Switching Waveforms (continued)
Write Timing[25, 26]
CLK
tS
ADSP#
tH
ADSC#
tS
A1
ADDRESS
A2
A3
tH
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
GW#
CE#
tS
ADV#
tH
OE#
tKQX
DQ
Q
tOEHZ
D(A1)
SINGLE WRITE
Document #: 38-05022 Rev. *A
D(A2)
D(A2+1)
D(A2+1)
D(A2+2)
BURST WRITE
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
BURST WRITE
Page 20 of 24
CY7C1347D
Switching Waveforms (continued)
Read/Write Timing[25, 26]
CLK
tS
ADSP#
tH
ADSC#
tS
ADDRESS
A1
A2
BWa#, BWb#,
BWc#, BWd#,
BWE#, GW#
A3
A4
A5
tH
CE#
ADV#
OE#
DQ
Q(A1)
Q(A2)
Single Reads
D(A3)
Single Write
Q(A4)
Q(A4+1)
Q(A4+2)
D(A5)
Burst Read
D(A5+1)
Burst Write
Ordering Information
Speed
(MHz)
250
Ordering Code
CY7C1347D-250AC
CY7C1347D-250BGC
225
CY7C1347D-225AC
CY7C1347D-225BGC
200
CY7C1347D-200AC
CY7C1347D-200BGC
166
CY7C1347D-166AC
CY7C1347D-166BGC
Document #: 38-05022 Rev. *A
Package
Name
Package Type
Operating
Range
A101
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
Commercial
BG119
A101
BG119
A101
BG119
A101
BG119
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
100-Lead 14 x 20 x 1.4 mm Thin Quad Flat Pack
119-Lead FBGA (14 x 22 x 2.4 mm)
Page 21 of 24
CY7C1347D
Package Diagrams
100-Pin Thin Plastic Quad Flatpack (14 x 20 x 1.4 mm) A101
51-85050-A
Document #: 38-05022 Rev. *A
Page 22 of 24
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347D
Package Diagrams (continued)
119-Lead FBGA (14 x 22 x 2.4 mm) BG119
51-85115
Document #: 38-05022 Rev. *A
Page 23 of 24
© Cypress Semiconductor Corporation, 2001. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use
of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize
its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress
Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY7C1347D
Document Title: CY7C1347D: 128K x 36 Synchronous Pipelied SRAM
Document Number: 38-05022
Rev.
ECN No.
Issue
Date
Orig. of
Change
Description of Change
**
106740
05/07/01
RCS
New Data Sheet
*A
107485
06/06/01
RCS
Added Minimum and Maximum values for 2.5V VCCQ
and all other subsequent parameters.
Defined alternate options for non-utilized JTAG pins.
Document #: 38-05022 Rev. *A
Page 24 of 24