CY8CPLC10
Powerline Communication Solution
Features
Functional Overview
■
Integrated Powerline Modem PHY
■
2400 bps Frequency Shift Keying Modulation
■
Powerline Optimized Network Protocol
The CY8CPLC10 is an integrated Powerline Communication
solution with the Powerline Modem PHY and Powerline Network
Protocol Stack on the same chip. This helps in robust communication between different nodes on a Powerline.
■
Integrates Data Link, Transport, and Network Layers
Powerline Transmitter
■
Supports Bidirectional Half-Duplex Communication
■
CRC Error Detection to Minimize Data Loss
The application residing on a host microcontroller generates
messages to be transmitted on the Powerline. These messages
are delivered to the CY8CPLC10 over an I2C serial link.
■
I2C enabled Powerline Application Layer
■
Supports I2C Frequencies of 50, 100, and 400 kHz
■
Reference Designs for 110V to 240V AC, 12V to 24V AC/DC
Coupling Circuits
■
Reference Designs Comply with CENELEC EN50065-1:2001
and FCC Part 15
The Powerline Network Layer residing on the CY8CPLC10
receives these I2C messages and generates a Powerline Transceiver (PLT) packet. These packets are modulated by the FSK
Modem and coupled with Powerline by the external coupling
circuit.
Powerline Receiver
Powerline signals are received by the coupling circuit and
demodulated by the FSK Modem PHY. These PLT packets are
decoded by the Powerline Network Protocol and then transferred
to the external host microcontroller in an I2C format.
Applications
■
Residential and commercial lighting control
■
Home automation
■
Automatic meter reading
■
Industrial control and signage
■
Smart energy management
Logic Block Diagram
Host System
Powerline Network
Protocol
I2C Packet
Powerline
FSK Modem
PHY
Application
Circuitry
CY8CPLC10
PSoCTM/
External µC
Powerline Communication Solution
AC/DC Powerline
Coupling Circuit
(110V-240V AC, 12V-24V
AC/DC, etc.)
Powerline
Cypress Semiconductor Corporation
Document Number: 001-50001 Rev *C
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised August 21, 2009
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CY8CPLC10
Robust Communication using Cypress’s
PLC Solution
Powerline Modem PHY
Figure 2. CY8CPLC10: FSK Modem PHY
Powerlines are one of the world’s most widely available communication mediums for PLC technology. The pervasiveness of
Powerlines also makes it difficult to predict the characteristics
and operation of PLC products. Because of the variable quality
of Powerline around the world, implementing robust communication over Powerline is an engineering challenge. Keeping this
in mind, Cypress's PLC solution is designed to enable secure
and reliable communication over Powerline. Cypress PLC
features that enable robust communication over Powerline
include:
■
■
■
Powerline Network
Protocol
I2C Packet
Powerline
FSK Modem
PHY
Integrated Powerline PHY modem with optimized filters and
amplifiers to work with lossy high voltage and low voltage
Powerlines.
Powerline optimized Network Protocol that supports bidirectional communication with acknowledgement based signaling.
In case of data packet loss due to bursty noise on the Powerline,
the transmitter can retransmit data.
The Powerline Network Protocol also supports 8-bit CRC for
error detection and data packet retransmission.
A Carrier Sense Multiple Access (CSMA) scheme, built into the
Network Protocol, minimizes collisions between packet transmissions on the Powerline. This provides support for multiple
masters and reliable communication on a bigger network.
CY8CPLC10
■
Powerline Communication Solution
The physical layer of Cypress’s PLC solution is implemented
using an FSK modem that enables half duplex communication
on a Powerline. This modem supports raw data rates up to 2400
bps.
Figure 3. CY8CPLC10: FSK Modem PHY Block Diagram
Network Protocol
Detailed Description
Figure 1. CY8CPLC10 Internal Block Diagram
Digital
Receiver
External External
Crystal
Clock
TX
RX
BIU
Digital
Transmitter
Status and interrupt signals
TX
Buffer
SCL
SDA
I2C
Interface
Memory
Array
FSK
Modulator
FSK Out
Processor
RX
Buffer
FSK
De-Modulator
FSK In
EEPROM
I2C Address
Select
3-bit Logical
Address
The CY8CPLC10 consists of two main functional components:
■
■
Powerline Modem PHY
Powerline Network Protocol
Local
Oscillator
Hysteresis
Comparator
Logic ‘1’ or
Logic ‘0’
Low Pass
Filter
Modulator
External Low
Pass Filter
Correlator
Square Wave
at FSK
Frequencies
Transmitter
Clocking
Circuitry
Powerline Modem PHY
CLKSEL
IF Band
Pass Filter
Local
Oscillator
Mixer
Programmable
Gain Amplifier
Receiver
INT
HF Band
Pass Filter
RX
Amplifier
Automatic
Gain Control
Coupling Circuit
The application resides on a host system such as PSoC®,
EZ-Color™, or any other microcontroller. The messages
generated by the application are communicated to the
CY8CPLC10 over I2C and processed by these functional
components. The following sections present a brief description
of each of these components.
Document Number: 001-50001 Rev. *D
Page 2 of 25
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CY8CPLC10
Transmitter Section
Figure 4. CY8CPLC10: Powerline Network Protocol
Digital data from the network layer is serialized by the digital
transmitter and fed as input to the modulator. The modulator
divides the local oscillator frequency by a definite factor
depending on whether the input data is high level logic ‘1’ or low
level logic ‘0’. It then generates a sine wave at 133.3 kHz (Logic
‘0’) or 131.8 kHz (Logic ‘1’), which is fed to the Programmable
Gain Amplifier to generate FSK modulated signals. The logic ‘1’
frequency can also be configured as 130.4 kHz for wider FSK
bandwidth. The device also provides a provision to bypass the
internal TX filter and output a square wave at the respective FSK
frequencies.
Powerline Communication Solution
Powerline Network
Protocol
Powerline
FSK Modem
PHY
CY8CPLC10
I2C Packet
Receiver Section
The incoming FSK signal from the Powerline is input to a High
Frequency (HF) Band Pass Filter that filters out-of-band
frequency components and outputs filtered signal within the
desired spectrum of 125 kHz to 140 kHz for further demodulation. The Mixer block multiplies the filtered FSK signals with a
locally generated signal to produce heterodyned frequencies.
The Intermediate Frequency (IF) Band Pass Filters further
remove out-of-band noise as required for further demodulation.
This signal is fed to the correlator which produces a DC
component (consisting of Logic ‘1’ and ‘0’) and a higher
frequency component.
The output of the correlator is fed to a Low Pass FIlter (LPF) that
outputs only the demodulated digital data at 2400 baud and
suppresses all other higher frequency components generated in
the correlation process. The output of the LPF is digitized by the
hysteresis comparator. This eliminates the effects of correlator
delay and false logic triggers due to noise. The Digital Receiver
deserializes this data and outputs to the Network Layer for interpretation.
The Network Protocol implemented on the CY8CPLC10 chip
supports the following features:
■
Bidirectional half-duplex communication
■
Master and slave and peer-to-peer network of Powerline nodes
■
Multiple masters on Powerline network
■
8-bit logical addressing supports up to 256 Powerline nodes
■
16-bit extended logical addressing supports up to 65530
Powerline nodes
■
64-bit physical addressing supports up to 264 Powerline nodes
■
Individual broadcast or group mode addressing
■
Carrier Sense Multiple Access (CSMA)
■
Full control over transmission parameters
❐ Acknowledged
❐ Unacknowledged
❐ Repeated transmit
❐ Sequence numbering
The receiver also implements Automatic Gain Control (AGC).
This functionality enables the receiver to adjust its gain automatically depending on the signal strength of the input FSK signal.
Coupling Circuit Reference Design
CSMA and Timing Parameters
The coupling circuit couples low voltage signals from
CY8CPLC10 to the Powerline. The topology of this circuit is
determined by the voltage on the Powerline and design
constraints mandated by Powerline usage regulations.
■
Cypress provides reference designs for a range of Powerline
voltages such as 110V AC, 240V AC, 12V DC, 24V DC, and
24V AC. The 110V AC and 240V AC designs are compliant to
the following Powerline usage regulations:
CSMA: The protocol provides the random selection of a period
between 85 and 115 ms (out of seven possible values in this
range) in which the band in use detector must indicate that the
line is not in use, before attempting a transmission
■
Band-In-Use (BIU): A Band-In-Use detector, as defined under
CENELEC EN 50065-1, is active whenever a signal that
exceeds 86 dBuVrms in the range 131.5 KHz to 133.5 KHz is
present for at least 4 ms. This threshold can be configured for
different end-system applications not requiring CENELEC
compliance.The modem tries to retransmit after every 85 to
115 ms when the Band is in use. The Transmitter times out after
1.1 seconds and generates an interrupt to indicate that the
transmitter was unable to acquire the Powerline.
■
FCC part 15 for North America
■
EN50065-1:2001
Powerline Network Protocol
Cypress’s Powerline optimized Network Protocol performs the
functions of the data link, network, and transport layers in an
ISO/OSI Equivalent Model.
Document Number: 001-50001 Rev. *D
Page 3 of 25
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CY8CPLC10
■
Throughput: Each unit of data (symbol) consists of 10 bits
because each character requires one start bit and one stop bit
and eight bits of data. At 2400 baud, this gives a throughput of
240 bytes/sec.
240 bytes/sec = 4.167 ms/byte = 66.6 ms/16 byte-packet Eq. 1
Assuming back to back transmission, this corresponds to:
240 bps/16 byte-packet =15 packets per second
Eq. 2
Table 2. Powerline Transceiver (PLT) Packet Header
Field
Name
SA Type
No. of
Bits
1
DA Type
2
Service
Type
1
Seq Num
4
Header
CRC
4
Powerline Transceiver Packet
The Powerline Network Protocol defines a Powerline Transceiver (PLT) packet structure, which is used for data transfer
between nodes across the Powerline. Packet formation and data
transmission across the Powerline network is implemented internally in CY8CPLC10.
A PLT Packet is apportioned into a variable length header
(minimum 6 bytes to maximum 20 bytes) and variable length
payload (minimum 0 bytes to maximum 31 bytes).
This packet is then transmitted by the Powerline Modem PHY
and the external coupling circuit across the Powerline.
The format of the PLT packet is shown in Table 1.
Table 1. Powerline Transceiver (PLT) Packet Structure
Byte
Offset
0x00
6
5
4
3
SA DA Type Service
Type
Type
2
RSVD
1
0
Response RSVD
Destination Address
(8-bit Logical, 16-bit Extended Logical or 64-bit
Physical)
0x02
Source Address
(8-bit Logical, 16-bit Extended Logical or 64-bit
Physical)
0x04
Command
RSVD
0x05
0x06
Payload Length
Seq Num
Sequence
Number
0 - Logical Addressing
1- Physical Addressing
00 - Logical Addressing
01 - Group Addressing
10 - Physical Addressing
11 - Invalid
0 - Unacknowledged
Messaging
1 - Acknowledged Messaging
Four bit Unique Identifier for
each packet between source
and destination
Four bit CRC Value. This
enables the receiver to
suspend receiving the rest of
the packet if its header is
corrupted
The packet payload has a length of 0 to 31 bytes. Payload
content is user defined and can be read or written through I2C.
0x01
0x03
Source
Address
Type
Destination
Address
Type
Description
Payload
Bit Offset
7
Tag
Powerline Packet Header
CRC
Payload (0 to 31 Bytes)
Packet CRC
The last byte of the packet is an 8-Bit CRC value used to check
packet data integrity. This CRC calculation includes the header
and payload portions of the packet and is in addition to the
Powerline Packet Header CRC.
Addressing
The logical address of the PLC node is set through software by
the external host controller or by a remote node on the
Powerline. The logical address can also be set through hardware
with the 3-bit LOG_ADDR (Logical Address) Port (for example,
an on-board 3-bit DIP switch). However, it is overwritten when
set in software. Every PLC node also has a unique 64-bit
physical address which is used for assigning the logical
addresses.
All the address pins are logically inverted, that is, applying a high
voltage on these pins corresponds to writing a logic ‘0’ and vice
versa.
Group Membership
Powerline Transceiver Packet CRC
Packet Header
The Packet Header comprises the first six bytes of the packet
when 1-byte logical addressing is used. When 8-byte physical
addressing is used, the source and destination addresses each
contain eight bytes. In this case, the header can consist of a
maximum of 20 bytes. Unused fields marked RSVD are for future
expansion and are transmitted as bit 0. Table 2 describes the
PLT Packet Header fields in detail.
Document Number: 001-50001 Rev. *D
Group Membership enables the user to multicast messages to
select groups. The CY8CPLC10 supports two types of group
addressing.
■
Single Group Membership: The Network protocol supports up
to 256 different groups on the network in this mode. In this
mode, each PLC node can only be part of a single group. For
example, multiple PLC nodes can be part of Group 131.
■
Multiple Group Membership: The Network protocol supports
eight different groups in this mode and each PLC node can be
a part of multiple groups. For example, a single PLC node can
be a part of Group 3, Group 4, and Group 7at the same time.
Page 4 of 25
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CY8CPLC10
CY8CPLC10 Memory Map
Both these modes can also be used together for Group
membership. For example, a single PLC node can be a part of
Group 131 and also multiple groups such as Group 3, Group 4,
and Group 7.
Table 3 gives the detailed CY8CPLC10 memory location information. This information can be used for application development on an external host controller. Several PLC Commands
are instantiated from the Powerline Network Protocol based on
which memory location is written.
The Group membership ID for broadcasting messages to all
nodes in the network is 0x00.
The Service Type is always set to Unacknowledgment Mode in
Group Addressing Mode. This is to avoid Acknowledgment
flooding on the Powerline during multicast.
Table 3. CY8CPLC10 Memory Map
Offset
Register Name Access
7
6
5
4
INT_Clear INT_Polarity INT_UnableTo
TX
INT_TX_
NO_ACK
3
2
INT_TX_ INT_RX_
NO_RESP Packet_
Dropped
1
0
INT_RX_
Data_
Available
INT_TX_
Data_
Sent
0x00
INT_Enable
RW
0x01
Local_LA_
LSB
RW
8 - bit Logical Address/LSB for extended 16-bit address
0x02
Local_LA_
MSB
RW
MSB for 16-bit Extended Address
0x03
Local_Group
RW
0x04
Local_Group_Ho RW
t
0x05
PLC_Mode
RW
0x06
TX_Message_
Length
RW
Send_
Message
Repeater
0x07
TX_Config
RW
TX_SA_
Type
TX_DA_Type
0x08
TX_DA
RW
0x10
TX_CommandID RW
0x11
TX_Data
0x30
Threshold_Noise RW
Reserved
0x31
Modem_Config
RW
Reserved
0x32
TX_Gain
RW
0x33
RX_Gain
RW
0x34-0x3F Reserved
RW
0x40
RX_Message_
INFO
R
0x41
RX_SA
R
0x49
RX CommandID R
0x4a
RX_Data
R
0x69
INT_Status
R
8-bit Group Address
One Hot Encoded (e.g. if byte = 0b00010001, then member of groups #5 and #1)
TX_Enable RX_Enable
Lock_
Configuration
Disable_
BIU
Rx_
Overwrite
Set_Ext_ Promiscuous Promiscuous
Address
_MASK
_CRC_MAS
K
Payload_Length_MASK
TX_Service
_Type
TX_Retry
Remote Node Destination Address (8 bytes)
TX Command ID
RW
TX Data (31 bytes)
Auto_BIU_
Threshold
Reserved
TX_Delay
Reserved
BIU_Threshold_Constant
Modem_F Reserve
SKBW_MA
d
SK
Reserved
Reserved
Modem_BPS_MASK
TX_Gain
CMP
Reserved
PGA
Reserved
New_RX_
Msg
RX_DA_
Type
RX_SA_
Type
RX_Msg_Length
Remote Node Source Address (8 Bytes)
RX Command ID
RX Data (31 bytes)
Status_Valu
e_Change
Reserved
Status_BUSY Status_TX_ Status_TX Status_ Status_RX_ Status_TX_D
NO_ACK
_
RX_Pack Data_Availab
ata_
NO_RESP et_Dropp
le
Sent
ed
0x6A
Local_PA
R
Physical Address (8 bytes), "0x6A -> MSB"
0x72
Local_FW
R
Version Number
Document Number: 001-50001 Rev. *D
Page 5 of 25
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CY8CPLC10
Table 4 gives the description of the various fields outlined in Table 3 on page 5.
Table 4. Memory Field Description
Field Name
No. of Bits
Description
INT_Enable Register (0x00)
INT_Clear
1
0 - INT Cleared (W)
1 - INT Triggered (Set Internally)
INT_Polarity
1
0 - Active High
1 - Active Low
INT_UnableToTX
1
Enable Interrupt for BIU Timeout and the Modem is
unable to Transmit if Disable BIU = 0
INT_TX_NO_ACK
1
Enable Interrupt for no acknowledgment received if
Service Type = 1 (Ack Mode)
INT_TX_NO_RESP
1
Enable Interrupt for No Response Received
INT_RX_Packet_Dropped
1
Enable Interrupt when RX Packet is dropped because
RX Buffer is full
INT_RX_Data_Available
1
Enable Interrupt when RX buffer has new data
INT_TX_Data_Sent
1
Enable Interrupt when TX data is sent successfully
TX_Enable
1
0 - TX Disabled (Can send ACKs only)
1 - TX Enabled
RX_Enable
1
0 - RX Disabled (Can Receive ACKs only)
1 - RX Enabled
Lock_Configuration
1
0 - Allow Remote Access to change config (TX Enable,
Ext Address, Disable BIU, Threshold Value, Logical
Address, Group Membership)
1 - Lock Remote Access to change config
Disable_BIU
1
0 - Enables Band-In-Use
1 - Disables Band-In-Use
RX_Overwrite
1
0 - If RX Buffer is full, new RX Message is dropped
1 - If RX Buffer is full, new RX Message overwrites RX
Buffer
Set_Ext_Address
1
0 - 8-bit Addressing Mode
1 - Extended 16-bit Addressing Mode
Note: This mode should be the same in all the devices
in the network
Promiscuous_MASK
1
0 - Drops the RX Message if Destination Address does
not match the Local Address
1- Ignores Destination Address match and accepts all
CRC-verified RX Messages
Promiscuous_CRC_MASK
1
0 - Drops the RX Message if CRC fails
1- Ignores CRC and accepts all RX Messages if Destination Address matches Local Address
PLC_Mode Register (0x05)
TX_Message_Length Register (0x06)
Send_Message
1
0 - Transmitter is idle. Automatically cleared after each
Transmit
1 - Triggers the Transmit to send message in TX Data
across Powerline
Note: The registers TX Config, TX Destination
Address, TX Command ID and TX Data need to be set
before the user sets this bit to Logic 1
Payload_Length_MASK
5
5-bit value for variable payload length. The payload
length can vary from 0 to 31.
TX_Configuration Register (0x07)
Document Number: 001-50001 Rev. *D
Page 6 of 25
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CY8CPLC10
Table 4. Memory Field Description (continued)
Field Name
No. of Bits
Description
TX_Config Register(0x07.)
TX_SA_Type
1
0 - Logical Address
1 - Physical Address
TX_DA_Type
2
00 - Logical Address
01 - Group Address
10 - Physical Address
11 - Invalid
TX_Service_Type
1
0 - Unacknowledgement mode
1 - Acknowledgement Mode
TX_Retry
4
4-bit value for variable TX Retry Count
TX_DA Register (0x08 - 0x0F)
8-bit Logical Address
0x08
16-bit Logical Address
0x08 - LSB
0x09 - MSB
64-bit Physical Address
0x08 - MSB
|
0x0F - LSB
Threshold_Noise Register (0x30)
Auto_BIU_Threshold
1
0 - Auto Set Threshold is disabled
1 - Auto Set Threshold is enabled. This state overrides
the Threshold Values in Register 0x30.
BIU_Threshold_Constant
3
0000 - 64 dBuV
0001 - 70 dBuV
0010 - 76 dBuV
0011 - 83 dBuV
0100 - 85 dBuV
0101 - 88 dBuV
0110 - 91 dBuV
0111 - 93 dBuV
Modem_Config Register (0x31)
TX_Delay
2
00 - 6 ms
01 - 12 ms
10 - 18 ms
11 - 24 ms
Modem_FSK_BW_MASK
1
0 - Logic '0' - 133.3kHz
Logic '1' - 131.8kHz
1 - Logic '0' - 133.3kHz
Logic '1' - 130.4kHz
Modem_BPS_MASK
2
00 - 600bps
01 - 1200bps
10 - 1800bps
11 - 2400bps (default)
TX_Gain Register (0x32)
Document Number: 001-50001 Rev. *D
Page 7 of 25
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CY8CPLC10
Table 4. Memory Field Description (continued)
Field Name
TX_Gain
No. of Bits
4
Description
0000 - 0.008
0001 - 0.012
0010 - 0.020
0011 - 0.027
0100 - 0.039
0101 - 0.055
0110 - 0.078
0111 - 0.109
1000 - 0.156
1001 - 0.219
1010 - 0.313
1011 - 0.375
1100 - 0.500
1101 - 0.711
1110 - 1.000
RX_Gain Register (0x33)
CMP
3
000 - 0.021
001 - 0.042
010 - 0.062
011 - 0.125
100 - 0.250
101 - 0.375
110 - 0.500
111 - 0.625
PGA
3
000 - 1.0
001 - 1.0
010 - 2.0
011 - 4.0
100 - 8.0
101 - 16.0
110 - 24.0
111 - 48.0
New_RX_Msg
1
0 - No Packet received
1 - New Packet received
Note: User sets this bit to Logic 0 after reading the RX
Message. This allows the device to receive a new RX
message
RX_DA_Type
1
0 - Logical / Physical Addressing
1 - Group Addressing
RX_SA_Type
1
0 - Logical Address
1 - Physical Address
RX_Msg_Length
5
5-bit value for variable payload length. The payload
length can vary from 0 to 31.
RX_Message_INFO Register (0x40)
RX_SA Register (0x41 - 0x48)
8-bit Logical Address
0x41
16-bit Logical Address
0x41 - LSB
0x42 - MSB
64-bit Physical Address
0x41 - MSB
|
0x48 - LSB
INT_Status Register (0x69)
Note: This register is cleared when the user sets INT_Clear to Logic 0
Document Number: 001-50001 Rev. *D
Page 8 of 25
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CY8CPLC10
Table 4. Memory Field Description (continued)
Field Name
No. of Bits
Description
Status_Value_Change
1
0 - No Change
1 - Change
Status_BUSY
1
0 - No BIU Timeout
1- BIU Timeout and the Modem is unable to Transmit,
if Disable BIU = 0
Status_TX_NO_ACK
1
If Service Type = 1 (ACK Mode)
0 - ACK Received (when TX Data sent = 1)
1 - No ACK received (when TX Data sent = 0)
Note: The timeout window for receiving the ACK is
500ms
Status_TX_NO_RESP
1
0 - Response Received (when TX Data sent = 1)
1 - No Response Received (when TX Data sent = 0)
Note:The timeout window for receiving Responses is
3s
Status_RX_Packet_Dropped
1
If RX Overwrite = 0
0 - No RX Packet is dropped
1- RX Packet is dropped because RX Buffer is full
Status_RX_Data_Available
1
0 - No new data available in RX buffer
1- RX buffer has new data available
Status_TX_Data_Sent
1
0 - No TX data sent
1- TX data sent successfully
Document Number: 001-50001 Rev. *D
Page 9 of 25
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CY8CPLC10
External Host Application
Remote Commands
The application residing on the external host microcontroller has
direct access to the local PLC memory over I2C. The I2C communication enables the host controller to instantiate several PLC
functions by reading or writing to the appropriate memory
locations in the PLC chip. Thus the host application can
configure the CY8CPLC10, read status and configuration information, and transmit data to remote Powerline nodes. Refer to
the CY8CPLC10 application note (AN52478) on how to build a
PLC command set using the CY8CPLC10 memory map. The
device has a dedicated pin (I2C_ADDR) for selecting the I2C
slave address while communicating with the external controller.
The two I2C slave addresses available are 0x01 and 0x7F.
These commands initiate transmission over the Powerline to a
remote PLC node. These commands when instantiated over I2C
enable the host application to send and receive data over
Powerline. Along with the data payload, the I2C packets also
carry additional information for the Powerline transmission to a
remote node:
■
Destination address (8-bit logical, 16-bit extended logical, or
64-bit physical)
■
Transmission retries
■
Payload length
The PLC commands can be classified into two types based on
which Powerline node they are designated to: local node or
remote node.
Variable header and payload definitions enable flexibility in application development. The available remote commands are
described in Table 5 with the respective Command IDs.
Local Commands
EEPROM Back Up for Remote Reset
These commands act solely on the attached local PLC device.
No transmissions are sent over the Powerline to a remote PLC
device when executing these local transceiver commands.
These commands are used for configuring the local PLC node
such as setting the local logical address or reading the status and
configuration information.
The device also has an EEPROM to back up Memory Registers
0x00-0x05 and 0x30-0x32. When the device is reset remotely by
the SetRemote_Reset command (described in Table 5), it clears
its memory map and loads from the EEPROM and returns to idle
mode.
Table 5. Remote Commands
Cmd ID
Command Name
Description
Payload (TX Data)
Response (RX Data)
0x01
SetRemote_TXEnable
Sets the TX Enable bit in the 0 - Disable Remote TX
PLC Mode Register. Rest of the 1 - Enable Remote TX
PLC Mode register is
unaffected
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x02
SetRemote_Reset
Reset the Remote Node
Configuration
None
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x03
SetRemote_ExtendedAddr
Set the Addressing to
Extended Addressing Mode
None
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x04
SetRemote_LogicalAddr
Assigns the specified logical
address to the remote PLC
node
If Ext Address = 0,
Payload = 8-bit Logical
Address
If Ext Address = 1,
Payload = 16-bit
Logical Address
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x05
GetRemote_LogicalAddr
Get the Logical Address of the None
remote PLC node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
{If Ext Address = 0, Response
= 8-bit Logical Address
If Ext Address = 1, Response
= 16-bit Logical Address}
0x06
GetRemote_PhysicalAddr
Get the Physical Address of the None
remote PLC node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = 64-bit Physical
Address
Document Number: 001-50001 Rev. *D
Page 10 of 25
[+] Feedback
CY8CPLC10
Table 5. Remote Commands (continued)
Cmd ID
Command Name
Description
Payload (TX Data)
0x07
GetRemote_State
Request data from a Remote
PLC node
0x08
GetRemote_Version
Get the Version Number of the None
Remote Node
If TX Enable = 0, Response =
None
If TX Enable = 1, Response =
Remote Version register
0x09
SendRemote_Data
Transmit data to a Remote
Node.
Payload = Local TX
Data
If Local Service Type = 0,
Response = None
If Local Service Type = 1,
Response = Ack
0x0A
RequestRemote_Data
Request data from a Remote
Node
Payload = Local TX
Data
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = Remote TX Data
0x0B
ResponseRemote_Data
Transmit response data to a
Remote Node.
Payload = Local TX
Data
None
0x0C
SetRemote_BIU
Enables/Disables BIU function- 0 - Enable Remote BIU If Remote Lock Config = 0,
ality at the remote node
1 - Disable Remote BIU Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x0D
SetRemote_ThresholdValue
Sets the Threshold Value at the 3-bit Remote
Remote node
Threshold Value
0x0E
SetRemote_GroupMembershi Sets the Group Membership of Byte0 - Remote SIngle
p
the Remote node
Group Membership
Address
Byte1- Remote Multiple
Group Membership
Address
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
0x0F
GetRemote_GroupMembershi Gets the Group Membership of None
p
the Remote node
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response =
Byte0 - Remote SIngle Group
Membership Address
Byte1- Remote Multiple Group
Membership Address
0x10 0x2F
Reserved
0x30 0xFF
User Defined Command Set
Document Number: 001-50001 Rev. *D
None
Response (RX Data)
If Remote TX Enable = 0,
Response = None
If Remote TX Enable = 1,
Response = Remote PLC Mode
register
If Remote Lock Config = 0,
Response = 00 (Success)
If Remote Lock Config = 1,
Response = 01 (Denied)
Page 11 of 25
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CY8CPLC10
Target Applications
Lighting Control
CY8CPLC10 enables control of incandescent, sodium vapor, fluorescent, and LED lighting fixtures over the existing Powerline.
Cypress’s Powerline communication solution easily integrates with wall-switch dimmers and lamp and appliance modules, enabling
on and off, dimming, color mixing, and tunable white light control. When operating in master mode, the CY8CPLC10 can control
individual or a group of lighting fixtures in a home or a commercial building. Elaborate lighting scenes can be created using application
software. Household lighting fixtures can also be programmed to turn on and off at user defined intervals using a PC based Graphical
User Interface.
Figure 5. Powerline Communication for Home Lighting
Figure 6. Powerline Communication for Pool Lighting
Document Number: 001-50001 Rev. *D
Page 12 of 25
[+] Feedback
CY8CPLC10
Smart Energy Management
Using the CY8CPLC10, individual panels in a solar array can transmit diagnostic data over the existing DC powerlines. An Array
Diagnostic Unit Controller can communicate with individual solar panels to have specific diagnostic information probed. When the
diagnostic data is collected by the controller, it is transmitted across the Powerline to a data monitoring console. This makes it possible
to acquire and transmit real time data regarding energy output of individual panels to the array controller and subsequently even to a
solar farm control station over the Powerline.
Figure 7. Powerline Communication for Smart Energy Management (Solar Diagnostics)
Document Number: 001-50001 Rev. *D
Page 13 of 25
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CY8CPLC10
Automatic Meter Reading
The CY8CPLC10 can be designed in electric meters in household and industrial environments to transmit power usage information
to a centralized billing system. The Cypress Powerline communication solution is ideally suited to handle multiple data sources
because of the in-built Network Protocol Stack that enables individual addressing of multiple nodes on the same Powerline. In physical
addressing mode, up to 264 power meters can transmit usage statistics to the local billing center. Application Layer software can be
used to provide real time usage statistics to a customer. Energy utilities can improve customer service and control meter reading costs,
especially in areas where accessing meters is difficult or unsafe, while making the invoicing process more efficient.
Figure 8. Powerline Communication for Automatic Meter Reading
Industrial Signage
An entire array of new convenience and advanced control features are available in automobiles today. It is projected that a high feature
content car cannot have enough space to contain multiple wiring segments and connectors without compromising power loss and
safety. One solution is to reduce the number of cables by using existing Powerline as the transmission medium of digital control signals.
The CY8CPLC10 enables control of Automotive LED strobe, beacon, tail lights, and indicators over the existing direct current (DC)
12V to 42V battery Powerline. Combined with Cypress’s EZ-Color lighting solution, dimming and color mixing of LED based automotive
lighting fixtures in applications such as mobile LED displays is possible.
Figure 9. Powerline Communication for Industrial Signage
Document Number: 001-50001 Rev. *D
Page 14 of 25
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CY8CPLC10
Pinouts
Figure 10. CY8CPLC10 28-Pin SSOP
RX_LED
1
28
NC
FSK_OUT
CLKSEL
TX_SHUTDOWN
LOG_ADDR_0
2
27
3
26
4
25
5
24
6
23
LOG_ADDR_1
LOG_ADDR_2
7
22
8
21
NC
I2C_SCL
9
20
10
19
I2C_SDA
XTAL_STABLITY
11
18
12
17
13
16
14
15
XTAL_IN
VSS
VDD
FSK_IN
I2C_ADDR
RSVD
RSVD
HOST_INT
AGND
RXCOMP_IN
RXCOMP_OUT
RESET
BIU_LED
EXTCLK
TX_LED
XTAL_OUT
Table 6. Pin Definitions
Pin
Number
Pin Name
I/O
Description
1
RX_LED
Output
RX Indicator LED
2
NC
Not Connected
Pin not connected
3
FSK_OUT
Analog Output
Analog FSK Output. This signal is coupled to the powerline through an
external coupling circuit
4
CLKSEL
Input (Internal Pull up) Clock Source Select
Logic ‘0’ – External Clock Oscillator (EXTCLK) selected
Logic ‘1’ – External Crystal (XTAL_IN, XTAL_OUT) selected
5
TX_SHUTDOWN
Output
6
LOG_ADDR_0
Input (Internal Pull up) Connected to the Least Significant Bit of the 3-bit Logical Address. This is
an inverted pin; applying a high voltage on this pin corresponds to writing
a logic ‘0’ and vice versa.
7
LOG_ADDR_1
Input (Internal Pull up) Connected to the 2nd Most Significant Bit of the 3-bit Logical Address. This
is an inverted pin; applying a high voltage on this pin corresponds to writing
a logic ‘0’ and vice versa.
8
LOG_ADDR_2
Input (Internal Pull up) Connected to the Most Significant Bit of the 8-bit DIP Switch. This is an
inverted pin; applying a high voltage on this pin corresponds to writing a
logic ‘0’ and vice versa.
9
NC
Not Connected
Pin not connected
10
I2C_SCL
Input
I2C Serial Clock
11
I2C_SDA
Input/Output
I2C Serial Data
12
XTAL_STABILITY
Input/Output
External Crystal Stability
13
XTAL_IN
Input
External Crystal Input. This is the input clock from an external crystal oscillator
14
Vss
Ground
Ground
15
XTAL_OUT
Output
External Crystal Output. This pin is used along with XTAL_IN to connect
to the external oscillator
Document Number: 001-50001 Rev. *D
Output to Disable Transmit circuitry during Receive Mode. Logic ‘0’ - TX
Shutdown
Page 15 of 25
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CY8CPLC10
Table 6. Pin Definitions (continued)
Pin
Number
Pin Name
I/O
Output
Description
16
TX_LED
TX Indicator LED
17
EXTCLK
Input
Optional external 24 MHz clock oscillator input
18
BIU_LED
Output
BIU Indicator LED
19
RESET
Reset
Reset Pin
20
RXCOMP_OUT
Analog Output
Analog Output to the external Low Pass Filter circuitry
21
RXCOMP_IN
Analog Input
Analog Input from the external Low Pass Filter circuitry
22
AGND
Ground
Analog Ground
23
HOST_INT
Output
Interrupt Output to Host Controller to enable interrupt based serial communication
24
RSVD
Reserved
Reserved Pin
Reserved Pin
25
RSVD
Reserved
26
I2C_ADDR
Input (Internal Pull up) Set I2C Slave Address.
Logic ‘0’ - Slave Address ‘0x01’
Logic ‘1’ - Slave Address ‘0x7F’
This is an inverted pin i.e. applying a high voltage on this pin corresponds
to writing a logic ‘0’ and vice versa.
27
FSK_IN
Input
Analog FSK Input.This is the input signal from the Powerline.
28
VDD
Power
Supply Voltage. 5V ± 10%
Document Number: 001-50001 Rev. *D
Page 16 of 25
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CY8CPLC10
Electrical Specifications
This chapter presents the DC and AC electrical specifications of the CY8CPLC10 PLC device. For the most up to date electrical
specifications, confirm that you have the most recent data sheet by going to the web at http://www.cypress.com.
Specifications are valid for -40oC ≤ TA ≤ 85oC and TJ ≤ 100oC, except where noted.
The following table lists the units of measure that are used in this chapter.
Table 7. Units of Measure
Symbol
C
dB
fF
Hz
KB
Kbit
kHz
kΩ
MHz
MΩ
μA
μF
μH
μs
μV
μVrms
o
Unit of Measure
degree Celsius
decibels
femto farad
hertz
1024 bytes
1024 bits
kilohertz
kilohm
megahertz
megaohm
microampere
microfarad
microhenry
microsecond
microvolts
microvolts root-mean-square
Symbol
μW
mA
ms
mV
nA
ns
nV
Ω
pA
pF
pp
ppm
ps
sps
s
V
Unit of Measure
microwatts
milli-ampere
milli-second
milli-volts
nanoampere
nanosecond
nanovolts
ohm
picoampere
picofarad
peak-to-peak
parts per million
picosecond
samples per second
sigma: one standard deviation
volts
Absolute Maximum Ratings
Table 8. Absolute Maximum Ratings
Symbol
TSTG
Description
Storage Temperature
Min
-55
Typ
25
Max
+100
Units
o
C
TA
-40
–
+85
oC
Vdd
VIO
Ambient Temperature with Power
Applied
Supply Voltage on Vdd Relative to Vss
DC Input Voltage
–
–
DC Voltage Applied to Tristate
IMIO
Maximum Current into any Input/Output
Pin
Maximum Current into any Input/Output
Pin Configured as Analog Driver
Electro Static Discharge Voltage
Latch up Current
–
+6.0
Vdd +
0.5
Vdd +
0.5
+50
V
V
VIOZ
-0.5
Vss 0.5
Vss 0.5
-25
mA
-50
–
+50
mA
2000
–
–
–
–
200
V
mA
IMAIO
ESD
LU
Document Number: 001-50001 Rev. *D
–
Notes
Higher storage temperatures reduces
data retention time. Recommended
storage temperature is +25oC ± 25oC.
Extended duration storage temperatures above 65oC degrades reliability.
V
Human Body Model ESD.
Page 17 of 25
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CY8CPLC10
Operating Temperature
Table 9. Operating Temperature
Symbol
TA
TJ
Description
Ambient Temperature
Junction Temperature
Min
-40
-40
Typ
–
–
Max
+85
+100
Units
o
C
o
C
Notes
The temperature rise from ambient
to junction is package specific. See
Thermal Impedances.The user
must limit the power consumption to
comply with this requirement.
DC Electrical Characteristics
DC Power Supply
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 10. DC Power Supply
Symbol
VDD
IDD (TX Mode)
IDD (RX Mode)
Description
Supply Voltage
Supply current (TX Mode)
Supply current (RX Mode)
Min
4.75
Typ
–
30
41
Max
5.25
Units
V
mA
mA
Notes
Conditions are 5.0V, TA = 25°C
Conditions are 5.0V, TA = 25°C
DC I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 11. DC I/O Specifications
Symbol
RPU
RPD
VOH
VOL
VIL
VIH
VH
IIL
CIN
Description
Pull Up Resistor
Pull Down Resistor
High Output Level
Low Output Level
Input Low Level
Input High Level
Input Hysterisis
Input Leakage (Absolute Value)
Capacitive Load on Pins as Input
COUT
Capacitive Load on Pins as Output
Document Number: 001-50001 Rev. *D
Min
4
4
Vdd - 1.0
–
–
2.1
–
–
–
Typ
5.6
5.6
–
–
–
–
60
1
3.5
Max
8
8
–
0.75
0.8
–
–
10
Units
kΩ
kΩ
V
V
V
V
mV
nA
pF
–
3.5
10
pF
Notes
IOH = 10 mA
IOL = 25 mA
Gross tested to 1 μA.
Package and pin dependent.
Temp = 25oC.
Package and pin dependent.
Temp = 25oC.
Page 18 of 25
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CY8CPLC10
AC Electrical Characteristics
AC Chip-Level Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Note See the individual user module data sheets for information on maximum frequencies for user modules.
Table 12. AC Chip-Level Specifications
Symbol
F32K2
Description
External Crystal Oscillator
Min
–
Typ
32.768
Max
–
Units
kHz
TOS
TOSACC
External Crystal Oscillator Startup to 1%
External Crystal Oscillator Startup to 100 ppm
–
–
250
300
500
600
ms
ms
TXRST
TRAMP
External Reset Pulse Width
Supply Ramp Time
10
0
–
–
–
–
μs
μs
Notes
Accuracy is capacitor and
crystal dependent. 50% duty
cycle.
The crystal oscillator
frequency is within 100 ppm of
its final value by the end of the
Tosacc period. Correct
operation assumes a properly
loaded 1 uW maximum drive
level 32.768 kHz crystal, -40
oC £ T £ 85 oC.
A
AC I/O Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 13. AC I/O Specifications
Symbol
TRiseS
TFallS
Description
Rise Time, Cload = 50 pF
Fall Time, Cload = 50 pF
Min
10
10
Typ
27
22
Max
–
–
Units[1]
ns
ns
Notes
10% - 90%
10% - 90%
Figure 11. I/O Timing Diagram
90%
GPIO
Pin
Output
Voltage
10%
TRiseF
TRiseS
Document Number: 001-50001 Rev. *D
TFallF
TFallS
Page 19 of 25
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CY8CPLC10
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the voltage and temperature ranges: 4.75V to 5.25V
and -40°C ≤ TA ≤ 85°C, respectively. Typical parameters apply to 5V at 25°C and are for design guidance only.
Table 14. AC Characteristics of the I2C SDA and SCL Pins
Symbol
FSCLI2C
THDSTAI2C
TLOWI2C
THIGHI2C
TSUSTAI2C
THDDATI2C
TSUDATI2C
TSUSTOI2C
TBUFI2C
TSPI2C
Description
SCL Clock Frequency
Hold Time (repeated) START Condition.
After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START
Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and
START Condition
Pulse Width of spikes are suppressed by
the input filter.
Standard Mode
Min
Max
0
100
4.0
–
Fast Mode
Min
Max
0
400
0.6
–
Units
Notes
kHz
μs
4.7
4.0
4.7
–
–
–
1.3
0.6
0.6
–
–
–
μs
μs
μs
0
250
4.0
4.7
–
–
–
–
0
100[2]
0.6
1.3
–
–
–
–
μs
ns
μs
μs
–
–
0
50
ns
Figure 12. Definition for Timing for Fast and Standard Mode on the I2C Bus Packaging Dimensions
SDA
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
SCL
S THDSTAI2C THDDATI2C THIGHI2C
TSUSTAI2C
Sr
TSUSTOI2C
P
S
Notes
1. 50 ns minimum input pulse width is based on the input synchronizers running at 24 MHz (42 ns nominal period)
2. A Fast-Mode I2C-bus device can be used in a Standard-Mode I2C-bus system, but the requirement tSU;DAT Š 250 ns must then be met. This is automatically the
case if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit
to the SDA line trmax + tSU;DAT = 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
Document Number: 001-50001 Rev. *D
Page 20 of 25
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CY8CPLC10
Packaging Information
This section illustrates the packaging specifications for the CY8CPLC10 PLC device, along with the thermal impedances for the
package and the typical package capacitance on crystal pins.
Figure 13. 28-Pin (210-Mil) SSOP
51-85079 *C
Capacitance on Crystal Pins
Thermal Impedances
Table 15. Thermal Impedances per
Package[4]
Package
28 SSOP
Table 16. Typical Package Capacitance on Crystal Pins
Typical θJA[3]
94 oC/W
Package
28 SSOP
Package Capacitance
2.8 pF
Solder Reflow Peak Temperature
Following is the minimum solder reflow peak temperature to achieve good solderability.
Table 17. Solder Reflow Peak Temperature
Package
28 SSOP
Minimum Peak Temperature[5]
o
240 C
Maximum Peak Temperature
260oC
Notes
3. TJ = TA + POWER x θJA
4. To achieve the thermal impedance specified for the QFN package, the center thermal pad should be soldered to the PCB ground plane.
5. Higher temperatures may be required based on the solder melting point. Typical temperatures for solder are 220 ± 5oC with Sn-Pb or 245 ± 5oC with Sn-Ag-Cu
paste. Refer to the solder manufacturer specifications.
Document Number: 001-50001 Rev. *D
Page 21 of 25
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CY8CPLC10
Evaluation Tools
■
28-Pin CY8C27443-24PXI PDIP PSoC Device Sample
CY3272-PLC HV Evaluation Kit
■
PSoC Designer Software CD
The CY3272-PLC is for evaluating, prototyping, and development with the CY8CPLC10. The I2C interface enables users
to develop applications on an external micro in order to communicate over Powerline. The hardware comprises of the High
Voltage coupling circuit for 110V AC to 230V AC Powerline which
is compliant with the CENELEC/FCC standards. This board also
has an on-board Switch Mode Power Supply. The kit comprises:
■
Getting Started Guide
■
USB 2.0 Cable
■
High Voltage (110 to 230V AC) PLC Board
■
CY8CPLC10-28PVXI (28SSOP)
■
Software CD
■
Supporting Literature
CY3273-PLC LV Evaluation Kit
The CY3273-PLC is for evaluating, prototyping and development
with the CY8CPLC10. The I2C interface enables users to
develop applications on an external micro in order to communicate over Powerline. The hardware comprises of the Low
Voltage coupling circuit for 12 to 24V AC/DC Powerline. This
board also has a Linear Power Supply. The kit comprises:
■
Low Voltage (12-24V AC/DC) PLC Board
■
CY8CPLC10-28PVXI (28SSOP)
■
Software CD
■
Supporting Literature
CY3210-MiniProg1
The CY3210-MiniProg1 kit enables the user to program PSoC
devices via the MiniProg1 programming unit. The MiniProg is a
small, compact prototyping programmer that connects to the PC
through a provided USB 2.0 cable. The kit includes:
■
MiniProg Programming Unit
■
MiniEval Socket Programming and Evaluation Board
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample
Document Number: 001-50001 Rev. *D
CY3210-PSoCEval1
The CY3210-PSoCEval1 kit features an evaluation board and
the MiniProg1 programming unit. The evaluation board includes
an LCD module, potentiometer, LEDs, and plenty of bread
boarding space to meet all your evaluation needs. The kit
includes:
■
Evaluation Board with LCD Module
■
MiniProg Programming Unit
■
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample (2)
■
PSoC Designer Software CD
■
Getting Started Guide
■
USB 2.0 Cable
CY3214-PSoCEvalUSB
The CY3214-PSoCEvalUSB evaluation kit features a development board for the CY8C24794-24LFXI PSoC device. Special
features of the board include both USB and capacitive sensing
development and debugging support. This evaluation board also
includes an LCD module, potentiometer, LEDs, an enunciator,
and plenty of bread boarding space to meet all your evaluation
needs. The kit includes:
■
PSoCEvalUSB Board
■
LCD Module
■
MIniProg Programming Unit
■
Mini USB Cable
■
PSoC Designer and Example Projects CD
■
Getting Started Guide
■
Wire Pack
Page 22 of 25
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CY8CPLC10
Development Tools
The development kits do not have on-board Powerline capability,
but can be used with a PLC kit for development purposes. All
development tools and development kits are sold at the Cypress
Online Store.
CY3215-DK Basic Development Kit
The CY3215-DK is for prototyping and development with PSoC
Designer. This kit can be used in conjunction with the PLC kits
to support in-circuit emulation. The software interface enables
users to run, halt, and single step the processor and view the
content of specific memory locations. PSoC Designer also
supports the advanced emulation features. The kit includes:
Device Programmers
All device programmers are purchased from the Cypress Online
Store.
CY3216 Modular Programmer
The CY3216 Modular Programmer kit features a modular
programmer and the MiniProg1 programming unit. The modular
programmer includes three programming module cards and
supports multiple Cypress products. The kit includes:
■
Modular Programmer Base
■
3 Programming Module Cards
■
MiniProg Programming Unit
■
PSoC Designer Software CD
■
PSoC Designer Software CD
■
ICE-Cube In-Circuit Emulator
■
Getting Started Guide
■
ICE Flex-Pod for CY8C29x66 Family
■
USB 2.0 Cable
■
Cat-5 Adapter
■
Mini-Eval Programming Board
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
iMAGEcraft C Compiler (Registration Required)
■
ISSP Cable
■
USB 2.0 Cable and Blue Cat-5 Cable
■
2 CY8C29466-24PXI 28-PDIP Chip Samples
CY3207 ISSP In-System Serial Programmer (ISSP)
The CY3207ISSP is a production programmer. It includes
protection circuitry and an industrial case that is more robust than
the MiniProg in a production programming environment.
Note that CY3207ISSP needs special software and is not
compatible with PSoC Programmer. The kit includes:
■
CY3207 Programmer Unit
■
PSoC ISSP Software CD
■
110 ~ 240V Power Supply, Euro-Plug Adapter
■
USB 2.0 Cable
Third Party Tools
Several tools are specially designed by the following third party
vendors to accompany PSoC devices during development and
production. Specific details of each of these tools are found at
http://www.cypress.com under Design > Evaluation Boards.
Build a PSoC Emulator into Your Board
For details on emulating the circuit before going to volume production using an on-chip debug (OCD) non-production PSoC
device, see Application Note “Debugging - Build a PSoC
Emulator
into
Your
Board
AN2323”
at
http://www.cypress.com/design/AN2323.
Document Number: 001-50001 Rev. *D
Page 23 of 25
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CY8CPLC10
Ordering Information
The following table lists the CY8CPLC10 PLC device’s key package features and ordering codes.
Table 18. CY8CPLC10 PLC Device Key Features and Ordering Information
Package
28-Pin (210 Mil) SSOP
28-Pin (210 Mil) SSOP
(Tape and Reel)
Ordering
Code
CY8CPLC10-28PVXI
CY8CPLC10-28PVXIT
Flash
(Bytes)
32K
32K
RAM
(Bytes)
2K
2K
Switch Mode Pump Temperature
Range
Yes
-40C to +85C
Yes
-40C to +85C
XRES Pin
Yes
Yes
Ordering Code Definitions
CY 8 C PLC 10 - xx xxx
Package Type:
PVX = SSOP Pb-Free
Thermal Rating:
I = Industrial
Pin Count: 28
Fixed Function Device
Family Code: Powerline Communication Solution
Technology Code: C = CMOS
Marketing Code: 8 = Cypress M8C Core
Company ID: CY = Cypress
Document Number: 001-50001 Rev. *D
Page 24 of 25
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CY8CPLC10
Document History Page
Document Title: CY8CPLC10 Powerline Communication Solution
Document Number: 001-50001
Rev.
ECN No.
Orig. of
Change
Submission
Date
Description of Change
**
2606671
GHH/PYRS
11/13/08
New Datasheet
*A
2662761
GHH/AESA
02/20/09
Added:
- Repeater Functionality
- AGC Functionality
- Optional TX Filter Bypass
- Configurable Baud Rates and FSK Frequencies
- Configurable RX Gain
*B
2748542
GHH/PYRS
*C
2752799
GHH
*D
2754780
GHH/PYRS
08/05/2009 Converted from Preliminary to Final
Modified:
- Memory Map Structure (Added TX_Gain Register)
- Pinout (Added option for external clocking: EXTCLK)
Removed:
- Repeater Functionality
- Optional TX Filter Bypass
08/17/2009 Posting to external web.
08/21/2009 Added
- Optional external clock oscillator
- Suppy current for TX and RX modes
Removed
- Noise strength from Memory map in Table3
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© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without
the express written permission of Cypress.
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer
assumes all risk of such use and in doing so indemnifies Cypress against all charges.
Use may be limited by and subject to the applicable Cypress software license agreement.
Document Number: 001-50001 Rev. *D
Revised August 21, 2009
Page # of 25
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