DAC8501 SBAS212A – APRIL 2001 – REVISED FEBRUARY 2003 Low-Power, Rail-to-Rail Output, 16-Bit Serial Input DIGITAL-TO-ANALOG CONVERTER FEATURES DESCRIPTION ● microPOWER OPERATION: 250µA at 5V ● MULTIPLYING-MODE BANDWIDTH: 350kHz ● POWER-ON RESET TO ZERO ● POWER SUPPLY: +2.7V to +5.5V ● ENSURED MONOTONIC BY DESIGN ● SETTLING TIME: 10µs to ±0.003% FSR ● LOW-POWER SERIAL INTERFACE WITH SCHMITT-TRIGGERED INPUTS ● ON-CHIP OUTPUT BUFFER AMPLIFIER, RAIL-TO-RAIL OPERATION ● SYNC INTERRUPT FACILITY ● MSOP-8 PACKAGE The DAC8501 is a low-power, single, 16-bit buffered voltage output Digital-to-Analog Converter (DAC) optimized for multiplying operation. Its on-chip precision output amplifier allows rail-to-rail output swing to be achieved. The DAC8501 uses a versatile 3-wire serial interface that operates at clock rates up to 30MHz and is compatible with standard SPI™, QSPI™, Microwire™, and Digital Signal Processor (DSP) interfaces. The low-power consumption of this part in normal operation makes it ideally suited to portable battery-operated equipment. The power consumption is 1.2mW at 5V reducing to 1µW in power-down mode. APPLICATIONS ● ● ● ● ● ● The DAC8501 requires an external reference voltage to set the output range of the DAC. The DAC8501 incorporates a power-on reset circuit that ensures that the DAC output powers up at 0V and remains there until a valid write takes place to the device. The DAC8501 contains a power-down feature, accessed over the serial interface, that reduces the current consumption of the device to 200nA at 5V. PROCESS CONTROL DATA ACQUISITION SYSTEMS CLOSED-LOOP SERVO-CONTROL PC PERIPHERALS PORTABLE INSTRUMENTATION PROGRAMMABLE ATTENUATION The DAC8501 is available in an MSOP-8 package. SPI and QSPI are registered trademarks of Motorola. Microwire is a registered trademark of National Semiconductor. VDD VFB VREF Ref (+) VOUT 16-Bit DAC 16 DAC Register 16 SYNC SCLK DIN Shift Register Power-Down Control Logic Resistor Network GND Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2001-2003, Texas Instruments Incorporated ABSOLUTE MAXIMUM RATINGS(1) VDD to GND ........................................................................... –0.3V to +6V Digital Input Voltage to GND ................................. –0.3V to +VDD + 0.3V VOUT to GND .......................................................... –0.3V to +VDD + 0.3V VREF to GND ........................................................... –0.3V to +VDD + 0.3V VFB to GND ............................................................. –0.3V to +VDD + 0.3V Operating Temperature Range ...................................... –40°C to +105°C Storage Temperature Range ......................................... –65°C to +150°C Junction Temperature Range (TJ max) ........................................ +150°C Power Dissipation ........................................................ (TJ max — TA)/θJA θJA Thermal Impedance ......................................................... 206°C/W θJC Thermal Impedance ........................................................... 44°C/W Lead Temperature, Soldering: Vapor Phase (60s) ............................................................... +215°C Infrared (15s) ........................................................................ +220°C NOTE: (1) Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to absolute maximum conditions for extended periods may affect device reliability. ELECTROSTATIC DISCHARGE SENSITIVITY This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more susceptible to damage because very small parametric changes could cause the device not to meet its published specifications. PACKAGE/ORDERING INFORMATION PRODUCT RELATIVE ACCURACY (LSB) DIFFERENTIAL NONLINEARITY (LSB) DAC8501E ±64 ±1 MSOP-8 " " " " SPECIFICATION TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER TRANSPORT MEDIA, QUANTITY DGK –40°C to +105°C D01 " " " DAC8501E/250 DAC8501E/2K5 Tape and Reel, 250 Tape and Reel, 2500 PACKAGE PACKAGE-LEAD DESIGNATOR(1) NOTE: (1) For the most current specifications and package information, refer to our web site at www.ti.com. PIN DESCRIPTION PIN CONFIGURATIONS Top View 2 MSOP VDD 1 8 GND VREF 2 7 DIN VFB 3 6 SCLK VOUT 4 5 SYNC DAC8501 PIN NAME DESCRIPTION 1 VDD Power-Supply Input, +2.7V to +5.5V 2 VREF Reference Voltage Input 3 VFB Feedback connection for the output amplifier. 4 VOUT Analog output voltage from DAC. The output amplifier has rail-to-rail operation. 5 SYNC Level-triggered control input (active LOW). This is the frame synchronization signal for the input data. When SYNC goes LOW, it enables the input shift register and data is transferred in on the falling edges of the following clocks. The DAC is updated following the 24th clock cycle unless SYNC is taken HIGH before this edge, in which case the rising edge of SYNC acts as an interrupt and the write sequence is ignored by the DAC8501. 6 SCLK Serial Clock Input. Data can be transferred at rates up to 30MHz. 7 DIN Serial Data Input. Data is clocked into the 24-bit input shift register on the falling edge of the serial clock input. 8 GND Ground reference point for all circuitry on the part. DAC8501 www.ti.com SBAS212A ELECTRICAL CHARACTERISTICS VDD = +2.7V to +5.5V, and –40°C to +105°C, unless otherwise specified. DAC8501E PARAMETER STATIC PERFORMANCE (1) Resolution Relative Accuracy Differential Nonlinearity Zero Code Error Full-Scale Error Gain Error Zero Code Error Drift Gain Temperature Coefficient OUTPUT CHARACTERISTICS (2) Output Voltage Range Output Voltage Settling Time Slew Rate Capacitive Load Stability Code Change Glitch Impulse Digital Feedthrough DC Output Impedance Short-Circuit Current Power-Up Time REFERENCE INPUT Reference Current CONDITIONS MIN Ensured Monotonic by Design All Zeroes Loaded to DAC Register All Ones Loaded to DAC Register +5 –0.15 ±20 ±5 0 To ±0.003% FSR 0200H to FD00H RL = 2kΩ; 0pF < CL < 200pF RL = 2kΩ; CL = 500pF 8 RL = ∞ RL = 2kΩ to Ground 1LSB Change Around Major Carry VDD = +5V VDD = +3V Coming Out of Power-Down Mode VDD = +5V Coming Out of Power-Down Mode VDD = +3V VREF = VDD = +5V VREF = VDD = +3.6V POWER EFFICIENCY IOUT/IDD = = = = +5V +3V +5V +3V Bits % of FSR LSB mV % of FSR % of FSR µV/°C ppm of FSR/°C VREF V 10 µs µs V/µs pF pF nV-s nV-s Ω mA mA 2.5 µs 5 µs 150 µA µA V kΩ 350 64 kHz kHz 0 VDD VDD VDD VDD ±0.098 ±1 ±20 ±1.25 ±1.25 UNITS 12 1 470 1000 20 0.5 1 50 20 35 20 MULTIPLYING MODE Small-Signal Bandwidth Full-Power Bandwidth POWER REQUIREMENTS VDD IDD (normal mode) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V IDD (all power-down modes) VDD = +3.6V to +5.5V VDD = +2.7V to +3.6V MAX 16 Reference Input Range Reference Input Impedance LOGIC INPUTS (2) Input Current VINL, Input LOW Voltage VINL, Input LOW Voltage VINH, Input HIGH Voltage VINH, Input HIGH Voltage Pin Capacitance TYP 45 30 VDD ±1 0.8 0.6 3 µA V V V V pF 5.5 V 2.4 2.1 2.7 DAC Active and Excluding Load Current VIH = VDD and VIL = GND VIH = VDD and VIL = GND 250 240 400 390 µA µA VIH = VDD and VIL = GND VIH = VDD and VIL = GND 0.2 0.05 1 1 µA µA ILOAD = 2mA, VDD = +5V 89 TEMPERATURE RANGE Specified Performance –40 % +105 °C NOTES: (1) Linearity calculated using a reduced code range of 485 to 64714; output unloaded. (2) Ensured by design and characterization, not production tested. DAC8501 SBAS212A www.ti.com 3 TIMING CHARACTERISTICS(1, 2) VDD = +2.7V to +5.5V; all specifications –40°C to +105°C, unless otherwise noted. DAC8501E PARAMETER t1 (3) t2 t3 t4 t5 t6 t7 t8 DESCRIPTION CONDITIONS MIN TYP MAX UNITS VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 13 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 22.5 13 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 5 5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 4.5 4.5 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 0 0 ns ns VDD = 2.7V to 3.6V VDD = 3.6V to 5.5V 50 33 ns ns SCLK Cycle Time SCLK HIGH Time SCLK LOW Time SYNC to SCLK Rising Edge Setup Time Data Setup Time Data Hold Time SCLK Falling Edge to SYNC Rising Edge Minimum SYNC HIGH Time NOTES: (1) All input signals are specified with tR = tF = 5ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2. (2) See Serial Write Operation timing diagram, below. (3) Maximum SCLK frequency is 30MHz at VDD = +3.6V to +5.5V and 20MHz at VDD = +2.7V to +3.6V. SERIAL WRITE OPERATION t1 SCLK t8 t3 t4 t2 t7 SYNC t6 t5 DIN 4 DB23 DB0 DAC8501 www.ti.com SBAS212A TYPICAL CHARACTERISTICS: VDD = +5V At TA = +25°C, and +VDD = +5V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code DLE (LSB) ZERO-SCALE ERROR vs TEMPERATURE 20 64 48 32 16 0 –16 –32 –48 –64 15 10 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Error (mV) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 5 0 –5 –10 –15 –20 –40 0 40 80 120 Temperature (°C) Digital Input Code FULL-SCALE ERROR vs TEMPERATURE IDD HISTOGRAM 20 2000 15 1500 5 Frequency Error (mV) 10 0 –5 –10 1000 500 –15 –20 –40 0 0 40 80 120 100 130 Temperature (°C) IDD (µA) DAC8501 SBAS212A 160 190 220 250 280 310 340 370 400 www.ti.com 5 TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, and +VDD = +5V, unless otherwise noted. SOURCE AND SINK CURRENT CAPABILITY SUPPLY CURRENT vs DIGITAL INPUT CODE 5 500 DAC Loaded with FFFFH 400 3 IDD (µA) VOUT (V) 4 2 1 300 200 100 DAC Loaded with 0000H 0 0 0 5 10 15 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH ISOURCE/SINK (mA) Digital Input Code POWER-SUPPLY CURRENT vs TEMPERATURE SUPPLY CURRENT vs SUPPLY VOLTAGE 350 350 300 300 250 250 200 200 IDD (µA) Quiescent Current (µA) VREF tied to VDD. 150 150 100 100 50 50 0 –40 0 40 80 0 120 2.7 3.2 3.7 4.2 Temperature (°C) 4.7 5.2 5.7 VDD (V) POWER-DOWN CURRENT vs SUPPLY VOLTAGE SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 100 700 90 600 80 500 60 IDD (µA) IDD (nA) 70 +105°C 50 –40°C 40 400 300 30 20 200 +25°C 10 0 100 2.7 3.2 3.7 4.2 4.7 5.2 5.7 0 VDD (V) 6 1 2 3 4 5 VLOGIC (V) DAC8501 www.ti.com SBAS212A TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, and +VDD = +5V, unless otherwise noted. FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Full-Scale Code Change FFFFH to 0000H Output Loaded with 2kΩ and 200pF to GND Full-Scale Code Change 0000H to FFFFH Output Loaded with 2kΩ and 200pF to GND Large-Signal Output (1.0V/div) Time (2µs/div) Time (2µs/div) HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1V/div) Half-Scale Code Change 4000H to C000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change C000H to 4000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) EXITING POWER-DOWN (8000H Loaded) POWER-ON RESET TO 0V Loaded with 2kΩ to VDD. Scope Trigger (5.0V/div) VDD (2V/div) Output (1.0V/div) VOUT (1V/div) Time (50µs/div) Time (2µs/div) DAC8501 SBAS212A www.ti.com 7 TYPICAL CHARACTERISTICS: VDD = +5V (Cont.) At TA = +25°C, and +VDD = +5V, unless otherwise noted. MULTIPLYING MODE SMALL-SIGNAL GAIN AND PHASE vs FREQUENCY CODE CHANGE GLITCH 20 0 Gain 0 Glitch Waveform (50mV/div) –45 –40 Phase –60 –90 –80 –100 –135 –120 –140 0.01 Time (2µs/div) 0.1 1 10 Frequency (kHz) 100 –180 1000 TYPICAL CHARACTERISTICS: VDD = +2.7V At TA = +25°C, and +VDD = +2.7V, unless otherwise noted. LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+25°C) LE (LSB) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH DLE (LSB) DLE (LSB) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (–40°C) 64 48 32 16 0 –16 –32 –48 –64 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Digital Input Code Digital Input Code DLE (LSB) ZERO-SCALE ERROR vs TEMPERATURE 20 64 48 32 16 0 –16 –32 –48 –64 15 10 2.0 1.5 1.0 0.5 0.0 –0.5 –1.0 –1.5 –2.0 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH Error (mV) LE (LSB) LINEARITY ERROR AND DIFFERENTIAL LINEARITY ERROR vs CODE (+105°C) 0 –5 –10 –15 –20 –40 0 40 80 120 Temperature (°C) Digital Input Code 8 5 DAC8501 www.ti.com SBAS212A Phase (°) Gain (dB) VOUT (50mV/div) –20 TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, and +VDD = +2.7V, unless otherwise noted. FULL-SCALE ERROR vs TEMPERATURE IDD HISTOGRAM 20 2000 15 1500 5 Frequency Error (mV) 10 0 –5 –10 1000 500 –15 0 –20 –40 0 40 80 120 100 130 160 190 220 250 280 310 340 370 400 Temperature (°C) IDD (µA) SUPPLY CURRENT vs DIGITAL INPUT CODE SOURCE AND SINK CURRENT CAPABILITY 3.0 500 2.5 400 DAC Loaded with FFFFH IDD (µA) VOUT (V) 2.0 1.5 300 200 1.0 100 0.5 DAC Loaded with 0000H 0 0 0 5 10 0000H 2000H 4000H 6000H 8000H A000H C000H E000H FFFFH 15 Digital Input Code ISOURCE/SINK (mA) SUPPLY CURRENT vs LOGIC INPUT VOLTAGE 200 300 180 250 160 IDD (µA) Quiescent Current (µA) POWER-SUPPLY CURRENT vs TEMPERATURE 350 200 150 140 120 100 100 50 0 80 –40 0 40 80 120 0 Temperature (°C) 1.0 1.5 2.0 2.5 3.0 VLOGIC (V) DAC8501 SBAS212A 0.5 www.ti.com 9 TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, and +VDD = +2.7V, unless otherwise noted. FULL-SCALE SETTLING TIME FULL-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1.0V/div) Full-Scale Code Change 0000H to FFFFH Output Loaded with 2kΩ and 200pF to GND Full-Scale Code Change FFFFH to 0000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) HALF-SCALE SETTLING TIME HALF-SCALE SETTLING TIME Scope Trigger (5.0V/div) Scope Trigger (5.0V/div) Large-Signal Output (1.0V/div) Small-Signal Error (1mV/div) Small-Signal Error (1mV/div) Large-Signal Output (1.0V/div) Half-Scale Code Change 4000H to C000H Output Loaded with 2kΩ and 200pF to GND Half-Scale Code Change C000H to 4000H Output Loaded with 2kΩ and 200pF to GND Time (2µs/div) Time (2µs/div) POWER-ON RESET to 0V EXITING POWER-DOWN (8000H Loaded) Loaded with 2kΩ to VDD. Scope Trigger (5.0V/div) VDD (1V/div) Output (1.0V/div) VOUT (1V/div) Time (2µs/div) Time (50µs/div) 10 DAC8501 www.ti.com SBAS212A TYPICAL CHARACTERISTICS: VDD = +2.7V (Cont.) At TA = +25°C, and +VDD = +2.7V, unless otherwise noted. VOUT (20mV/div) CODE CHANGE GLITCH Glitch Waveform (20mV/div) Time (2µs/div) RESISTOR STRING THEORY OF OPERATION DAC SECTION The architecture consists of a string DAC followed by an output buffer amplifier. Figure 1 shows a block diagram of the DAC architecture. VDD VFB REF (+) Resistor String REF(–) VOUT The resistor string section is shown in Figure 2, it is simply a string of resistors, each of value R. The code loaded into the DAC register determines at which node on the string the voltage is tapped off to be fed into the output amplifier by closing one of the switches connecting the string to the amplifier. It is ensured monotonic because it is a string of resistors. R DAC Register Output Amplifier R GND FIGURE 1. DAC8501 Architecture. R To Output Amplifier The input coding to the DAC8501 is straight binary, so the ideal output voltage is given by: VOUT = VREF • D 65536 (1) where D = decimal equivalent of the binary code that is loaded to the DAC register; it can range from 0 to 65535. R R FIGURE 2. Resistor String. DAC8501 SBAS212A www.ti.com 11 SERIAL INTERFACE OUTPUT AMPLIFIER The output buffer amplifier is capable of generating rail-to-rail voltages on its output which gives an output range of 0V to VDD; it is capable of driving a load of 2kΩ in parallel with 1000pF to GND. The source and sink capabilities of the output amplifier can be seen in the typical characteristics. The slew rate is 1V/µs with a full-scale settling time of 8µs with the output unloaded. The inverting input of the output amplifier is brought out to the VFB pin which allows for better accuracy in critical applications by tying the VFB point and the amplifier output together directly at the load. Other signal conditioning circuitry may also be connected between these points for specific applications. MULTIPLYING MODE OPTIMIZATIONS The DAC8501 is a version of the DAC8531 optimized for multiplying mode at a typical bandwidth of up to 350kHz, which gives better phase and gain performance. Two aspects of the DAC8501 operation are affected by the optimizations. The resistor string in the DAC8531 is disconnected from the reference input when power-down mode is entered, but in the DAC8501, the resistor string continues to draw current from the reference input during power-down mode. The DAC8501 has slightly different offset characteristics from the DAC8531: the DAC8501 may output 0V for the first few hundred codes, whereas the DAC8531 typically has far fewer such dead codes near 0. Offset and gain errors are measured from code 0200H for both devices, so specifications are not affected. In all other respects, the DAC8531 and DAC8501 operate identically. Multiplying-mode bandwidth is measured at both small-signal and full-power levels. Bandwidth at full-power amplitude, which is typically 64kHz, is limited by the 1V/µs slew rate of the output amplifier. Small-amplitude signals that do not cause the amplifier to slew are bandlimited by the output amplifier to approximately 350kHz. If the design approaches either of these limits, the DAC8501 must be tested in the application to ensure that it meets the needed requirements. The DAC8501 has a 3-wire serial interface (SYNC, SCLK, and DIN), which is compatible with SPI, QSPI, and Microwire interface standards as well as most DSPs, (see the Serial Write Operation timing diagram for an example of a typical write sequence). The write sequence begins by bringing the SYNC line LOW, data from the DIN line is clocked into the 24-bit shift register on the falling edge of SCLK. The serial clock frequency can be as high as 30MHz, making the DAC8501 compatible with high-speed DSPs. On the 24th falling edge of the serial clock, the last data bit is clocked in and the programmed function is executed (i.e., a change in DAC register contents and/or a change in the mode of operation). At this point, the SYNC line can be kept LOW or brought HIGH. In either case, it must be brought HIGH for a minimum of 33ns before the next write sequence so that a falling edge of SYNC can initiate the next write sequence. As the SYNC buffer draws more current when the SYNC signal is HIGH than it does when it is LOW, SYNC must be idled LOW between write sequences for lowest power operation of the part; as mentioned above, it must be brought HIGH again just before the next write sequence. INPUT SHIFT REGISTER The input shift register is 24 bits wide, as shown in Figure 3. The first six bits are don’t cares. The next two bits (PD1 and PD0) are control bits that control which mode of operation the part is in (normal mode or any one of three power-down modes): there is a more complete description of the various modes in the Power-Down Modes section. The next 16 bits are the data bits which are transferred to the DAC register on the 24th falling edge of SCLK. SYNC INTERRUPT In a normal write sequence, the SYNC line is kept LOW for at least 24 falling edges of SCLK and the DAC is updated on the 24th falling edge. However, if SYNC is brought HIGH before the 24th falling edge, this acts as an interrupt to the write sequence. When this happens, the shift register is reset and the write sequence is seen as invalid. Neither an update of the DAC register contents or a change in the operating mode occurs, as shown in Figure 4. DB23 X DB0 X X X X X PD1 PD0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 FIGURE 3. Data Input Register. 24th Falling Edge 24th Falling Edge CLK SYNC DIN DB23 DB0 DB23 Invalid Write Sequence: SYNC HIGH before 24th Falling Edge DB0 Valid Write Sequence: Output Updates on the 24th Falling Edge FIGURE 4. SYNC Interrupt Facility. 12 DAC8501 www.ti.com SBAS212A POWER-ON RESET The DAC8501 contains a power-on reset circuit that controls the output voltage during power-up. On power-up, the DAC register is filled with zeros and the output voltage is 0V; it remains there until a valid write sequence is made to the DAC. This is useful in applications where it is important to know the state of the output of the DAC when it is in the process of powering up. POWER-DOWN MODES The DAC8501 supports four separate modes of operation which are programmable by setting two bits (PD1 and PD0) in the control register. Table I shows how the state of the bits corresponds to the mode of operation of the device. PD1 (DB17) PD0 (DB16) 0 0 OPERATING MODE Normal Operation — — Power-Down Modes 0 1 Output 1kΩ to GND 1 0 Output 100kΩ to GND 1 1 High-Z MICROPROCESSOR INTERFACING DAC8501 TO 8051 INTERFACE Figure 6 shows a serial interface between the DAC8501 and a typical 8051-type microcontroller. The setup for the interface is as follows: TXD of the 8051 drives SCLK of the DAC8501, whereas RXD drives the serial data line of the part. The SYNC signal is derived from a bit-programmable pin on the port, in this case, port line P3.3 is used. When data is to be transmitted to the DAC8501, P3.3 is taken LOW. The 8051 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left LOW after the first eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken HIGH following the completion of the third write cycle. The 8051 outputs the serial data in a format which has the LSB first. The DAC8501 requires its data with the MSB as the first bit received, therefore the 8051 transmit routine must take this into account, and mirror the data as needed. TABLE I. Modes of Operation for the DAC8501. When both bits are set to 0, the part works normally with its typical current consumption of 250µA at 5V; however, for the three power-down modes, the supply current falls to 200nA at 5V (50nA at 3V). Not only does the supply current fall, but the output stage is also internally switched from the output of the amplifier to a resistor network of known values, this has the advantage that the output impedance of the part is known while the part is in power-down mode. There are three different options: the output is connected internally to GND through a 1kΩ resistor; a 100kΩ resistor; or it is left opencircuited (High-Z), Figure 5 shows the output stage. 80C51/80L51(1) DAC8501(1) P3.3 SYNC TXD SCLK RXD DIN NOTE: (1) Additional pins omitted for clarity. FIGURE 6. DAC8501 to 80C51/80L51 Interface. DAC8501 TO Microwire INTERFACE Figure 7 shows an interface between the DAC8501 and any Microwire compatible device. Serial data is shifted out on the falling edge of the serial clock and is clocked into the DAC8501 on the rising edge of the SK signal. VFB Resistor String DAC Amplifier Power-Down Circuitry VOUT MicrowireTM Resistor Network FIGURE 5. Output Stage During Power-Down. SYNC SK SCLK SO DIN NOTE: (1) Additional pins omitted for clarity. All linear circuitry is shut down when the power-down mode is activated, however, the contents of the DAC register are unaffected when in power-down. The time to exit powerdown is typically 2.5µs for VDD = 5V, and 5µs for VDD = 3V, (see the Typical Characteristics for more information). FIGURE 7. DAC8501 to Microwire Interface. DAC8501 SBAS212A DAC8501(1) CS www.ti.com 13 DAC8501 TO 68HC11 INTERFACE Figure 8 shows a serial interface between the DAC8501 and the 68HC11 microcontroller. SCK of the 68HC11 drives the SCLK of the DAC8501, whereas the MOSI output drives the serial data line of the DAC. The SYNC signal is derived from a port line (PC7), similar to what was done for the 8051. +15 +5V REF02 285µA (IDD + IREF) DAC8501(1) 68HC11(1) PC7 3-Wire Serial Interface SYNC SCK SCLK MOSI VDD SYNC VREF DAC8501 SCLK VOUT = 0V to 5V DIN DIN NOTE: (1) Additional pins omitted for clarity. FIGURE 8. DAC8501 to 68HC11 Interface. FIGURE 9. REF02 as a Power Supply to the DAC8501. The 68HC11 should be configured so that its CPOL bit is a 0 and its CPHA bit is a 1, this configuration causes data appearing on the MOSI output to be valid on the falling edge of SCK. When data is being transmitted to the DAC, the SYNC line is taken LOW (PC7). Serial data from the 68HC11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle, data is transmitted MSB first. In order to load data to the DAC8501, PC7 is left LOW after the first eight bits are transferred, then a second and third serial write operation is performed to the DAC and PC7 is taken HIGH at the end of this procedure. are at some value other than 5V. The REF02 will output a steady supply voltage for the DAC8501; if the REF02 is used, the typical current it needs to supply to the DAC8501 is 285µA. This is with no load on the output of the DAC. When the DAC output is loaded, the REF02 also needs to supply the current to the load. The total current required (with a 5kΩ load on the DAC output) is: 285µA + (5V/ 5kΩ) = 1.29mA (2) The load regulation of the REF02 is typically 0.005%/mA, which results in an error of 322µV for the 1.29mA current drawn from it. This corresponds to a 4.2LSB error. APPLICATIONS BIPOLAR OPERATION USING THE DAC8501 USING REF02 AS A POWER SUPPLY FOR THE DAC8501 The DAC8501 has been designed for single-supply operation but a bipolar output range is also possible using the circuit in Figure 10. The circuit shown will give an output voltage range of ±VREF. Rail-to-rail operation at the amplifier output is achievable using an OPA703 as the output amplifier. Due to the extremely low supply current required by the DAC8501, an alternative option is to use a REF02 +5V precision voltage reference to supply the required voltage to the part, as shown in Figure 9. This is especially useful if the power supply is quite noisy or if the system supply voltages R2 10kΩ VREF +5V R1 10kΩ OPA703 VFB VREF 10µF DAC8501 0.1µF ±VREF VOUT –5V 3-Wire Serial Interface FIGURE 10. Bipolar Operation with the DAC8501. 14 DAC8501 www.ti.com SBAS212A The output voltage for any input code can be calculated as follows: VO = VREF D R1 + R 2 • – VREF • 65536 R1 R • 2 (3) R1 where D represents the input code in decimal (0 to 65535). With VREF = 5V, R1 = R2 = 10kΩ: 10 • D VO = – 5V 65536 (4) This is an output voltage range of ±5V with 0000H corresponding to a –5V output and FFFFH corresponding to a +5V output. Similarly, using VREF = 2.5V, a ±2.5V output voltage range can be achieved. LAYOUT A precision analog component requires careful layout, adequate bypassing, and clean, well-regulated power supplies. As the DAC8501 offers single-supply operation, it will often be used in close proximity with digital logic, microcontrollers, microprocessors, and digital signal processors. The more digital logic present in the design and the higher the switching speed, the more difficult it will be to keep digital noise from appearing at the output. Due to the single ground pin of the DAC8501, all return currents, including digital and analog return currents, must flow through the GND pin, which would, ideally, be connected directly to an analog ground plane. This plane would be separate from the ground connection for the digital components until they were connected at the power-entry point of the system. The power applied to VDD should be well regulated and low noise. Switching power supplies and DC/DC converters will often have high-frequency glitches or spikes riding on the output voltage. In addition, digital components can create similar high-frequency spikes as their internal logic switches states. This noise can easily couple into the DAC output voltage through various paths between the power connections and analog output. As with the GND connection, VDD should be connected to a power-supply plane or trace that is separate from the connection for digital logic until they are connected at the powerentry point. In addition, the 1µF to 10µF and 0.1µF bypass capacitors are strongly recommended. In some situations, additional bypassing may be required, such as a 100µF electrolytic capacitor or even a Pi filter made up of inductors and capacitors—all designed to essentially low-pass filter the +5V supply, removing the high-frequency noise. DAC8501 SBAS212A www.ti.com 15 PACKAGE DRAWING DGK (R-PDSO-G8) PLASTIC SMALL-OUTLINE PACKAGE 0,38 0,25 0,65 8 0,08 M 5 0,15 NOM 3,05 2,95 4,98 4,78 Gage Plane 0,25 1 0°– 6° 4 3,05 2,95 0,69 0,41 Seating Plane 1,07 MAX 0,15 0,05 0,10 4073329/C 08/01 NOTES: A. B. C. D. 16 All linear dimensions are in millimeters. This drawing is subject to change without notice. Body dimensions do not include mold flash or protrusion. Falls within JEDEC MO-187 DAC8501 www.ti.com SBAS212A PACKAGE OPTION ADDENDUM www.ti.com 9-Dec-2004 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty DAC8501E/250 ACTIVE MSOP DGK 8 250 None CU NIPDAU Level-3-220C-168 HR DAC8501E/2K5 ACTIVE MSOP DGK 8 2500 None CU NIPDAU Level-3-220C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - May not be currently available - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. None: Not yet available Lead (Pb-Free). Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Green (RoHS & no Sb/Br): TI defines "Green" to mean "Pb-Free" and in addition, uses package materials that do not contain halogens, including bromine (Br) or antimony (Sb) above 0.1% of total product weight. (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDECindustry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 1 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. All products are sold subject to TI’s terms and conditions of sale supplied at the time of order acknowledgment. TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with TI’s standard warranty. Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty. Except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. TI assumes no liability for applications assistance or customer product design. Customers are responsible for their products and applications using TI components. To minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. TI does not warrant or represent that any license, either express or implied, is granted under any TI patent right, copyright, mask work right, or other TI intellectual property right relating to any combination, machine, or process in which TI products or services are used. Information published by TI regarding third-party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from TI under the patents or other intellectual property of TI. Reproduction of information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. Reproduction of this information with alteration is an unfair and deceptive business practice. TI is not responsible or liable for such altered documentation. Resale of TI products or services with statements different from or beyond the parameters stated by TI for that product or service voids all express and any implied warranties for the associated TI product or service and is an unfair and deceptive business practice. TI is not responsible or liable for any such statements. Following are URLs where you can obtain information on other Texas Instruments products and application solutions: Products Applications Amplifiers amplifier.ti.com Audio www.ti.com/audio Data Converters dataconverter.ti.com Automotive www.ti.com/automotive DSP dsp.ti.com Broadband www.ti.com/broadband Interface interface.ti.com Digital Control www.ti.com/digitalcontrol Logic logic.ti.com Military www.ti.com/military Power Mgmt power.ti.com Optical Networking www.ti.com/opticalnetwork Microcontrollers microcontroller.ti.com Security www.ti.com/security Telephony www.ti.com/telephony Video & Imaging www.ti.com/video Wireless www.ti.com/wireless Mailing Address: Texas Instruments Post Office Box 655303 Dallas, Texas 75265 Copyright 2004, Texas Instruments Incorporated