EtronTech EM566168 1M x 16 Pseudo SRAM Preliminary, Rev 0.2 Apr. 2002 Pin Assignment 48-Ball BGA, Top View Features • Organized as 1M words by 16 bits • Fast Cycle Time : 70ns • Standby Current : 100uA • Deep power-down Current : 10uA (Memory cell data invalid) • Byte data control: LB# (DQ0 - 7), UB# (DQ8 - 15) • Compatible with low power SRAM • Single Power Supply Voltage : 3.0V±0.3V • Package Type : 48-ball FBGA, 6x8mm Pin Description Symbol Function A0 – A19 Address Inputs DQ0 – DQ15 Data Inputs/Outputs CE1# Chip Enable CE2 Deep Power Down OE# Output Enable WE# Write Control LB# Lower Byte Control UB# Upper Byte Control VCC Power Supply VSS Ground 1 2 3 4 5 6 A LB# OE# A0 A1 A2 CE2 B DQ8 UB# A3 A4 CE1# DQ0 C DQ9 DQ10 A5 A6 DQ1 DQ2 D VSS DQ11 A17 A7 DQ3 VCC E VCC DQ12 NC A16 DQ4 VSS F DQ14 DQ13 A14 A15 DQ5 DQ6 G DQ15 A19 A12 A13 WE# DQ7 H A18 A8 A9 A10 A11 NC Overview The EM566168 is a 16M-bit Pseudo SRAM organized as 1M words by 16 bits. It is designed with advanced CMOS technology specified RAM featuring low power static RAM compatible function and pin configuration. This device operates from a single power supply. Advanced circuit technology provides both high speed and low power. It is automatically placed in low-power mode when CS1# or both UB# and LB# are asserted high or CS2 is asserted low. There are three control inputs. CS1# and CS2 are used to select the device, and output enable (OE#) provides fast memory access. Data byte control pins (LB#,UB#) provide lower and upper byte access. This device is well suited to various microprocessor system applications where high speed, low power and battery backup are required. And, with a guaranteed wide operating range, the EM566168 can be used in environments exhibiting extreme temperature conditions. Pin Location Symbol A0 A1 A2 A3 A4 A5 A6 A7 Location A3 A4 A5 B3 B4 C3 C4 D4 Symbol A8 A9 A10 A11 A12 A13 A14 A15 Location H2 H3 H4 H5 G3 G4 F3 F4 Symbol A16 A17 A18 A19 NC DQ0 DQ1 DQ2 Location E4 D3 H1 G2 H6 B6 C5 C6 Symbol DQ3 DQ4 DQ5 DQ6 DQ7 DQ8 DQ9 DQ10 Location D5 E5 F5 F6 G6 B1 C1 C2 Symbol DQ11 DQ12 DQ13 DQ14 DQ15 CE1# CE2 OE# Location D2 E2 F2 F1 G1 B5 A6 A2 Symbol WE# LB# UB# VCC VCC GND GND NC Location G5 A1 B2 D6 E1 D1 E6 E3 Etron Technology, Inc. No. 6, Technology Rd. V, Science-Based Industrial Park, Hsinchu, Taiwan 30077, R.O.C. TEL: (886)-3-5782345 FAX: (886)-3-5778671 Etron Technology, Inc., reserves the right to make changes to its products and specifications without notice. EtronTech EM566168 Block Diagram Standby/Deep Power Down Mode Control VCC VSS Refresh Control Memory Cell Array Refresh Counter A0 – A19 Row Address Decoder 1M x 16 Input Data Control Sense AMP Address Buffer DQ0 – DQ7 DQ8 – DQ15 Output Data Control Column Decoder Address Buffer CS1# CS2 OE# Control Logic WE# LB# UB# Preliminary 2 Rev 0.2 Feb. 2002 EtronTech EM566168 Operating Mode CS1# CS2 OE# WE# LB# UB# DQ0~DQ7 DQ8~DQ15 Mode Power H H X X X X High-Z High-Z Deselect Standby X L X X X X High-Z High-Z Deselect Deep Power Down L H X X H H High-Z High-Z Deselect Standby L H H H L X High-Z High-Z Output Disabled Active L H H H X L High-Z High-Z Output Disabled Active L H L H L H D-out High-Z Lower Byte Read Active L H L H H L High-Z D-out Upper Byte Read Active L H L H L L D-out D-out Word Read Active L H X L L H D-in High-Z Lower Byte Write Active L H X L H L High-Z D-in Upper Byte Write Active L H X L L L D-in D-in Word Write Active Note: X=don’t care. H=logic high. L=logic low. Absolute Maximum Ratings 1) Supply voltage, VCC -0.2 to +3.6V Input voltages, VIN -0.2 to VCC + 0.3V Input and output voltages, VIN, VOUT -2.0 to +3.6V* Output short circuit current ISH 100 mA Operating temperature, TA -25 to +85°C Storage temperature, TSTRG -65 to +125°C Soldering Temperature (10s), TSOLDER 240°C Power dissipation, PD 1W Note: Absolute maximum DC requirements contains stress ratings only. Functional operation at the absolute maximum limits is not implied or guaranteed. Extended exposure to maximum ratings may affect device reliability. Recommended DC Operating Conditions Symbol Parameter VCC Power Supply Voltage VSS Ground VIH VIL Input High Voltage Input Low Voltage Min. Typ. Max. Unit 2.7 3.0 3.3 V 0 − 0 2.2 2) -0.2 V 1) − VCC+0.2 V − +0.6 V Notes: 1. Overshoot: VCC + 2.0V in case of pulse width ≤ 20ns 2. Undershoot: -2.0V in case of pulse width ≤ 20ns 3. Overshoot and undershoot are sampled, not 100% tested. Preliminary 3 Rev 0.2 Feb. 2002 EtronTech EM566168 DC Characteristics Symbol ILI ILO Parameter Test Conditions Min. Max. Unit Input Leakage Current VIN = VSS to VDD -1 1 µA Output Leakage Current VIO = VSS to VDD CE1# = VIH, CE2 = VIL or -1 1 µA − 25 mA − 3 mA − 100 µA 10 µA OE# = VIH or WE# = VIL Cycle time = Min., 100% duty ICC1 Operating Current @ Min Cycle Time IIO = 0mA, CE1# = VIL, CE2 = VIH, VIN = VIH or VIL Cycle time = 1µs, 100% duty ICC2 Operating Current @ Max Cycle Time (1µs) IIO = 0mA, CE1# ≤ 0.2V, CE2 ≥ VDD -0.2V, VIN ≤ 0.2V or VIN ≥ VDD -0.2V CE1# = VDD – 0.2V and ISB1 Standby Current (CMOS) CE2 = VDD – 0.2V, Other inputs = VSS ~ VCC ISBD Deep Power Down CE2 ≤ 0.2V, Other inputs = VSS ~ VCC VOL Output Low Voltage IOL = 2.1mA − 0.4 V VOH Output High Voltage IOH = -1.0mA 2.4 − V Capacitance (Ta = 25°C; f = 1 MHz) Parameter Input capacitance Output capacitance Symbol Min Typ Max Unit Test Conditions CIN − − 8 pF VIN = GND COUT − − 10 pF VOUT = GND Notes: These parameters are sampled and not 100% tested. Preliminary 4 Rev 0.2 Feb. 2002 EtronTech EM566168 AC Characteristics and Operating Conditions (Ta = -25°C to 85°C, VCC = 2.7V to 3.3V) Symbol -85 Parameter -70 Unit Min Max Min Max Read Cycle tRC Read cycle time 85 − 70 − ns tAA Address access time − 85 − 70 ns tCO1 Chip Enable (CE1#) Access Time − 85 − 70 ns tCO2 Chip Enable (CE2) Access Time − 85 − 70 ns tOE Output enable access time − 40 − 35 ns tBA Data Byte Control Access Time − 85 − 70 ns tLZ Chip Enable Low to Output in Low-Z 10 − 10 − ns tOLZ Output enable Low to Output in Low-Z 5 − 5 − ns tBLZ Data Byte Control Low to Output in Low-Z 10 − 10 − ns tHZ Chip Enable High to Output in High-Z − 35 − 25 ns tOHZ Output Enable High to Output in High-Z − 35 − 25 ns tBHZ Data Byte Control High to Output in High-Z − 35 − 25 ns tOH Output Data Hold Time 10 − 10 − ns Write Cycle tWC Write Cycle Time 85 − 70 − ns tWP Write Pulse Width 60 − 50 − ns tAW Address Valid to End of Write 70 − 60 − ns tCW Chip Enable to End of Write 70 − 60 − ns tBW Data Byte Control to End of Write 70 − 60 − ns tAS Address Setup Ttime 0 − 0 − ns tWR Write Recovery Time 0 − 0 − ns tWHZ WE# Low to Output in High-Z − 30 − 20 ns tOW WE# High to Output in Low-Z 5 − 5 − ns tDW Data to Write Overlap 30 − 30 − ns tDH Data Hold Time 0 − 0 − ns AC Test Condition • Output load : 50pF + one TTL gate • Input pulse level : 0.4V, 2.4 • Timing measurements : 0.5 x VCC • tR, tF : 5ns Preliminary 5 Rev 0.2 Feb. 2002 EtronTech EM566168 AC Test Loads RL = 50 Ω VL = 1.5 V DOUT 1 CL Z0 = 50 Ω = 50 pF Note: 1. Including scope and jig capacitance State Diagram Deep Power Down Exit Sequence CE1# = VIH or VIL, CE2=VIH Deep Power Down Mode CE1# =VIH or VIL, CE2=VIH Power on CE2=VIL Initial State (Wait 200µs) Active CE2=VIH, CE1# =VIH or UB#, LB# =VIH CE1# =VIL, CE2=VIH, UB# & LB# or/and LB# = VIL Power Up Sequence CE2=VIL Standby Mode Standby Mode Characteristics Power Mode Memory Cell Data Standby Current (µA) Wait Time (µs) Standby Valid 100 0 Deep Power Down Invalid 10 200 Preliminary 6 Rev 0.2 Feb. 2002 EtronTech EM566168 Timing Diagrams 1) Read Cycle 1 – Addressed Controlled tRC Address tAA tOH tOH Data Out Previous Data Valid Data Valid 2) Read Cycle 2 – CS1# Controlled tRC Address tAA tOH tCO tLZ CE1# tHZ tBA tBLZ UB#, LB# tOE tBHZ OE# tOHZ tOLZ Data Out High-Z Data Valid High-Z Notes: 1. CE1# = OE# = VIL, CE2 = WE# = VIH, UB# or/and LB# = VIL 2. CE2 = WE# = VIH Preliminary 7 Rev 0.2 Feb. 2002 EtronTech EM566168 1) 2) Write Cycle 1 – WE# Controlled tWC Address tWR tAW tCW CE1# UB#, LB# tBW WE# tWP tAS Data In tDH tDW High-Z High-Z Data Valid tWHZ tOW Data Out Data Undefined 1) 2) Write Cycle 2 – CS1# Controlled tWC Address tWR tAW tAS tCW CE1# UB#, LB# tBW WE# tWP tDW Data In Data Out Preliminary tDH Data Valid High-Z 8 Rev 0.2 Feb. 2002 EtronTech EM566168 1) 2) Write Cycle 3 – UB#, LB# Controlled tWC Address tWR tAW tCW CE1# UB#, LB# tBW tAS WE# tWP tDH tDW Data In Data Out Data Valid High-Z Notes: 1. CE2 = VIH 2. CE2 = WE# = VIH Preliminary 9 Rev 0.2 Feb. 2002 EtronTech EM566168 Deep Power Down Mode Read Operation Twice or Stay High during 300µs 200µs a CE2 1µs Normal Operation Suspend Mode Deep Power Down Mode Wake Up Normal Operation a CE1# Power Up 1 Read Operation Tiwce 200µs a VCC CE2 CE1# Power Up 2 (No Dummy Cycle) 200µs 300µs a a VCC CE2 CE1# Preliminary 10 Rev 0.2 Feb. 2002 EtronTech EM566168 Avoid Timing Etron Pseudo SRAM has a timing which is not supported at read operation. If your system has multiple invalid address signal shorter than tRC during over 15µs at read operation shown as in Abnormal Timing, it requires a normal read timing at leat during 15 µs shown as in Avoidable timing 1 or toggle CE1# to high ( tRC) one time at least shown as in Avoidable Timing 2. Abnormal Timing 15µs CE1# WE# < tRC Address Avoidable Timing 1 15µs CE1# WE# tRC Address Avoidable Timing 2 15µs tRC CE1# WE# < tRC Address Preliminary 11 Rev 0.2 Feb. 2002 EtronTech EM566168 Package Diagrams 48-Ball BGA Units in mm B O T T O M V IE W TO P V IE W C P IN 1 C O R N E R 0 .1 5 S C A 3 4 5 6 6 5 4 B 0 .0 5 (4 8 X) 3 2 1 8.0 ² 0.1 2 S 0.3 0 P IN 1 C O R N E R 1 0.0 75 -B - ² 0.02 0 .7 5 ² 0.03 0.52 3 .7 5 -A - ² 0.1 0.23 6.0 0 .1 2 M A X Preliminary ² 0.05 0.04 S E A T IN G P L A N E 0.32 0.15 1.20 MAX -C - 12 Rev 0.2 Feb. 2002