FINTEK F71883FG

F71883
F71883
Super Hardware Monitor + LPC I/O
Release Date: May, 2008
Version: V0.27P
May, 2008
V0.27P
F71883
F71883 Datasheet Revision History
Version
Date
Page
Revision History
0.20P
2005/10/14
-
Release Version
0.21P
2006/01/20
-
Added new functions ( Intel PECI/SST interface) and
updated registers description and schematic
0.22P
2006/09/04
125
Updated 80-Port application circuit.
0.23P
2006/11/23
60
Modified the description of Wakeup Control Register 2Dh
bit 7(SPI_CS1_EN)
0.24P
2007/7/6
-
0.25P
2007/9/14
12
Modified power source of pin 84 (VSB Æ VBAT)
Company readdress
0.26P
2008/1/30
121
Modified operating temperature
0.27P
2008/5/30
84
Modified chapter 8.6.2.35 title
Please note that all data and specifications are subject to change without notice. All the trade marks of products
and companies mentioned in this data sheet belong to their respective owners.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal injury. Customers using or selling these products for
use in such applications do so at their own risk and agree to fully indemnify Fintek for any damages resulting from
such improper use or sales.
May, 2008
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Table of Content
1.
2.
3.
4.
5.
6.
7.
8.
General Description ........................................................................................................................1
Feature List .....................................................................................................................................1
Key Specification............................................................................................................................4
Block Diagram ................................................................................................................................4
Pin Configuration............................................................................................................................5
Pin Description................................................................................................................................5
Function Description.....................................................................................................................14
7.1 Power on Strapping Option.......................................................................................................14
7.2 FDC...........................................................................................................................................14
7.3 UART........................................................................................................................................28
7.4 Parallel Port...............................................................................................................................32
7.5 Hardware Monitor.....................................................................................................................35
7.6 Keyboard Controller .................................................................................................................45
7.7 SPI Interface..............................................................................................................................46
7.8 80 Port.......................................................................................................................................47
7.9 ACPI Function ..........................................................................................................................47
7.10 AMDSI and Intel SST PECI Function......................................................................................50
Register Description......................................................................................................................51
8.1 Global Control Registers...........................................................................................................55
8.2 FDC Registers (CR00)..............................................................................................................62
8.3 UART1 Registers (CR01) .........................................................................................................65
8.4 UART 2 Registers (CR02) ........................................................................................................66
8.5 Parallel Port Registers (CR03)..................................................................................................68
8.6 Hardware Monitor Registers (CR04)........................................................................................70
8.6.2.1
8.6.2.2
8.6.2.3
8.6.2.4
8.6.2.5
8.6.2.6
8.6.2.7
HW Monitor Config. Register  Index 01h .....................................................................71
BEEP OVT ALERT Config. Register  Index 02h...........................................................71
Case Open Config. Register  Index 03h..........................................................................71
PECI AMDSI Select Register  Index 0Ah ......................................................................72
PECI CPU Select Register  Index 0Bh (MEAS_TYPE == 2’b01)..............................72
AMDSI Version Register  Index 0Bh (MEAS_TYPE ==2’b10).................................72
TCC Temp. Register  Index 0Ch (MEAS_TYPE == 2’b01) .......................................72
8.6.2.8 AMDSI Node ID Register  Index 0Ch (MEAS_TYPE ==2’b10) ...............................72
8.6.2.9 SST Address Register  Index 0Dh ..................................................................................72
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8.6.2.10
8.6.2.11
8.6.2.12
8.6.2.13
8.6.2.14
8.6.2.15
8.6.2.16
8.6.2.17
8.6.2.18
8.6.2.19
8.6.2.20
8.6.2.21
8.6.2.22
8.6.2.23
8.6.2.24
8.6.2.25
8.6.2.26
8.6.2.27
8.6.2.28
8.6.2.29
8.6.2.30
8.6.2.31
8.6.2.32
8.6.2.33
8.6.2.34
8.6.2.35
8.6.2.36
8.6.2.37
VID Divide Register  Index 0Eh...................................................................................73
Configuration Register  Index 0Fh................................................................................73
Voltage1 PME# Enable Register  Index 10h.................................................................74
Voltage1 Interrupt Status Register  Index 11h ..............................................................74
Voltage1 Exceeds Real Time Status Register 1  Index 12h ..........................................74
Voltage1 BEEP Enable Register  Index 13h .................................................................74
Voltage reading and limit Index 20h- 4Fh ....................................................................74
Temperature PME# Enable Register  Index 60h...........................................................75
Temperature Interrupt Status Register  Index 61h ........................................................75
Temperature Real Time Status Register  Index 62h......................................................76
Temperature BEEP Enable Register  Index 63h ...........................................................77
OVT Output Enable Register 1  Index 66h...................................................................77
Temperature Sensor Type Register  Index 6Bh ............................................................77
TEMP1 Limit Hystersis Select Register -- Index 6Ch.....................................................78
TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh ................................78
DIODE OPEN Status Register -- Index 6Fh....................................................................78
Temperature Filter Select Register -- Index 8Eh .............................................................79
FAN PME# Enable Register  Index 90h .......................................................................80
FAN Interrupt Status Register  Index 91h.....................................................................80
FAN Real Time Status Register  Index 92h ..................................................................81
FAN BEEP# Enable Register  Index 93h .....................................................................81
Fan Type Select Register -- Index 94h.............................................................................81
Fan mode Select Register -- Index 96h............................................................................82
Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h ..........................83
Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h ..........................84
Auto Fan Duty Update Rate Select Register -- Index 9Bh ..............................................84
FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE  Index 9Ch ........................84
FAN3 and FAN4 START UP DUTY-CYCLE/VOLTAGE  Index 9Dh ........................85
8.6.2.38
8.6.2.39
8.6.2.40
8.6.2.41
8.6.2.42
8.6.2.43
8.6.2.44
8.6.2.45
8.6.2.46
Fan Fault Time Register -- Index 9Fh..............................................................................85
VT1 BOUNDARY 1 TEMPERATURE – Index A6h......................................................86
VT1 BOUNDARY 2 TEMPERATURE – Index A7........................................................86
VT1 BOUNDARY 3 TEMPERATURE – Index A8h......................................................87
VT1 BOUNDARY 4 TEMPERATURE – Index A9........................................................87
FAN1 SEGMENT 1 SPEED COUNT – Index AAh ....................................................87
FAN1 SEGMENT 2 SPEED COUNT – Index ABh.....................................................88
FAN1 SEGMENT 3 SPEED COUNT – Index ACh...................................................88
FAN1 SEGMENT 4 SPEED COUNT – Index ADh ..................................................88
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8.6.2.47 FAN1 SEGMENT 5 SPEED COUNT – Index AEh...................................................88
8.6.2.48 FAN1 Temperature Mapping Select – Index AFh.......................................................88
8.6.2.49 VT2 BOUNDARY 1 TEMPERATURE – Index B6h......................................................90
8.6.2.50 VT2 BOUNDARY 2 TEMPERATURE – Index B7........................................................90
8.6.2.51 VT2 BOUNDARY 3 TEMPERATURE – Index B8h......................................................90
8.6.2.52 VT2 BOUNDARY 4 TEMPERATURE – Index B9........................................................90
8.6.2.53 FAN2 SEGMENT 1 SPEED COUNT – Index BAh ....................................................91
8.6.2.54 FAN2 SEGMENT 2 SPEED COUNT – Index BBh.....................................................91
8.6.2.55 FAN2 SEGMENT 3 SPEED COUNT – Index BCh...................................................91
8.6.2.56 FAN2 SEGMENT 4 SPEED COUNT – Index BDh ..................................................91
8.6.2.57 FAN2 SEGMENT 5 SPEED COUNT – Index BEh...................................................92
8.6.2.58 FAN2 Temperature Mapping Select – Index BFh.......................................................92
8.6.2.59 VT3 BOUNDARY 1 TEMPERATURE – Index C6h......................................................93
8.6.2.60 VT3 BOUNDARY 2 TEMPERATURE – Index C7........................................................93
8.6.2.61 VT3 BOUNDARY 3 TEMPERATURE – Index C8h......................................................94
8.6.2.62 VT3 BOUNDARY 4 TEMPERATURE – Index C9........................................................94
8.6.2.63 FAN3 SEGMENT 1 SPEED COUNT – Index CAh ....................................................94
8.6.2.64 FAN3 SEGMENT 2 SPEED COUNT – Index CBh.....................................................95
8.6.2.65 FAN3 SEGMENT 3 SPEED COUNT – Index CCh...................................................95
8.6.2.66 FAN3 SEGMENT 4 SPEED COUNT – Index CDh ..................................................95
8.6.2.67 FAN3 SEGMENT 5 SPEED COUNT – Index CEh...................................................95
8.6.2.68 FAN3 Temperature Mapping Select – Index CFh.......................................................95
8.6.2.69 VT4 BOUNDARY 1 TEMPERATURE – Index D6h .....................................................97
8.6.2.70 VT4 BOUNDARY 2 TEMPERATURE – Index D7 .......................................................97
8.6.2.71 VT4 BOUNDARY 3 TEMPERATURE – Index D8h .....................................................97
8.6.2.72 VT4 BOUNDARY 4 TEMPERATURE – Index D9 .......................................................98
8.6.2.73 FAN4 SEGMENT 1 SPEED COUNT – Index DAh ....................................................98
8.6.2.74 FAN4 SEGMENT 2 SPEED COUNT – Index DBh ....................................................98
8.6.2.75 FAN4 SEGMENT 3 SPEED COUNT – Index DCh ..................................................98
8.6.2.76 FAN4 SEGMENT 4 SPEED COUNT – Index DDh ..................................................99
8.6.2.77 FAN4 SEGMENT 5 SPEED COUNT – Index DEh...................................................99
8.6.2.78 FAN4 Temperature Mapping Select – Index DFh ......................................................99
8.7 KBC Registers (CR05) ...........................................................................................................100
8.8 GPIO Registers (CR06) ..........................................................................................................102
8.9 VID Registers (CR07).............................................................................................................109
8.10 SPI Registers (CR08)..............................................................................................................113
8.11 PME and ACPI Registers (CR0A)..........................................................................................118
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9.
Electron Characteristic................................................................................................................121
9.1 Absolute Maximum Ratings ...................................................................................................121
9.2 DC Characteristics ..................................................................................................................121
9.3 DC Characteristics Continued.................................................................................................121
10.
Ordering Information ..................................................................................................................122
11.
Package Dimensions .................................................................................................................123
12.
Application Circuit......................................................................................................................124
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1. General Description
The F71883 is the featured IO chip for PC system. Equipped with one IEEE 1284
parallel port, two UART ports, KBC, Serial Peripheral Interface (SPI), 80-Port, SIR and one
FDC. The F71883 integrated with hardware monitor, 9 sets of voltage sensor, 4 sets of
creative auto-controlling fans and 4 temperature sensor pins for the accurate dual current type
temp. measurement for CPU thermal diode or external transistors 2N3906.
The F71883 provides flexible features for multi-directional application. For instance,
supports 6/12 pins CPU VID controlling for VRM9.0/10.0/11* and CPU VID OTF (On The Fly),
provides 32 GPIO pins (multi-pin), IRQ sharing function also designed in UART feature for
particular usage and accurate current mode H/W monitor will be worth in measurement of
temperature, provides 3 modes fan speed control mechanism included Manual Mode/Speed
Mode/Temperature Mode for users’ selection Additionally, provides easy voltage sensor input
(VSI) function for sensing Vcore voltage, then output (VSO) the offset voltage for over/under
voltage change use.
Further, the F71883 supports an automatic/dynamic over-voltage function for application
of over-clocking or under-clocking. This function provides Turbo# pins by external trigger
signal to improve the CPU’s performance by voltage offset automatically when system is
going to run over-clocking or under-clocking. Due to achieve this action, suggest F75133S
Loading Gauge chip can be the part which detects system/CPU loading to decide when
issues the over-clocking/under-clocking signal for system executing. Briefly, user can gain
more features on motherboard by these two parts which improve performance and efficiency.
The F71883 also integrated SPI interface and 80-Port. The SPI interface is for BIOS
usage including bridge function and back up function, and the 80-Port is for engineering
usage. Others, the F71883 supports newest AMDSI and Intel PECI/SST interfaces for
temperature use. These features will help you more and improve product value. Finally, the
F71883 is powered by 3.3V voltage, with the LPC interface in the package of 128-QFP green
package.
2. Feature List
General Functions
¾ Comply with LPC Spec. 1.0
¾ Support DPM (Device Power Management), ACPI
¾ 6/12 VID pins for VRM9.0/10.0/11.0* and CPU VID OTF (On The Fly)
¾ Easy voltage sensor I/O (VSI/VSO) for Vcore change use.
¾ Support automatic and dynamic voltage change function (Turbo pins)
¾ Provides one FDC, two UARTs, KBC and Parallel Port
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¾ H/W monitor functions
¾ SPI interface for BIOS use
¾ 80-Port interface.
¾ Support AMD SID/SIC interface and Intel SST/PECI interface
¾ 32 GPIO Pins for flexible application
¾ 24/48 MHz clock input
¾ Packaged in 128-PQFP green package and powered by 3.3VCC
FDC
¾ Compatible with IBM PC AT disk drive systems
¾ Variable write pre-compensation with track selectable capability
¾ Support vertical recording format
¾ DMA enable logic
¾ 16-byte data FIFOs
¾ Support floppy disk drives and tape drives
¾ Detects all overrun and under run conditions
¾ Built-in address mark detection circuit to simplify the read electronics
¾ Completely compatible with industry standard 82077
¾ 360K/720K/1.2M/1.44M/2.88M format; 250K, 300K, 500K, 1M, 2M bps data transfer rate
UART
¾ Two high-speed 16C550 compatible UART with 16-byte FIFOs
¾ Fully programmable serial-interface characteristics
¾ Baud rate up to 115.2K
¾ Support IRQ sharing
Infrared
¾ Support IrDA version 1.0 SIR protocol with maximum baud rate up to 115.2K bps
Parallel Port
¾ One PS/2 compatible bi-directional parallel port
¾ Support Enhanced Parallel Port (EPP) − Compatible with IEEE 1284 specification
¾ Support Extended Capabilities Port (ECP) − Compatible with IEEE 1284 specification
¾ Enhanced printer port back-drive current protection
Keyboard Controller
¾ 8042 based with optional F/W from AMIKKEYTM-2, with 2K bytes of programmable
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ROM, and 256 bytes of RAM
¾ Asynchronous Access to Two Data Registers and One status Register
¾ Software compatibility with the 8042
¾ Support PS/2 mouse
¾ Support both interrupt and polling modes
¾ Fast Gate A20 and Hardware Keyboard Reset
¾ 6 MHz, 8 MHz, 12 MHz, or 16 MHz operating frequency
Hardware Monitor Functions
¾ 3 dual current type (±3℃) thermal inputs for CPU thermal diode and 2N3906 transistors
¾ Temperature range -20℃~145℃ (One is from -20~127℃, two sets are from 0~ 145℃)
¾ 9 sets voltage monitoring (6 external and 3 internal powers)
¾ High limit signal (SMI#) for Vcore level
¾ 4 fan speed monitoring inputs
¾ 4 fan speed PWM/DC control outputs(support 3 wire and 4 wire fans)
¾ Issue PME# and OVT# hardware signals output
¾ Case intrusion detection circuit
¾ WATCHDOG# comparison of all monitored values
Serial Peripheral Interface Compatible
¾ Support SPI bridge function for BIOS use
¾ Support Back Up BIOS function
80-Port Interface
¾ Monitor 0x80 Port status and output the value via the signals defined for 7-segment display.
¾ High nibble and low nibble are outputted interleaved at 1KHz frequency.
Integrate AMD SI Interface
Integrate Intel PECI/SST Interface
Package
¾ 128-pin PQFP green package
Noted: Patented TW207103 TW207104 TW220442 US6788131 B1 TWI235231 TW237183 TWI263778
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3. Key Specification
Supply Voltage
3.0V to 3.6V
Operating Supply Current
----- mA typ.
4. Block Diagram
CPU
Chipset
(NB+SB)
Super H/W Monitor +
F71883
IDE
USB
AC’97
I/O
Temperature
KBC
LED(GPIO)
Voltage
IrDA
COM
Fan
Parallel
Floppy
ACPI
VID
Controller
SPI
80-Port
AMDSI
PECI
A
SST
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5. Pin Configuration
6. Pin Description
I/O12t
I/OOD12t
I/OD16t5v
OD16-u10-5v
I/OD12ts5v
ILv/OD8-S1
ILv/OD12
- TTL level bi-directional pin with 12 mA source-sink cap ability.
- TTL level bi-directional pin, can select to OD or OUT by register, with 12 mA
source-sink capability.
- TTL level bi-directional pin,Open-drain output with 16 mA source-sink capability, 5V
tolerance.
- Open-drain output pin with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
- TTL level bi-directional pin and schmitt trigger, Open-drain output with 12 mA sink
capability, 5V tolerance.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 8mA drive and
1mA sink capability.
- Low level bi-directional pin (VIH Æ 0.9V, VIL Æ 0.6V.). Output with 12mA sink
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O8-u47-5v
O8
O12
O30
AOUT
OD12
OD12-5v
OD24
INt5v
INts
INts5v
AIN
P
6.1
capability.
- Open-drain pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
- Output pin with 8 mA source-sink capability.
- Output pin with 12 mA source-sink capability.
- Output pin with 30 mA source-sink capability.
- Output pin(Analog).
- Open-drain output pin with 12 mA sink capability.
- Open-drain output pin with 12 mA sink capability, 5V tolerance.
- Open-drain output pin with 24 mA sink capability.
- TTL level input pin,5V tolerance.
- TTL level input pin and schmitt trigger.
- TTL level input pin and schmitt trigger, 5V tolerance.
- Input pin(Analog).
- Power.
Power Pin
Pin No.
4,37,99
68
86
88
20, 48, 73, 117
6.2
Pin Name
VCC
VSB
VBAT
AGND(D-)
GND
Type
P
P
P
P
P
LPC Interface
Pin No.
29
Pin Name
LRESET#
Type
INts5v
PWR
VCC
30
31
32
LDRQ#
SERIRQ
LFRAM#
O12
I/O12t
INts
VCC
VCC
VCC
36-33
LAD[3:0]
I/O12t
VCC
38
39
PCICLK
CLKIN
INts
INts
VCC
VCC
PWR
VCC
VCC
6.3
Description
Power supply voltage input with 3.3V
Stand-by power supply voltage input 3.3V
Battery voltage input
Analog GND
Digital GND
Description
Reset signal. It can connect to PCIRST# signal on the
host.
Encoded DMA Request signal.
Serial IRQ input/Output.
Indicates start of a new cycle or termination of a
broken cycle.
These signal lines communicate address, control, and
data information over the LPC bus between a host and
a peripheral.
33MHz PCI clock input.
System clock input. According to the input frequency
24/48MHz.
FDC
Pin No.
7
Pin Name
DENSEL#
Type
OD24
8
MOA#
OD24
Description
Drive Density Select.
Set to 1 - High data rate.(500Kbps, 1Mbps)
Set to 0 – Low data rate. (250Kbps, 300Kbps)
Motor A On. When set to 0, this pin enables disk drive
0. This is an open drain output.
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9
DRVA#
OD24
VCC
10
WDATA#
OD24
VCC
11
DIR#
OD24
VCC
12
STEP#
OD24
VCC
13
HDSEL#
OD24
VCC
14
15
16
WGATE#
RDATA#
TRK0#
OD24
INts5v
INts5v
VCC
VCC
VCC
17
INDEX#
INts5v
VCC
18
WPT#
INts5v
VCC
19
DSKCHG#
INts5v
VCC
6.4
Pin No.
27
UART, SIR and 80-Port
Pin Name
IRTX
Type
O12
118
GPIO42
IRRX
GPIO43
DCD1#
I/OOD12t
INts
I/OOD12t
INt5v
119
RI1#
INt5v
VCC
120
121
CTS1#
DTR1#
INt5v
O8-u47,5v
VCC
VCC
FAN60_100
INt5v
28
Drive Select A. When set to 0, this pin enables disk
drive A. This is an open drain output.
Write data. This logic low open drain writes
pre-compensation serial data to the selected FDD. An
open drain output.
Direction of the head step motor. An open drain output.
Logic 1 = outward motion
Logic 0 = inward motion
Step output pulses. This active low open drain output
produces a pulse to move the head to another track.
Head select. This open drain output determines which
disk drive head is active.
Logic 1 = side 0
Logic 0 = side 1
Write enable. An open drain output.
The read data input signal from the FDD.
Track 0. This Schmitt-triggered input from the disk
drive is active low when the head is positioned over
the outermost track.
This Schmitt-triggered input from the disk drive is
active low when the head is positioned over the
beginning of a track marked by an index hole.
Write protected. This active low Schmitt input from the
disk drive indicates that the diskette is write-protected.
Diskette change. This signal is active low at power on
and whenever the diskette is removed.
PWR
VCC
VSB
VCC
Description
Infrared Transmitter Output.
General Purpose IO
Infrared Receiver input.
General Purpose IO.
Data Carrier Detect. An active low signal indicates the
modem or data set has detected a data carrier.
Ring Indicator. An active low signal indicates that a ring
signal is being received from the modem or data set.
Clear To Send is the modem control input.
UART 1 Data Terminal Ready. An active low signal
informs the modem or data set that controller is ready
to communicate. Internal 47k ohms pulled high and
disable after power on strapping.
Power on strapping pin:
1(Default): (Internal pull high)
Power on fan speed default duty is 60%.(PWM)
0: (External pull down)
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Power on fan speed default duty is 100%.(PWM)
122
RTS1#
O8-u47,5v
VCC
VIDOUT_TRAP INt5v
UART 1 Request To Send. An active low signal informs
the modem or data set that the controller is ready to
send data. Internal 47k ohms pulled high and disable
after power on strapping.
Power on strapping pin:
1(Default) :
1. VIDIN[5-0]/OUT[5-0] pins will be VIDIN function.
2. VIDOUT[5-0]/GPIO0[5-0] pins will be VIDOUT function
0:
1. VIDIN[5-0]/OUT[5-0] pins will be VIDIN[5-0]/OUT[5-0]
function.(In-Out on the same pins)
2. VIDOUT[5-0]/GPIO0[5-0] pins will be GPIO0 function.
123
DSR1#
INt5v
VCC
124
SOUT1
O8-u47,5v
VCC
Config4E_2E
INt5v
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a
communication link and transfer data to the UART.
UART 1 Serial Output. Used to transmit serial data
out to the communication link. Internal 47k ohms pulled
high and disable after power on strapping.
Power on strapping:
1(Default): Configuration register Æ4E
0
: Configuration register Æ2E
Serial Input. Used to receive serial data through the
communication link.
Data Carrier Detect. An active low signal indicates
the modem or data set has detected a data carrier.
125
SIN1
INt5v
VCC
126
DCD2#
INt5v
VCC
127
SEGG
RI2#
O8
INt5v
SEGF
O8
128
CTS2#
H#
INt5v
O30
VCC
Clear To Send is the modem control input.
H# for 7-segment display
1
DTR2#
O8-u47,5v
VCC
SEGD
O8
UART 2 Data Terminal Ready. An active low signal
informs the modem or data set that controller is ready
to communicate. Internal 47k ohms pulled high and
disable after power on strapping.
SEGD for 7-segment display
FWH_TRAP
INt5v
RTS2#
O8-u47,5v
2
VCC
VCC
SEGG for 7-segment display
Ring Indicator. An active low signal indicates that a
ring signal is being received from the modem or data
set.
SEGF for 7-segment display
Power on strapping :
1(Default): SPI as a backup BIOS
0
: SPI as a primary BIOS
UART 2 Request To Send. An active low signal
informs the modem or data set that the controller is
ready to send data. Internal 47k ohms pulled high and
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disable after power on strapping.
SEGC
PWM_DC
3
O8
INt5v
DSR2#
INt5v
L#
O30
SEGC for 7-segment display
Power on strapping :
VCC
1 (Default): Fan control method will be PWM Mode
0 Drive :Fan control method will be Linear Mode
Data Set Ready. An active low signal indicates the
modem or data set is ready to establish a
communication link and transfer data to the UART.
L# for 7-segment display
5
SOUT2
O8-u47,5v
SEGB
O8
UART 2 Serial Output. Used to transmit serial data
out to the communication link. Internal 47k ohms
pulled high and disable after power on strapping.
SEGB for 7-segment display.
SPI_TRAP
INt5v
Power on strapping:
VCC
1(Default) : SPI function disable
6
SIN2
INt5v
VCC
66
SEGE
GPIO17
O8
I/OOD12t
VSB
SEGA
O8
6.5
0
: SPI function enable
Serial Input. Used to receive serial data through the
communication link.
SEGE for 7-segment display
General Purpose IO
SEGA for 7-segment display
Parallel Port
Pin No.
100
Pin Name
SLCT
Type
INts5v
PWR
VCC
101
PE
INts5v
VCC
102
BUSY
INts5v
VCC
103
ACK#
INts5v
VCC
104
SLIN#
OD12-5v
VCC
105
INIT#
OD12-5v
VCC
Description
An active high input on this pin indicates that the
printer is selected. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
An active high input on this pin indicates that the
printer has detected the end of the paper. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
An active high input indicates that the printer is not
ready to receive data. Refer to the description of the
parallel port for definition of this pin in ECP and EPP
mode.
An active low input on this pin indicates that the printer
has received data and is ready to accept more data.
Refer to the description of the parallel port for the
definition of this pin in ECP and EPP mode.
Output line for detection of printer selection. Refer to
the description of the parallel port for the definition of
this pin in ECP and EPP mode.
Output line for the printer initialization. Refer to the
-9-
May, 2008
V0.27P
F71883
106
ERR#
INts5v
VCC
107
AFD#
OD12-5v
VCC
108
STB#
OD12-5v
VCC
109
PD0
I/O12ts5v
VCC
110
111
112
113
114
115
116
PD1
PD2
PD3
PD4
PD5
PD6
PD7
I/O12ts5v
I/O12ts5v
I/O12ts5v
I/O12ts5v
I/O12ts5v
I/O12ts5v
I/O12ts5v
VCC
VCC
VCC
VCC
VCC
VCC
VCC
6.6
Parallel port data bus bit 0. Refer to the description of
the parallel port for the definition of this pin in ECP and
EPP mode.
Parallel port data bus bit 1.
Parallel port data bus bit 2.
Parallel port data bus bit 3.
Parallel port data bus bit 4.
Parallel port data bus bit 5.
Parallel port data bus bit 6.
Parallel port data bus bit 7.
Hardware Monitor
Pin No.
93-97
98
21
22
Pin Name
VIN6~VIN2
Vcore(VIN1)
FANIN1
FANCTL1
23
24
FANIN2
FANCTL2
25
FANIN3
GPIO40
26
89
description of the parallel port for the definition of this
pin in ECP and EPP mode.
An active low input on this pin indicates that the printer
has encountered an error condition. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
An active low output from this pin causes the printer to
auto feed a line after a line is printed. Refer to the
description of the parallel port for the definition of this
pin in ECP and EPP mode.
An active low output is used to latch the parallel data
into the printer. Refer to the description of the parallel
port for the definition of this pin in ECP and EPP mode.
Type
AIN
AIN
INt s 5 v
OD12-5v
AOUT
INt s 5 4 v
OD12-5v
AOUT
INt s 5 v
I/OOD12t
PWR
VCC
VCC
VCC
VCC
FANCTL3
OD12-5V
AOUT
VCC
GPIO41
I/OOD12t
Fan 3 control output. This pin provides PWM
duty-cycle output or a voltage output.
*This pin default function is FANCTL (PWM signal
output), please take care the application if user want to
implement GPIO function.
General purpose IO.
D3+(System)
AIN
VCC
Thermal diode/transistor temperature sensor input for
system use.
VCC
VCC
VCC
Description
Voltage Input 2 ~ 6.
Voltage Input for Vcore.
Fan 1 tachometer input.
Fan 1 control output. This pin provides PWM
duty-cycle output or a voltage output.
Fan 2 tachometer input.
Fan 2 control output. This pin provides PWM
duty-cycle output or a voltage output.
Fan 3 speed input.
General purpose IO.
-10-
May, 2008
V0.27P
F71883
90
91
D2+
D1+(CPU)
AIN
AIN
VCC
VCC
92
79
VREF
PME#
AOUT
OD12-5v
VCC
VSB
59
GPIO25
GPIO10
SPI_SLK
I/OOD12t
I/OOD12t
O12
VSB
FANIN4
GPIO11
INt s 5 v
I/OOD12t
SPI_CS0#
O12
FANCTL4
GPIO12
OD12-5v
AOUT
I/OOD12t
SPI_MISO
INt 5 v
SPI master in/slave out pin.
FANCTL1_1
OD12-5v
Fan 1 control output. This pin provides PWM
duty-cycle open drain output for Intel 4-pin Fan.
GPIO13
I/OOD12t
SPI_MOSI
O12
SPI master out/slave in pin.
BEEP
OD24
Beep pin.
GPIO14
I/OOD12t
FWH_DIS
WDTRST#
O12
OD12-5v
Firmware hub disable
Watch dog timer signal output.
SPI_CS1#
O12
OVT#
OD12-5v
When using two SPI Flashes for primary and back up
BIOS, please connect this pin to back up BIOS chip
select pin.
Over temperature signal output.
60
61
62
63
67
6.7
Pin No.
64
65
Thermal diode/transistor temperature sensor input.
CPU thermal diode/transistor temperature sensor
input. This pin is for CPU use.
Voltage sensor output.
Generated PME event. It supports the PCI PME#
interface. This signal allows the peripheral to request
the system to wake up from the S3 state.
General Purpose IO.
General purpose IO.
Serial clock output pin for SPI device.
VSB
Fan 4 tachometer input
General purpose IO.
VSB
Function A: When using firmware hub BIOS for
primary BIOS and SPI BIOS for second BIOS, please
connect this pin to SPI BIOS chip select pin.
Function B: When using two SPI Flashes for primary
and back up BIOS, please connect this pin to primary
BIOS chip select pin.
Fan 4 control output. This pin provides PWM
duty-cycle output or a voltage output.
General purpose IO.
VSB
VSB
VSB
General purpose IO.
General purpose IO.
ACPI Function Pins
Pin Name
GPIO15
LED_VSB
Type
I/OOD12t
OD12
ALERT#
GPIO16
OD12
I/OOD12t
PWR
VSB
VSB
Description
General purpose IO.
Power LED for VSB.
Alert a signal when temperature over limit setting.
General purpose IO.
LED_VCC
OD12
Power LED for VCC.
Turbo2#
INts5v
VID Turbo 2 enable control pin. (Patent Issue)
-11-
May, 2008
V0.27P
F71883
74
VSB
PCIRST1#
GPIO20
PCIRST2#
GPIO21
PCIRST3#
OD12
I/OOD12
O12
I/OOD12
O12
GPIO22
GPIO23
RSTCON#
I/OOD12
I/OOD12
OD12
ATXPG_IN
GPIO24
PWSIN#
GPIO26
PWSOUT#
AIN
I/OOD12t
INts5v
I/OOD12t
OD12
83
GPIO27
S3#
GPIO30
PSON#
I/OOD12t
INts5v
I/OOD12t
OD12-5v
84
GPIO31
PWROK
I/OOD12t
OD12
VBAT
85
GPIO32
RSMRST#
I/OOD12t
OD12
VBAT
87
GPIO33
COPEN#
I/OOD12t
INts5v
VBAT
Pin Name
VIDIN[4:0]
Type
INts5v
PWR
VCC
OUT[4:0]
O12
VIDIN5
INts5v
OUT5
O12
75
76
77
78
80
81
82
6.8
Pin No.
46-42
47
VSB
VSB
VSB
VSB
VSB
VSB
VSB
VSB
It is a output buffer of RSTCON# and LRESET#.
General purpose IO.
It is a output buffer of RSTCON# and LRESET#.
General purpose IO.
It is a output buffer of RSTCON# and LRESET#.
General purpose IO.
General purpose IO. (Default)
RESET Connect# with 50ms debouce function, it
connects to reset button, and also other reset source
on the motherboard.
ATX Power Good input.
General purpose IO.
Main power switch button input.
General purpose IO.
Panel Switch Output. This pin is low active and pulse
output. It is power on request output#.
General purpose IO.
S3# Input is Main power on-off switch input.
General purpose IO.
Power supply on-off control output. Connect to ATX
power supply PS_ON# signal.
General purpose IO.
PWROK function, It is power good signal of VCC,
which is delayed 400ms (default) as VCC arrives at
2.8V.
General purpose IO.
Resume Reset# function, It is power good signal of
VSB, which is delayed 66ms as VSB arrives at 2.3V.
General purpose IO.
Case Open Detection #. This pin is connected to a
specially designed low power CMOS flip-flop backed
by the battery for case open state preservation during
power loss.
VID Controller
VCC
Description
CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
CPU VID output pins.
(These is for VID in-out function at the same pin)
(Power On Trapping by pin 122)
CPU VID input pins.
Special level input VIHÆ 0.9, VIL Æ 0.6
CPU VID output pins.
(These is for VID in-out function at the same pin)
(Power On Trapping by pin 122)
-12-
May, 2008
V0.27P
F71883
53-49
54
SID
VIDOUT[4:0]
ILv/OD12
OD12
GPIO[4:0]
VIDOUT5
GPIO5
I/OOD12t
OD12
I/OOD12t
VSB
VSB
General purpose pin. (Power On Trapping by pin 122)
CPU VID output pins.
General purpose pin. (Power On Trapping by pin 122)
55
SIC
SLOTOCC#
INts5v
56
GPIO06
GPIO07
I/OOD12t
I/OOD12t
Turbo1#
WDTRST#
VSI
SST
INts5v
OD12-5v
AIN
ILv/OD8-S1
VSO
PECI
AOUT
ILv/OD8-S1
VSB
Easy voltage sensor output for Vcore change use.
Intel PECI hardware monitor interface.
57
58
6.9
OD12
AMDSI interface data input.
CPU VID output pins.
VSB
AMDSI interface clock output.
CPU SLOTOCC# input.
VSB
General purpose pin.
General purpose pin.
VSB
VID Turbo 1 enable control pin. (Patent Issue)
Watch dog timer signal output.
Easy voltage sensor input for Vcore change use.
Intel SST hardware monitor interface.
KPC Function
Pin No.
40
Pin Name
KBRST#
Type
OD16-u10,5V
PWR
VCC
41
GA20
OD16-u10,5V
VCC
69
KDATA
I/OD16t,5V
VSB
Description
Keyboard reset. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P20)
Gate A20 output. This pin is high after system reset.
Internal pull high 3.3V with 10k ohms. (KBC P21)
Keyboard Data.
70
KCLK
I/OD16t,5V
VSB
Keyboard Clock.
71
MDAT
I/OD16t,5V
VSB
PS2 Mouse Data.
72
MCLK
I/OD16t,5V
VSB
PS2 Mouse Clock.
-13-
May, 2008
V0.27P
F71883
7. Function Description
7.1
Power on Strapping Option
The F71883 provides four pins for power on hardware strapping to select functions. There is
a form to describe how to set the functions you want.
Pin No.
1
7.2
Symbol
FWH_TRAP
2
PWM_DC
5
SPI_TRAP
121
FAN60_100
122
VIDOUT
124
Config4E_2E
Value
1
0
1
0
1
0
1
0
1
0
1
0
Description
SPI as a backup BIOS (Default)
SPI as a primary BIOS
Fan control mode: PWM mode. ( Default)
Fan control mode: Linear mode.
SPI function disable (Default)
SPI function enable
Power on Fan speed default duty is 60%(PWM)(Default)
Power on Fan speed default duty is 100%(PWM)
6 pins VIDIN and 6 pins VIDOUT (Default)
VIDIN/OUT on 6 pins , Original VIDOUT pins will be GPIO
pins.
Configuration Register I/O port is 4E/4F. (Default)
Configuration Register I/O port is 2E/2F.
FDC
The Floppy Disk Controller provides the interface between a host processor and one
floppy disk drives. It integrates a controller and a digital data separator with write
pre-compensation, data rate selection logic, microprocessor interface, and a set of registers.
The FDC supports data transfer rates of 250 Kbps, 300 Kbps, 500 Kbps, and 1 Mbps. It
operates in PC/AT mode and supports 3-mode type drives.
The FDC configuration is handled by software and a set of Configuration registers.
Status, Data, and Control registers facilitate the interface between the host microprocessor
and the disk drive, providing information about the condition and/or state of the FDC. These
configuration registers can select the data rate, enable interrupts, drives, and DMA modes,
and indicate errors in the data or operation of the FDC/FDD. The controller manages data
transfers using a set of data transfer and control commands. These commands are handled in
three phases: Command, Execution, and Result. Not all commands utilize all these three
phases.
The below content is about the FDC device register descriptions. All the registers are for
software porting reference.
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May, 2008
V0.27P
F71883
Status Register A (PS/2 mode)  Base + 0
Bit
Name
R/W Default
Description
7
INTPEND
R
0
This bit indicates the state of the interrupt output.
6
DRV2_N
R
-
0: a second drive has been installed.
1: a second drive has not been installed.
5
STEP
R
0
This bit indicates the complement of STEP# disk interface output.
4
TRK0_N
R
-
This bit indicates the state of TRK0# disk interface input.
3
HDSEL
R
0
This bit indicates the complement of HDSEL# disk interface output.
0: side 0.
1: side 1.
2
INDEX_N
R
-
This bit indicates the state of INDEX# disk interface input.
1
WPT_N
R
-
This bit indicates the state of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0
DIR
R
0
This bit indicates the complement of DIR# disk interface output.
Status Register A (Model 30 mode)  Base + 0
Bit
Name
R/W Default
Description
7
INTPEND
R
0
This bit indicates the state of the interrupt output.
6
DRQ
R
0
This bit indicates the state of the DRQ signal.
5
STEP_FF
R
0
This bit indicates the complement of latched STEP# disk interface output.
4
TRK0
R
-
This bit indicates the complement of TRK0# disk interface input.
3
HDSEL_N
R
1
This bit indicates the state of HDSEL# disk interface output.
0: side 0.
1: side 1.
2
INDEX
R
-
This bit indicates the complement of INDEX# disk interface input.
1
WPT
R
-
This bit indicates the complement of WPT# disk interface input.
0: disk is write-protected.
1: disk is not write-protected.
0
DIR_N
R
1
This bit indicates the state of DIR# disk interface output.
0: head moves in inward direction.
1: head moves in outward direction.
Status Register B (PS/2 Mode)  Base + 1
Bit
Name
7-6 Reserved
R/W Default
R
11
Description
Reserved. Return 11b when read.
5
DR0
R
0
Drive select 0. This bit reflects the bit 0 of Digital Output Register.
4
WDATA
R
0
This bit changes state at every rising edge of WDATA#.
3
RDATA
R
0
This bit changes state at every rising edge of RDATA#.
2
WGATE
R
0
This bit indicates the complement of WGATE# disk interface output.
1
MOTEN1
R
0
This bit indicates the complement of MOB# disk interface output. Not support
in this design.
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May, 2008
V0.27P
F71883
0
MOTEN0
R
0
This bit indicates the complement of MOA# disk interface output.
Status Register B (Model 30 Mode)  Base + 1
Bit
Name
R/W Default
Description
7
DRV2_N
R
-
0: a second drive has been installed.
1: a second drive has not been installed.
6
DSB_N
R
1
This bit indicates the state of DRVB# disk interface output. Not support in this
design.
5
DSA_N
R
1
This bit indicates the state of DRVA# disk interface output.
4
WDATA_FF
R
0
This bit is latched at the rising edge of WDATA# and is cleared by a read from
the Digital Input Register.
3
RDATA_FF
R
0
This bit is latched at the rising edge of RDATA# and is cleared by a read form
the Digital Input Register.
2
WGATE_FF
R
0
This bit is latched at the falling edge of WGATE# and is cleared by a read from
the Digital Input Register.
1
DSD_N
R
1
This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0
DSC_N
R
1
This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
Digital Output Register  Base + 2
Bit
Name
R/W Default
Description
7
MOTEN3
R
0
Motor enable 3. Not support in this design.
6
MOTEN2
R
0
Motor enable 2. Not support in this design.
5
MOTEN1
R/W
0
Motor enable 1. Used to control MOB#. MOB# is not support in this design.
4
MOTEN0
R/W
0
Motor enable 0. Used to control MOA#.
3
DAMEN
R/W
0
DMA enable. This bit has two mode of operation.
PC-AT and Model 30 mode: write 1 will enable DMA and IRQ, write 0 will
disable DMA and IRQ.
PS/2 mode: This bit is reserved. DMA and IRQ are always enabled in PS/2
mode.
2
RESET
R
0
Write 0 to this bit will reset the controller. I will remain in reset condition until a 1
is written.
1
DSD_N
R
1
This bit indicates the complement of DRVD# disk interface output. Not support
in this design.
0
DSC_N
R
1
This bit indicates the complement of DRVC# disk interface output. Not support
in this design.
Tape Drive Register  Base + 3
Bit
Name
R/W Default
Description
7-6 Reserved
R
00
Reserved. Return 00b when read.
5-4 TYPEID
R
11
Reserved in normal function, return 11b when read.
If 3 mode FDD function is enabled. These bits indicate the drive type ID.
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May, 2008
V0.27P
F71883
3-2 Reserved
R
11
Reserved. Return 11b when read in normal function.
Return 00b when read in 3 mode FDD function.
1-0 TAPESEL
R/W
0
These bits assign a logical drive number to be a tape drive.
Main Status Register  Base + 4
Bit
Name
R/W Default
Description
7
RQM
R
0
Request for Master indicates that the controller is ready to send or receive data
from the uP through the FIFO.
6
DIO
R
0
Data I/O (direction):
0: the controller is expecting a byte to be written to the Data Register.
1: the controller is expecting a byte to be read from the Data Register.
5
NON_DMA
R
0
Non DMA Mode:
0: the controller is in DAM mode.
1: the controller is interrupt or software polling mode.
4
FDC_BUSY
R
0
This bit indicate that a read or write command is in process.
3
DRV3_BUSY
R
0
FDD number 3 is in seek or calibration condition. FDD number 3 is not support
in this design.
2
DRV2_BUSY
R
0
FDD number 2 is in seek or calibration condition. FDD number 2 is not support
in this design.
1
DRV1_BUSY
R
0
FDD number 1 is in seek or calibration condition. FDD number 1 is not support
in this design.
0
DRV0_BUSY
R
0
FDD number 0 is in seek or calibration condition.
Data Rate Select Register  Base + 4
Bit
7
6
Name
SOFTRST
PWRDOWN
5 Reserved
4-2 PRECOMP
R/W Default
W
W
0
0
W
000
Description
A 1 written to this bit will software reset the controller. Auto clear after reset.
A 1 to this bit will put the controller into low power mode which will turn off the
oscillator and data separator circuits.
Return 0 when read.
Select the value of write precompensation:
250K-1Mbps
2Mbps
000: default delays
default delays
001: 41.67ns
20.8ns
010: 83.34ns
41.17ns
011: 125.00ns
62.5ns
100: 166.67ns
83.3ns
101: 208.33ns
104.2ns
110: 250.00ns
125.00ns
111: 0.00ns (disabled)
0.00ns (disabled)
The default value of corresponding data rate:
250Kbps: 125ns
300Kbps: 125ns
500Kbps: 125ns
1Mbps: 41.67ns
2Mbps: 20.8ns
-17-
May, 2008
V0.27P
F71883
1-0 DRATE
W
10
Data rate select:
MFM
00: 500Kbps
01: 300Kbps
10: 250Kbps
11: 1Mbps
FM
250Kbps
150Kbps
125Kbps
illegal
Data (FIFO) Register  Base + 5
Bit
Name
7-0 DATA
R/W Default
R/W
00h
Description
The FIFO is used to transfer all commands, data and status between controller
and the system. The Data Register consists of four status registers in a stack
with only one register presented to the data bus at a time. The FIFO is default
disabled and could be enabled via the CONFIGURE command.
Status Registers 0
Bit
Name
7-6 IC
R/W Default
Description
R
-
Interrupt code :
00: Normal termination of command.
01: Abnormal termination of command.
10: Invalid command.
11: Abnormal termination caused by poling.
5
SE
R
-
Seek end.
Set when a SEEK or RECALIBRATE or a READ or WRITE with implied seek
command is completed.
4
EC
R
-
Equipment check.
0: No error
1: When a fault signal is received form the FDD or the TRK0# signal fails to
occur after 77 step pulses.
3
NR
R
-
Not ready.
0: Drive is ready
1: Drive is not ready.
2
HD
R
-
Head address.
The current head address.
1-0 DS
R
-
Drive select.
00: Drive A selected.
01: Drive B selected.
10: Drive C selected.
11: Drive D selected.
Status Registers 1
Bit
Name
R/W Default
Description
7
EN
R
-
End of Track.
Set when the FDC tries to access a sector beyond the final sector of a cylinder.
6
DE
R
-
Data Error.
The FDC detect a CRC error in either the ID field or the data field of a sector.
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May, 2008
V0.27P
F71883
4
OR
R
-
Overrun/Underrun.
Set when the FDC is not serviced by the host system within a certain time
interval during data transfer.
3
Reserved
-
-
Unused. This bit is always “0”
2
ND
R
-
No Data.
Set when the following conditions occurred:
1. The specified sector is not found during any read command.
2. The ID field cannot be read without errors during a READ ID command.
3. The proper sector sequence cannot be found during a READ TRACK
command.
1
NW
R
-
No Writable
Set when WPT# is active during execution of write commands.
0
MA
R
-
Missing Address Mark.
Set when the following conditions occurred:
1. Cannot detect an ID address mark at the specified track after
encountering the index pulse form the INDEX# pin twice.
2. Cannot detect a data address mark or a deleted data address mark on the
specified track.
Status Registers 2
Bit
Name
R/W Default
Description
7
Reserved
-
-
Unused. This bit is always “0”.
6
CM
R
-
Control Mark.
Set when following conditions occurred:
1. Encounters a deleted data address mark during a READ DATA command.
2. Encounters a data address mark during a READ DELETED DATA
command.
5
DD
R
-
Data Error in Data Field.
The FDC detects a CRC error in the data field.
4
WC
R
-
Wrong Cylinder.
Set when the track address from the sector ID field is different from the track
address maintained inside the FDC.
3
SE
R
-
Scan Equal.
Set if the equal condition is satisfied during execution of the SCAN command.
2
SN
R
-
Scan Not Satisfied.
Set when the FDC cannot find a sector on the track which meets the desired
condition during any scan command.
1
BC
R
-
Bad Cylinder.
The track address from the sector ID field is different from the track address
maintained inside the FDC and is equal to FFh which indicates a bad track.
0
MD
R
-
Missing Data Address Mark.
Set when the FDC cannot detect a data address mark or a deleted data
address mark.
Status Registers 3
Bit
Name
R/W Default
Description
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May, 2008
V0.27P
F71883
7
Reserved
-
-
Unused. This bit is always “0”.
6
WP
R
-
Write Protect.
Indicates the status of WPT# pin.
5
Reserved
R
-
Unused. This bit is always “1”.
4
T0
R
-
Track 0.
Indicates the status of the TRK0# pin.
3
Reserved.
R
-
Unused. This bit is always “1”.
2
HD
R
-
Head Address.
Indicates the status of the HDSEL# pin.
1
DS1
R
-
0
DS0
R
-
Drive Select.
These two bits indicate the DS1, DS0 bits in the command phase.
Digital Input Register (PC-AT Mode)  Base + 7
Bit
7
Name
R/W Default
Description
DSKCHG
R
-
This bit indicates the complement of DSKCHG# disk interface input.
6-0 Reserved
R
-
Reserved.
Digital Input Register (PS/2 Mode)  Base + 7
Bit
7
Name
R/W Default
Description
DSKCHG
R
-
This bit indicates the complement of DSKCHG# disk interface input.
6-3 Reserved
-
-
Reserved.
2-1 DRATE
R
10
These bits indicate the status of the DRATE programmed through the Data
Rate Select Register or Configuration Control Register.
R
1
0: 1Mbps or 500Kbps data rate is chosen.
1: 300Kbps or 250Kbps data rate is chosen.
0
HIGHDEN_N
Digital Input Register (Model 30 Mode)  Base + 7
Bit
7
Name
DSKCHG_N
6-4 Reserved
R/W Default
Description
R
-
This bit indicates the state of DSKCHG# disk interface input.
-
-
Reserved.
3
DMAEN
R
0
This bit reflects the DMA bit in Digital Output Register.
2
NOPRE
R
0
This bit reflects the NOPRE bit in Configuration Control Register.
1-0 DRATE
R
10
These bits indicate the status of DRATE programmed through the Data Rate
Select Register or Configuration Control Register.
Configuration Control Register (PC-AT and PS/2 Mode)  Base + 7
Bit
Name
7-2 Reserved
R/W Default
-
-
Description
Reserved.
-20-
May, 2008
V0.27P
F71883
1-0 DRATE
W
10
These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
Configuration Control Register (Model 30 Mode)  Base + 7
Bit
Name
7-3 Reserved
R/W Default
Description
-
-
Reserved.
NOPRE
W
0
This bit could be programmed through Configuration Control Register and be
read through the bit 2 in Digital Input Register in Model 30 Mode. But it has no
functionality.
1-0 DRATE
W
10
These bit determine the data rate of the floppy controller. See DRATE bits in
Data Rate Select Register.
2
FDC Commands
Terminology:
C
D
DIR
Cylinder Number 0 -256
Data Pattern
Step Direction
0: step out
1: step in
DS0
Drive Select 0
DS1
Drive Select 1
DTL
Data Length
EC
Enable Count
EOT
End of Track
EFIFO
Enable FIFO
0: FIFO is enabled.
1: FIFO is disabled.
EIS
Enable Implied Seek
FIFOTHR FIFO Threshold
GAP
Alters Gap Length
GPL
Gap Length
H/HDS
Head Address
HLT
Head Load Time
HUT
Head Unload Time
LOCK
Lock EFIFO, FIFOTHR, PTRTRK bits.
Prevent these bits from being affected by software reset.
MFM
MFM or FM mode
0: FM
1: MFM
MT
Multi-Track
N
Sector Size Code. All values up to 07h are allowable.
00:
128 bytes
01:
256 bytes
..
..
07
16 Kbytes
NCN
New Cylinder Number
ND
Non-DMA Mode
OW
Overwritten
PCN
Present Cylinder Number
POLL
Polling disable
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May, 2008
V0.27P
F71883
PRETRK
R
RCN
SC
SK
SRT
ST0
ST1
ST2
ST3
WGATE
Read Data
Phase
Command
0: polling is enabled.
1: polling is disabled.
Precompensation Start Track Number
Sector address
Relative Cylinder Number
Sector per Cylinder
Skip deleted data address mark
Step Rate Time
Status Register 0
Status Register 1
Status Register 2
Status Register 3
Write Gate alters timing of WE.
R/W
W
D7
MT
D6
MFM
D5
SK
D4
0
D3
0
D2
1
D1
1
D0
0
W
0
0
0
0
0
HDS
DS1
DS0
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
---------------------------- DTL --------------------------
Sector ID
information prior to
command
execution
Execution
Result
R
R
---------------------------- ST0 ------------------------------------------------------ ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Read Deleted Data
Phase
R/W
Command
W
W
Data transfer
between the FDD
and system
Status information
after command
execution.
Sector ID
information after
command
execution.
D7
MT
D6
MFM
D5
SK
D4
0
D3
1
D2
1
D1
0
D0
0
0
0
0
0
0
HDS
DS1
DS0
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
-22-
Remark
Command code
Remark
Command code
Sector ID
information prior to
command
execution
May, 2008
V0.27P
F71883
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
---------------------------- DTL --------------------------
Execution
Result
R
R
---------------------------- ST0 ------------------------------------------------------ ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Read A Track
Phase
R/W
Command
W
W
Sector ID
information after
command
execution.
D7
0
D6
MFM
D5
0
D4
0
D3
0
D2
0
D1
1
D0
0
0
0
0
0
0
HDS
DS1
DS0
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
---------------------------- DTL --------------------------
Execution
Result
Data transfer
between the FDD
and system
Status information
after command
execution.
R
R
---------------------------- ST0 ------------------------------------------------------ ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
-23-
Remark
Command code
Sector ID
information prior to
command
execution
Data transfer
between the FDD
and system. FDD
reads contents of
all cylinders from
index hole to EOT.
Status information
after command
execution.
Sector ID
information after
command
execution.
May, 2008
V0.27P
F71883
Read ID
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
MFM
0
0
1
0
1
0
W
0
0
0
0
0
HDS
DS1
DS0
Execution
Result
Remark
Command code
The first correct ID
information on the
cylinder is stored in
Data Register.
R
---------------------------- ST0 --------------------------
R
----------------------------- ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Status information
after command
execution.
Disk status after
the command has
been completed.
Verify
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
MT
MFM
SK
1
0
1
1
0
W
EC
0
0
0
0
HDS
DS1
DS0
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
-------------------------- DTL/SC ------------------------
Command code
Sector ID
information prior to
command
execution
Execution
Result
Remark
No data transfer
R
---------------------------- ST0 --------------------------
R
----------------------------- ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Status information
after command
execution.
Sector ID
information after
command
execution.
Version
Phase
R/W
D7
D6
D5
D4
-24-
D3
D2
D1
D0
Remark
May, 2008
V0.27P
F71883
Command
W
0
0
0
1
0
0
0
0
Command code
Result
R
1
0
0
1
0
0
0
0
Enhanced
controller
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
MT
MFM
0
0
0
1
0
1
W
0
0
0
0
0
HDS
DS1
DS0
Write Data
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
---------------------------- DTL --------------------------
Command code
Sector ID
information prior to
command
execution
Execution
Result
Remark
Data transfer
between the FDD
and system.
R
---------------------------- ST0 --------------------------
R
----------------------------- ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Status information
after command
execution.
Sector ID
information after
command
execution.
Write Deleted Data
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
MT
MFM
0
0
1
0
0
1
W
0
0
0
0
0
HDS
DS1
DS0
W
----------------------------- C ---------------------------
W
----------------------------- H ---------------------------
W
----------------------------- R ---------------------------
W
------------------------------ N ---------------------------
W
---------------------------- EOT --------------------------
W
---------------------------- GPL --------------------------
W
---------------------------- DTL --------------------------
-25-
Remark
Command code
Sector ID
information prior to
command
execution
May, 2008
V0.27P
F71883
Execution
Data transfer
between the FDD
and system.
Result
R
---------------------------- ST0 --------------------------
R
----------------------------- ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
----------------------------- C ---------------------------
R
----------------------------- H ---------------------------
R
----------------------------- R ---------------------------
R
----------------------------- N ---------------------------
Status information
after command
execution.
Sector ID
information after
command
execution.
Format A Track
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
MFM
0
0
1
1
0
1
W
0
0
0
0
0
HDS
DS1
DS0
Execution
for each
sector
( repeat )
Result
Remark
Command code
W
------------------------------ N ---------------------------
Bytes/Sector
W
---------------------------- SC --------------------------
Sectors/Cylinder
W
---------------------------- GPL --------------------------
Gap 3 Length
W
----------------------------- D ---------------------------
Data Pattern
------------------------------ C ---------------------------
Input sector
parameter.
W
------------------------------ H ---------------------------
W
------------------------------ R ---------------------------
W
----------------------------- N --------------------------
R
---------------------------- ST0 --------------------------
R
----------------------------- ST1 --------------------------
R
---------------------------- ST2 --------------------------
R
------------------------- Undefined ----------------------
R
------------------------- Undefined ----------------------
R
-------------------------- Undefined -----------------------
R
------------------------- Undefined ----------------------
Status information
after command
execution.
Recalibrate
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
0
1
1
1
W
0
0
0
0
0
0
DS1
DS0
Execution
Remark
Command code
Head retracted to
track 0
-26-
May, 2008
V0.27P
F71883
Sense Interrupt Status
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
1
0
0
0
Result
R
---------------------------- ST0 --------------------------
R
---------------------------- PCN --------------------------
Remark
Command code
Specify
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
0
0
1
1
W
|------------------ SRT -------------------|
W
|------------------------------------- SRT ---------------------------------------|
Remark
Command code
|------------------ HUT -------------------|
ND
Seek
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
1
1
1
1
W
0
0
0
0
0
HDS
DS1
DS0
W
Remark
Command code
---------------------------- NCN --------------------------
Execution
Head positioned
over proper
cylinder on diskette
Configure
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
1
0
0
1
1
W
0
0
0
0
0
HDS
DS1
DS0
W
0
EIS
EFIFO
POLL
W
Remark
Command code
|---------------- FIFOTHR ---------------|
---------------------------- PRETRK --------------------------
Execution
Internal registers
written
Relative Seek
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
1
DIR
0
0
1
1
1
1
W
0
0
0
0
0
HDS
DS1
DS0
W
Remark
Command code
---------------------------- RCN --------------------------
Perpendicular Mode
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
1
0
0
1
0
W
OW
0
D3
D2
D1
D0
GAP
WGATE
-27-
Remark
Command code
May, 2008
V0.27P
F71883
Lock
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
LOCK
0
0
1
0
1
0
0
Result
R
0
0
0
LOCK
0
0
0
0
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
1
1
1
0
Result
R
-------------------------- PCN ( Drive 0 ) ------------------------
R
-------------------------- PCN ( Drive 0 ) ------------------------
R
-------------------------- PCN ( Drive 0 ) ------------------------
R
-------------------------- PCN ( Drive 0 ) ------------------------
Remark
Command code
Dumpreg
R
|------------------ SRT -------------------|
R
|------------------------------------- SRT ---------------------------------------|
R
Remark
Command code
|------------------ HUT -------------------|
ND
-------------------------- SC/EOT ------------------------
R
LOCK
0
D3
D2
R
0
EIS
EFIFO
POLL
R
D1
D0
GAP
WGATE
|---------------- FIFOTHR ---------------|
---------------------------- PRETRK --------------------------
Sense Drive Status
Phase
R/W
D7
D6
D5
D4
D3
D2
D1
D0
Command
W
0
0
0
0
0
1
0
0
W
0
0
0
0
0
HDS
DS1
DS0
Result
R
---------------------------- ST3 --------------------------
Remark
Command code
Status information
abut disk drive
Invalid
Phase
R/W
Command
W
---------------------------- Invalid Codes --------------------------
Result
R
---------------------------- ST0 --------------------------
7.3
D7
D6
D5
D4
D3
D2
D1
D0
Remark
FDC goes to
standby state.
ST0 = 80h
UART
The F71883 provides two UART ports and supports IRQ sharing for system application.
The UARTs are used to convert data between parallel format and serial format. They convert
parallel data into serial format on transmission and serial format into parallel data on receiver
-28-
May, 2008
V0.27P
F71883
side. The serial format is formed by one start bit, followed by five to eight data bits, a parity bit
if programmed and one ( 1.5 or 2 ) stop bits. The UARTs include complete modem control
capability and an interrupt system that may be software trailed to the computing time required
to handle the communication link. They have FIFO mode to reduce the number of interrupts
presented to the host. Both receiver and transmitter have a 16-byte FIFO.
The below content is about the UART1 and UART2 device register descriptions. All the
registers are for software porting reference.
Receiver Buffer Register  Base + 0
Bit
Name
7-0 RBR
R/W Default
R
Description
The data received.
Read only when LCR[7] is 0
00h
Transmitter Holding Register  Base + 0
Bit
Name
7-0 THR
R/W Default
W
00h
Description
Data to be transmitted.
Write only when LCR[7] is 0
Divisor Latch (LSB)  Base + 0
Bit
Name
7-0 DLL
R/W Default
R/W
01h
Description
Baud generator divisor low byte.
Access only when LCR[7] is 1.
Divisor Latch (MSB)  Base + 1
Bit
Name
7-0 DLM
R/W Default
R/W
00h
Description
Baud generator divisor high byte.
Access only when LCR[7] is 1.
Interrupt Enable Register  Base + 1
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
EDSSI
R/W
0
Enable Modem Status Interrupt. Access only when LCR[7] is 0.
2
ELSI
R/W
0
Enable Line Status Error Interrupt. Access only when LCR[7] is 0.
1
ETBFI
R/W
0
Enable Transmitter Holding Register Empty Interrupt. Access only when
LCR[7] is 0.
0
ERBFI
R/W
0
Enable Received Data Available Interrupt. Access only when LCR[7] is 0.
Interrupt Identification Register  Base + 2
Bit
7
Name
FIFO_EN
R/W Default
R
0
Description
0: FIFO is disabled
1: FIFO is enabled.
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May, 2008
V0.27P
F71883
FIFO_EN
R
0
0: FIFO is disabled
1: FIFO is enabled.
5-4 Reserved
-
-
Reserved.
3-1 IRQ_ID
R
000
R
1
6
0
IRQ_PENDN
000: Interrupt is caused by Modem Status
001: Interrupt is caused by Transmitter Holding Register Empty
010: Interrupt is caused by Received Data Available.
110: Interrupt is caused by Character Timeout
011: Interrupt is caused by Line Status.
1: Interrupt is not pending.
0: Interrupt is pending.
FIFO Control Register  Base + 2
Bit
Name
7-6 RCV_TRIG
5-3 Reserved
R/W Default
Description
00: Receiver FIFO trigger level is 1.
01: Receiver FIFO trigger level is 4.
10: Receiver FIFO trigger level is 8.
11: Receiver FIFO trigger level is 14.
W
00
-
-
Reserved.
2
CLRTX
R
0
Reset the transmitter FIFO.
1
CLRRX
R
0
Reset the receiver FIFO.
0
FIFO_EN
R
0
0: Disable FIFO.
1: Enable FIFO.
Line Control Register  Base + 3
Bit
Name
R/W Default
7
DLAB
R/W
0
6
SETBRK
R/W
0
5
STKPAR
R/W
0
4
EPS
R/W
0
3
PEN
R/W
0
2
STB
R/W
0
1-0 WLS
R/W
00
Description
0: Divisor Latch can’t be accessed.
1: Divisor Latch can be accessed via Base and Base+1.
0: Transmitter is in normal condition.
1: Transmit a break condition.
XX0: Parity Bit is disable
001: Parity Bit is odd.
011: Parity Bit is even
101: Parity Bit is logic 1
111: Parity Bit is logic 0
0: Stop bit is one bit
1: When word length is 5 bit stop bit is 1.5 bit
else stop bit is 2 bit
00: Word length is 5 bit
01: Word length is 6 bit
10: Word length is 7 bit
11: Word length is 8 bit
MODEM Control Register  Base + 4
Bit
Name
7-5 Reserved
R/W Default
Description
-
-
Reserved.
0: UART in normal condition.
1: UART is internal loop back
0: All interrupt is disabled.
1: Interrupt is enabled
(disabled) by IER.
4
LOOP
R/W
0
3
OUT2
R/W
0
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May, 2008
V0.27P
F71883
2
OUT1
R/W
0
Read from MSR[6] is loop back mode
1
RTS
R/W
0
0
DTR
R/W
0
0: RTS# is forced to logic 1
1: RTS# is forced to logic 0
0: DTR# is forced to logic 1
1: DTR# is forced to logic 0
Line Status Register  Base + 5
Bit
Name
R/W Default
7
RCR_ERR
R
0
6
TEMT
R
1
5
THRE
R
1
4
BI
R
0
3
FE
R
0
2
PE
R
0
1
OE
R
0
0
DR
R
0
Description
0: No error in the FIFO when FIFO is enabled
1: Error in the FIFO when FIFO is enabled.
0: Transmitter is in transmitting.
1: Transmitter is empty.
0: Transmitter Holding Register is not empty.
1: Transmitter Holding Register is empty.
0: No break condition detected.
1: A break condition is detected.
0: Data received has no frame error.
1: Data received has frame error.
0: Data received has no parity error.
1: Data received has parity error.
0: No overrun condition occurred.
1: An overrun condition occurred.
0: No data is ready for read.
1: Data is received.
MODEM Status Register  Base + 6
Bit
Name
R/W Default
7
DCD
R
-
6
RI
R
-
5
DSR
R
-
4
CTS
R
-
3
DDCD
R
0
2
TERI
R
0
1
DDSR
R
0
0
DCTS
R
0
Description
Complement of DCD# input. In loop back mode, this bit is equivalent to OUT2
in MCR.
Complement of RI# input. In loop back mode , this bit is equivalent to OUT1 in
MCR
Complement of DSR# input. In loop back mode , this bit is equivalent to DTR in
MCR
Complement of CTS# input. In loop back mode , this bit is equivalent to RTS in
MCR
0: No state changed at DCD#.
1: State changed at DCD#.
0: No Trailing edge at RI#.
1: A low to high transition at RI#.
0: No state changed at DSR#.
1: State changed at DSR#.
0: No state changed at CTS#.
1: State changed at CTS#.
Scratch Register  Base + 7
Bit
7-0 SCR
Name
R/W Default
R/W
00h
Description
Scratch register.
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May, 2008
V0.27P
F71883
7.4
Parallel Port
The parallel port in F71883 supports an IBM XT/AT compatible parallel port ( SPP ),
bi-directional paralle port ( BPP ), Enhanced Parallel Port ( EPP ), Extended Capabilities
Parallel Port ( ECP ) mode. Refer to the configuration registers for more information on
selecting the mode of operation.
The below content is about the Parallel Port device register descriptions. All the
registers are for software porting reference.
Parallel Port Data Register  Base + 0
Bit
Name
7-0 DATA
R/W Default
R/W
00h
Description
The output data to drive the parallel port data lines.
ECP Address FIFO Register  Base + 0
Bit
Name
7-0 ECP_AFIFO
R/W Default
R/W
00h
Description
Access only in ECP Parallel Port Mode and the ECP_MODE programmed in
the Extended Control Register is 011.
The data written to this register is placed in the FIFO and tagged as an
Address/RLE. It is auto transmitted by the hardware. The operation is only
defined for forward direction. It divide into two parts :
Bit 7 :
0: bits 6-0 are run length, indicating how many times the next byte to appear (0
= 1time, 1 = 2times, 2 = 3times and so on).
1: bits 6-0 are a ECP address.
Bit 6-0 :
Address or RLE depends on bit 7.
Device Status Register  Base + 1
Bit
Name
R/W Default
Description
7
BUSY_N
R
-
Inverted version of parallel port signal BUSY.
6
ACK_N
R
-
Version of parallel port signal ACK#.
5
PERROR
R
-
Version of parallel port signal PE.
4
SELECT
R
-
Version of parallel port signal SLCT.
3
ERR_N
R
-
Version of parallel port signal ERR#.
R
11
2-1 Reserved
Reserved. Return 11b when read.
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0
TMOUT
R
-
This bit is valid only in EPP mode. Return 1 when in other modes.
It indicates that a 10uS time out has occurred on the EPP bus.
0: no time out error.
1: time out error occurred, write 1 to clear.
Device Control Register  Base + 2
Bit
Name
7-6 Reserved
R/W Default
Description
-
11
Reserved. Return 11b when read.
5
DIR
R/W
0
0: the parallel port is in output mode.
1: the parallel port is in input mode.
It is auto reset to 0 when in SPP mode.
4
ACKIRQ_EN
R/W
0
Enable an interrupt at the rising edge of ACK#.
3
SLIN
R/W
0
Inverted and then drives the parallel port signal SLIN#.
When read, the status of inverted SLIN# is return.
2
INIT_N
R/W
0
Drives the parallel port signal INIT#.
When read, the status of INIT# is return.
1
AFD
R/W
0
Inverted and then drives the parallel port signal AFD#.
When read, the status of inverted AFD# is return.
0
STB
R/W
0
Inverted and then drives the parallel port signal STB#.
When read, the status of inverted STB# is return.
EPP Address Register  Base + 3
Bit
Name
7-0 EPP_ADDR
R/W Default
R/W
00h
Description
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Address Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Address Read protocol.
EPP Data Register  Base + 4 – Base + 7
Bit
Name
7-0 EPP_DATA
R/W Default
R/W
00h
Description
Write this register will cause the hardware to auto transmit the written data to
the device with the EPP Data Write protocol.
Read this register will cause the hardware to auto receive data from the device
by with the EPP Data Read protocol.
Parallel Port Data FIFO  Base + 400h
Bit
Name
7-0 C_FIFO
R/W Default
R/W
00h
Description
Data written to this FIFO is auto transmitted by the hardware to the device by
using standard parallel port protocol.
It is only valid in ECP and the ECP_MODE is 010b.The operation is only for
forward direction.
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ECP Data FIFO  Base + 400h
Bit
Name
7-0 ECP_DFIFO
R/W Default
R/W
00h
Description
Data written to this FIFO when DIR is 0 is auto transmitted by the hardware to
the device by using ECP parallel port protocol.
Data is auto read from device into the FIFO when DIR is 1 by the hardware by
using ECP parallel port protocol. Read the FIFO will return the content to the
system.
It is only valid in ECP and the ECP_MODE is 011b.
ECP Test FIFO  Base + 400h
Bit
Name
7-0 T_FIFO
R/W Default
R/W
00h
Description
Data may be read, written from system to the FIFO in any Direction. But no
hardware handshake occurred on the parallel port lines. It could be used to test
the empty, full and threshold of the FIFO.
It is only valid in ECP and the ECP_MODE is 110b.
ECP Configuration Register A  Base + 400h
Bit
7
Name
IRQ_MODE
6-4 IMPID
R/W Default
R
0
R
001
Description
0: interrupt is ISA pulse.
1: interrupt is ISA level.
Only valid in ECP and ECP_MODE is 111b.
000: the design is 16-bit implementation.
001: the design is 8-bit implementation (default).
010: the design is 32-bit implementation.
011-111: Reserved.
Only valid in ECP and ECP_MODE is 111b.
3
Reserved
-
-
Reserved.
2
BYTETRAN_N
R
1
0: when transmitting there is 1 byte waiting in the transceiver that does not
affect the FIFO full condition.
1: when transmitting the state of the full bit includes the byte being transmitted.
Only valid in ECP and ECP_MODE is 111b.
R
00
Return 00 when read.
Only valid in ECP and ECP_MODE is 111b.
1-0 Reserved
ECP Configuration Register B  Base + 401h
Bit
Name
R/W Default
Description
7
COMP
R
0
0: only send uncompressed data.
1: compress data before sending.
Only valid in ECP and ECP_MODE is 111b.
6
Reserved
R
1
Reserved. Return 1 when read.
Only valid in ECP and ECP_MODE is 111b.
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5-3 ECP_IRQ_CH
R
001
000: the interrupt selected with jumper.
001: select IRQ 7 (default).
010: select IRQ 9.
011: select IRQ 10.
100: select IRQ 11.
101: select IRQ 14.
110: select IRQ 15.
111: select IRQ 5.
Only valid in ECP and ECP_MODE is 111b.
2-0 ECP_DMA_CH
R
011
Return the DMA channel of ECP parallel port.
Only valid in ECP and ECP_MODE is 111b.
Extended Control Register  Base + 402h
Bit
Name
7-5 ECP_MODE
R/W Default
R/W
000
Description
000: SPP Mode.
001: PS/2 Parallel Port Mode.
010: Parallel Port Data FIFO Mode.
011: ECP Parallel Port Mode.
100: EPP Mode.
101: Reserved.
110: Test Mode.
111: Configuration Mode.
Only valid in ECP.
4
ERRINTR_EN
R/W
0
0: disable the interrupt generated on the falling edge of ERR#.
1: enable the interrupt generated on the falling edge of ERR#.
3
DAMEN
R/W
0
0: disable DMA.
1: enable DMA. DMA starts when SERVICEINTR is 0.
2
SERVICEINTR
R/W
1
0: enable the following case of interrupt.
DMAEN = 1: DMA mode.
DMAEN = 0, DIR = 0: set to 1 whenever there are writeIntrThreshold or more
bytes are free in the FIFO.
DMAEN = 0, DIR = 0: set to 1 whenever there are readIntrThreshold or more
bytes are valid to be read in the FIFO.
1
FIFOFULL
R
0
0: The FIFO has at least 1 free byte.
1: The FIFO is completely full.
0
FIFOEMPTY
R
0
0: The FIFO contains at least 1 byte.
1: The FIFO is completely empty.
7.5
Hardware Monitor
For the 8-bit ADC has the 8mv LSB, the maximum input voltage of the analog pin is
2.048V. Therefore the voltage under 2.048V (ex:1.5V) can be directly connected to these
analog inputs. The voltage higher than 2.048V should be reduced by a factor with external
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resistors so as to obtain the input range. Only 3Vcc is an exception for it is main power of the
F71883. Therefore 3Vcc can directly connect to this chip’s power pin and need no external
resistors. There are two functions in this pin with 3.3V. The first function is to supply internal
analog power of the F71883 and the second function is that voltage with 3.3V is connected to
internal serial resistors to monitor the +3.3V voltage. The internal serial resistors are two 150K
ohm, so that the internal reduced voltage is half of +3.3V.
There are four voltage inputs in the F71883 and the voltage divided formula is shown as
follows:
VIN = V+12V ×
R2
R1 + R2
where V+12V is the analog input voltage, for example.
If we choose R1=27K, R2=5.1K, the exact input voltage for V+12v will be 1.907V, which
is within the tolerance. As for application circuit, it can be refer to the figure shown as follows.
Voltage Inputs
150K
(directly connect to the chip)
3Vcc
VIN (Lower than 2.304V)
VIN3.3
(directly connect to the chip)
150K
VIN1(Max2.304V)
VIN(Higher than
R1
R2
8-bit ADC
with
8 mV LSB
VREF Pin 1
R
10K, 1%
Pin 3, 4 or 5
Typical BJT
Connection
D+
D-
2N3906
RTHM
10K, 25 C
Typical Thermister
Connection
Fig 7-1
SMI# interrupt for voltage is shown as figure. Voltage exceeding or going below high
limit will cause an interrupt if the previous interrupt has been reset by writing “1” all the
interrupt Status Register. Voltage exceeding or going below low limit will result the same
condition as voltage exceeding or going below high limit.
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*
(pulse mode)
(level mode)
*
*
*
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are written 1
Voltage SMI# Mode
Fig 7-2
The F71883 monitors three remote temperature sensors. One of these sensors can be
measured from -20°C to 127°C. The others can be measured from 0°C to 145°C (2 Sets) .More
detail please refer register description.
Remote-sensor transistor manufacturers
Manufacturer
Model Number
Panasonic
2SB0709 2N3906
Philips
PMBT3906
Monitor Temperature from “thermistor”
The F71883 can connect three thermistor to measure environment temperature or
remote temperature. The specification of thermistor should be considered to (1) β value is
3435K (2) resistor value is 10K ohm at 25°C. In the Figure 7-1, the thermistor is connected by
a serial resistor with 10K ohm, then connected to VREF.
Monitor Temperature from “thermal diode”
Also, if the CPU, GPU or external circuits provide thermal diode for temperature
measurement, the F71883 is capable to these situations. The build-in reference table is for
PNP 2N3906 transistor, and each different kind of thermal diode should be matched with
specific offset and BJT gain. In the Figure 7-1, the transistor is directly connected into
temperature pins.
ADC Noise Filtering
The ADC is integrating type with inherently good noise rejection. Micro-power operation
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places constraints on high-frequency noise rejection; therefore, careful PCB board layout and
suitable external filtering are required for high-accuracy remote measurement in electronically
noisy environment. High frequency EMI is best filtered at D+ and D- with an external 2200pF
capacitor. Too high capacitance may introduce errors due to the rise time of the switched
current source. Nearly all noise sources tested cause the ADC measurement to be higher
than the actual temperature, depending on the frequency and amplitude.
Over Temperature Signal (OVT#)
OVT# alert for temperature is shown as figure 7-3. When monitored temperature
exceeds the over-temperature threshold value, OVT# will be asserted until the temperature
goes below the hysteresis temperature.
To
T
HYST
OVT#
Fig 7-3
Temperature PME#
PME# interrupt for temperature is shown as figure 7-4. Temperature exceeding high limit
or going below hysteresis will cause an interrupt if the previous interrupt has been reset by
writing “1” all the interrupt Status Register.
To
T HYST
SMI#
(pulse mode)
(level mode
active low)
*
*
*
*
*Interrupt Reset when Interrupt Status Registers are written 1
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Fig 7-4
Fan speed count
Inputs are provided by the signals from fans equipped with tachometer outputs. The
level of these signals should be set to TTL level, and maximum input voltage cannot be over
5V. If the input signals from the tachometer outputs are over the 5V, the external trimming
circuit should be added to reduce the voltage to obtain the input specification. The normal
circuit and trimming circuits are shown as follows:
+12V
+12V
Pull-up resister
4.7K Ohms
Pull-up resister < 1K
or totem-pole output
+12V
22K~30K
FAN Out
Fan Input
+12V
FANIN 1
GND
10K
> 1K
Fan Input
FAN Out
FANIN 1
GND
F71883
3.3V Zener
FAN
Connector
F71883
Fan with Tach Pull-Up to +12V, or
Totem-Pole Putput and Zener Clamp
Fan with Tach Pull-Up to +12V, or Totern-Pole
Output and Register Attenuator
Fig 7-5 / 7-6
+5V
+5V
Pull-up resister
4.7K Ohms
Pull-up resister < 1K
or totem-pole output
+5V
FAN Out
1K~2.7K
Fan Input
+5V
FANIN1
GND
10K
> 1K
FAN Out
Fan Input
FANIN1
GND
F71883
3.3V Zener
FAN
Connector
F71883
Fan with Tach Pull-Up to +5V, or
Totem-Pole Putput and Zener Clamp
Fan with Tach Pull-Up to +5V, or Totern-Pole
Output and Register Attenuator
Fig 7-7 / 7-8
Determine the fan counter according to:
Count =
1.5 × 10 6
RPM
In other words, the fan speed counter has been read from register, the fan speed can be
evaluated by the following equation. As for fan, it would be best to use 2 pulses tachometer
output per round.
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RPM =
1.5 × 10 6
Count
Fan speed control
The F71883 provides 2 fan speed control methods:
1. LINEAR FAN CONTROL 2. PWM DUTY CYCLE
Linear Fan Control
The range of DC output is 0~3.3V, controlled by 8-bit register. 1 LSB is about 0.013V.
The output DC voltage is amplified by external OP circuit, thus to reach maximum FAN
OPERATION VOLTAGE, 12V. The output voltage will be given as followed:
Output_voltage (V) = 3.3 ×
Programmed 8bit Register Value
255
And the suggested application circuit for linear fan control would be:
8
12V
3
2
-
PMOS
1
D1
1N4148
LM358
4
DC OUTPUT VOLTAGE
+
R
4.7K
JP1
R 10K
3
2
1
C
47u
CON3
R
3.9K
R 27K FANIN MONITOR
C
0.1u
R
10K
DC FAN Control with OP
Fig 7-9
PWM duty Fan Control
The duty cycle of PWM can be programmed by a 8-bit register. The default duty cycle is
set to 100%, that is, the default 8-bit registers is set to FFh. The expression of duty can be
represented as follows.
Duty_cycle(%) =
Programmed 8bit Register Value
× 100%
255
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+5V
+12V
R1
R1
R2
R2
PNP Transistor
D
G
G
NMOS
PWM Clock Input
PNP Transistor
D
S
PWM Clock Input
NMOS
+
S
+
C
C
FAN
FAN
-
-
Fig 7-10
Fan speed control mechanism
There are some modes to control fan speed and they are 1.Manual mode, 2.Stage auto
mode, 3. Linear auto mode. More detail, please refer the description of registers.
Manual mode
For manual mode, it generally acts as software fan speed control.
Stage auto mode
At this mode, the F71883 provides automatic fan speed control related to temperature
variation of CPU/GPU or the system. The F71883 can provide four temperature boundaries
and five intervals, and each interval has its related fan speed count. All these values should
be set by BIOS first. Take figure 7-11 as example. When temperature boundaries are set as
45, 55, 65, and 75°C and there are five intervals (each interval is 10(C). The related desired
fan speed counts for each interval are 0500h, 0400h, 0300h, 0200h and 0100h. When the
temperature is within 55~65(C, the fan speed count 300h will be load into FAN EXPECT
COUNT that define in registers. Then, the F71883 will adjust PWMOUT duty-cycle to meet the
expected value. It can be said that the fan will be turned on with a specific speed set by BIOS
and automatically controlled with the temperature variation. The F71883 will take charge of all
the fan speed control and need no software support.
Desired Counts
0100h
75 Degree C
0200h
65 Degree C
0300h
55 Degree C
0400h
45 Degree C
0500h
Figure 7-11
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There are some examples as below:
A. Stage auto mode (PWM Duty)
Set temperature as 60°C, 50°C, 40°C, 30°C and Duty as 100%, 90%, 80%, 70%, 60%
PWM duty
60 Degree C
50 Degree C
hysteresis 47 Degree C
100%
0xFF
90%
0xE5
80%
0xCC
70%
0xB2
60%
0x99
40 Degree C
30 Degree C
Temp.
Fan Speed
a
b
c
d
a. Once temp. is under 30°C, the lowest fan speed keeps 60% PWM duty
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 60% to 90% PWM duty
and increase with temp. level.
c.
Once temp. keeps in 55°C, fan speed keeps in 90% PWM duty
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed
reduces to 80% PWM duty and stays there.
B. Stage auto mode (RPM%)
Set temperature as 60°C, 50°C, 40°C, 30°C and assume the Full Speed is 6000rpm, set
90% of full speed RPM(5400rpm), 80%(4800rpm), 70%(4200rpm), 60%(3600rpm) of full
speed RPM
6000RPM
60 Degree C
90%(5400RPM)
50 Degree C
hysteresis 47 Degree C
80%(4800RPM)
40 Degree C
70%(4200RPM)
30 Degree C
60%(3600RPM)
Temp.
Fan Speed
a
b
c
d
a. Once temp. is under 30°C, the lowest fan speed keeps 60% of full speed (3600RPM).
b. Once temp. is over 30°C,40°C,50°C, the fan speed will vary from 3600RPM to 5400RPM
and increase with temp. level.
c. Once temp. keeps in 55°C, fan speed keeps in 90% of full speed (5400RPM)
d. If set the hysteresis as 3°C (default 4°C), once temp reduces under 47°C, fan speed
reduces to 4800RPM and stays there.
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Linear auto mode
Otherwise, F71883 supports linear auto mode. Below has two examples to describe this
mode. More detail, please refer the register description.
A. Linear auto mode (PWM Duty I)
Set temperature as 70°C, 60°C, 50°C, 40°C and Duty as 100%, 70%, 60%, 50%, 40%
PWM duty
100%
70 Degree C
hysteresis 65 Degree C
70%
60 Degree C
60%
50 Degree C
50%
40 Degree C
Temp.
Fan Speed
40%
a
b
c
d
a. Once temp. is under 40°C, the lowest fan speed keeps 40% PWM duty
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% PWM duty
and linearly increase with temp. variation.
The temp.-fan speed monitoring and flash
interval is 1sec.
c. Once temp. goes over 70°C, fan speed will directly increase to 100% PWM duty (full
speed)
d. If set the hysteresis as 5°C(default is 4°C), once temp reduces under 65°C (not 70°C),
fan speed reduces from 100% PWM duty and decrease linearly with temp..
B. Linear auto mode (RPM%)
Set temperature as 70°C, 60°C, 50°C, 40°C and if full speed is 6000RPM, setting 100%,
70%, 60%, 50%, 40% of full speed.
6000RPM
70 Degree C
hysteresis 65 Degree C
70%(4200RPM)
60 Degree C
60%(3600RPM)
50 Degree C
50%(3000RPM)
40 Degree C
40%(2400RPM)
Temp.
Fan Speed
a
b
c
d
a. Once temp. is under 40°C, the lowest fan speed keeps 40% of full speed (2400RPM)
b. Once temp. is over 40°C,50°C,60°C, the fan speed will vary from 40% to 70% of full
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speed and almost linearly increase with temp. variation.
The temp.-fan speed
monitoring and flash interval is 1sec.
c. Once temp. goes over 70°C, fan speed will directly increase to full speed 6000RPM.
If set the hysteresis as 5°C, once temp reduces under 65°C (not 70°C), fan speed reduces from
full speed and decrease linearly with temp..
PWMOUT Duty-cycle operating process
In both “Manual RPM” and “Temperature RPM” modes, the F71883 adjust PWMOUT
duty-cycle according to current fan count and expected fan count. It will operate as follows:
(1). When expected count is 0xFFF, PWMOUT duty-cycle will be set to 0x00 to turn off
fan.
(2). When expected count is 0x000, PWMOUT duty-cycle will be set to 0xFF to turn on
fan with full speed.
(3). If both (1) and (2) are not true,
(4). When PWMOUT duty-cycle decrease to MIN_DUTY(≠ 00h), obviously the
duty-cycle will decrease to 00h next, the F71883 will keep duty-cycle at 00h for 1.6
seconds. After that, the F71883 starts to compare current fan count and expected
count in order to increase or decrease its duty-cycle. This ensures that if there is
any glitch during the period, the F71883 will ignore it.
Start Duty
Stop Duty
Fig 7-12
FAN_FAULT#
Fan_Fault# will be asserted when the fan speed doesn’t meet the expected fan speed
within a programmable period (default is 11 seconds) or when fan stops with respect to PWM
duty-cycle which should be able to turn on the fan. There are two conditions may cause the
FAN_FAULT# event.
(1). When PWM_Duty reaches 0xFF, the fan speed count can’t reach the fan expected
count in time. (Figure 7-13)
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11 sec(default)
Current Fan Count
Expected Fan Count
100%
Duty-cycle
Fan_Fault#
Fig 7-13
(2). After the period of detecting fan full speed, when PWM_Duty > Min. Duty, and fan
count still in 0xFFF.
7.6
Keyboard Controller
The KBC provides the functions included a keyboard and a PS/2 mouse, and can be
used with IBM(-compatible personal computers or PS/2-based systems. The controller
receives serial data from the keyboard or PS/2 mouse, checks the parity of the data, and
presents the data to the system as a byte of data in its output buffer. The controller will assert
an interrupt to the system when data are placed in its output buffer.
The below content is about the KBC device register descriptions. All the registers are for
software porting reference.
Status Register
The status register is an 8 bits register at I/O address 64h that provides information about the status of the KBC
Bit
Name
R/W Default
Description
7
Parity error
R
0
0:odd parity
1:even parity
6
Time out
R
0
0:no time out error
1:time out error
5
Auxiliary device
OBF
R
0
0: Auxiliary output buffer empty
1: Auxiliary output buffer full
4
Inhinit
R
0
0:keyboard is inhibited
1: keyboard is not inhibited
3
Command/data
R
0
0:data byte
1:command byte
2
SYSTEM_FLAG
R
0
This bit is set or clear by command byte of KBC
1
IBF
R
0
0:input buffer empty
1: input buffer full
0
OBF
R
0
0:output buffer empty
1: output buffer full
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Command register
The internal KBC operation is controlled by the KBC command byte (KCCB). The KCCB resides in I/O address
64h that is read with a 20h command and written with a 60h command data.
Bit
Name
7
Reserved
6
R/W Default
Description
-
-
Reserved
Translate code
R/W
1
0: Pass un-translated scan code.
1: Translate scan code to IBM PC standard.
5
Disable Auxiliary
Device
R/W
0
1: Disable Auxiliary inhibit function.
4
Disable Keyboard
R/W
0
1: Disable keyboard inhibit function.
3
Reserved
-
-
Reserved
2
System flag
R/W
1
0: The system is executing POST as a result of a cold boot.
1: The system is executing POST as a result of a shutdown or warm boot.
1
Enable Auxiliary
Interrupt
R/W
1
0: Ao interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ12).
0
Enable keyboard
Interrupt
R/W
1
0:No interrupt
1: A system interrupt is generated when a byte is placed in output buffer
(IRQ1).
DATA register
The DATA register is an 8 bits register at I/O address 60h. the KBC used the output buffer to send the scan code
received from keyboard and data byte replay by command to the system.
Power on default <7:0> = 00000000 binary
7.7
SPI Interface
Communication between the two devices is handling the serial peripheral interface (SPI).
Every SPI system consist of one master and one or more slaves, where a master provides the
SPI clock and slave receives clock from the master.
This design is only master function, for basic signal, master-out/slave-in (MOSI),
master-in/slave-out (MISO), serial clock (SCK), and 4 slaves select (SS), are needed for SPI
interface. Each of slave select supports from 512kbits to 4096kbits flash is decided by
configuration register. Serial clock (SCK) signal frequency is varied from 24MHz to 187.5 KHz.
The serial data (MOSI) for SPI interface translates to depend on SCK rising edge or falling
edge is decided by configuration register.
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7.8
80 Port
Monitor the value of 0x80 port and output the value via the signals defined for 7-segment
display. High nibble and low nibble are outputted interleaved at 1KHz frequency.
7.9
ACPI Function
The Advanced Configuration and Power Interface (ACPI) is a system for controlling the use
of power in a computer. It lets computer manufacturer and user to determine the computer’s
power usage dynamically.
There are three ACPI states that are of primary concern to the system designer and they are
designated S0, S3 and S5. S0 is a full-power state; the computer is being actively used in this
state. The other two are called sleep states and reflect different power consumption when
power-down. S3 is a state that the processor is powered down but the last procedural state is
being stored in memory which is still active. S5 is a state that memory is off and the last
procedural state of the processor has been stored to the hard disk. Take S3 and S5 as
comparison, since memory is fast, the computer can quickly come back to full-power state, the
disk is slower than the memory and the computer takes longer time to come back to full-power
state. However, since the memory is off, S5 draws the minimal power comparing to S0 and S3.
It is anticipated that only the following state transitions may happen:
S0→S3, S0→S5, S5→S0, S3→S0 and S3→S5.
Among them, S3→S5 is illegal transition and won’t be allowed by state machine. It is necessary
to enter S0 first in order to get to S5 from S3. As for transition S5→S3 will occur only as an
immediate state during state transition from S5→S0. It isn’t allowed in the normal state transition.
The below diagram described the timing, the always on and always off, keep last state could
be set in control register. In keep last state mode, one register will keep the status of before
power loss. If it is power on before power loss, it will remain power on when power is resumed,
otherwise, if it is power off before power loss, it will remain power off when power is resumed.
-47-
May, 2008
V0.27P
F71883
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
DEFAULT TIMING
Always off
VBAT
VSB
RSMRST#
S3#
PS_ON#
PSIN#
PSOUT#
VCC3V
ALways ON TIMING
PCI Reset and PWROK Signals
The F71883 supports 3 output buffers for 3 reset signals. If the register RSTCON_EN is set to
1, the pin RSTCON# will infect PCIRST1# ~ PCIRST3# outcome. Then, the result of PCIRST#
outcome will be affected by conditions as below:
PCIRST1# Æ Output buffer of RSTCON# and LRESET#.
PCIRST2# Æ Output buffer of RSTCON# and LRESET#.
PCIRST3# Æ Output buffer of RSTCON# and LRESET#.
-48-
May, 2008
V0.27P
F71883
+3.3V
Delay
RSTCON#
PWROK
ATXPG
PCIRST1~3#
LRESET#
RSTCON#
So far as the PWROK issue is as the figure above. PWROK is delayed 400ms (default) as
VCC arrives 2.8V, and the delay timing can be programmed by register. (100ms ~ 400ms)
In the figure, the RSTCON# will be implemented by register RSTCON_EN. If RSTCON_EN be
set to 0, the RSTCON# pin will affect PWROK output(Default). If RSTCON_EN be set to 1, the
RSTCON# pin will affect PCIRST outputs.
VCC3
CPU
5
7
6 4.7K
8 4.7K
VCORE
PWOK
NORTH BRIDGE
VSI
PCIRST3#
IDE
VSO
to PWM VCORE SENSE
ATA 133
SATA*2
PCIRST2#
1
1
VSB3
R86
4.7K
PCIRST#
2
RSTCON#
LRESET#
SUSB#
R88
4.7K R90
1
PWSIN#
S3#
F71882
F71883
PWSOUT#
5
2
7
RSTGND
PSW+
RESET
PSW-
6
-PWR_BTN
1
2
8
1 2
2
1
R89
1K
R91
33
C42
0.1UF
ATXPG_IN
Front Panel
PS_ON#
RSMRST#
PCI
VSB3
FRONT PANEL
VCC3
2
SOUTH BRIDGE
PCIRST1#
VSB3
2 4.7K
4 4.7K
2
VCC3
VCC5
ATX1
3V3
3V3
-12V
3V3
GND
GND
PS-ON
5V
GND
GND
GND
5V
GND
GND
-5V
PW-OK
5V
5VSB
5V
12V
1
2
3
4
5
6
7
8
9
10
VCC3
VSB5
VCC5
1
11
12
13
14
15
16
17
18
19
20
R87
4.7K
2
-12V
+12V
VSB5
1
R85
4.7K
ATX CONNECTOR
ATX CONNECTOR
2
1
VSB5
2
PCLK_1,2,3(33MHz)
1
3
1 1K
TC1
22uF
Title
Size
A
Date:
Feature Integration Technology Inc.
Document Number
ACPI & VSI/VSO
Monday , July 11, 2005
Rev
0.1
Sheet
5
of
6
ACPI Reference Circuit
-49-
May, 2008
V0.27P
F71883
7.10 AMDSI and Intel SST PECI Function
The F71883 provides Intel SST/PECI/AMDSI interfaces for new generational CPU temperature
sensing. In AMDSI interface, there are SIC and SID signals for temperature information reading from
AMD CPU. The SIC signal is for clocking use, the other is for data transferring. More detail please
refer register description.
VDDIO
300
AMD CPU
300
SIC
SIC
SID
F71883
SID
In Intel SST and PECI interfaces, the F71883 can connect to CPU/SST directly. The F71883 can
read the temperature data from CPU, than the fan control machine of F71883 can implement the Fan
to cool down CPU temperature. As same as PECI, chipset can get information from F71883
including CPU temperature, system temperature (F71883 provides D+/D- for system temperature
sensing), fan speed status by SST. The application circuit is as below. More detail please refer the
register description.
Intel
ICH8
F71883
SST
SST
100K
avoid pre-BIOS floating
Intel
F71883
CPU
avoid pre-BIOS floating
PECI
PECI
100K
-50-
May, 2008
V0.27P
F71883
8. Register Description
The configuration register is used to control the behavior of the corresponding devices. To
configure the register, using the index port to select the index and then writing data port to alter the
parameters. The default index port and data port are 0x4E and 0x4F respectively. Pull down the
SOUT1 pin to change the default value to 0x2E/0x2F. To enable configuration, the entry key 0x87
must be written to the index port. To disable configuration, write exit key 0xAA to the index port.
Following is a example to enable configuration and disable configuration by using debug.
-o 4e 87
-o 4e 87
( enable configuration )
-o 4e aa
( disable configuration )
The Following is a register map (total devices) grouped in hexadecimal address order, which
shows a summary of all registers and their default value. Please refer each device chapter if you
want more detail information.
Global Control Registers
“-“ Reserved or Tri-State
Global Control Registers
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
02
Software Reset Register
-
-
-
-
-
-
-
0
07
Logic Device Number Register (LDN)
0
0
0
0
0
0
0
0
20
Chip ID Register
0
0
0
0
0
1
0
1
21
Chip ID Register
0
1
0
0
0
0
0
1
23
Vender ID Register
0
0
0
1
1
0
0
1
24
Vender ID Register
0
0
1
1
0
1
0
0
25
Software Power Down Register
-
-
0
0
0
0
0
0
26
UART IRQ Sharing Register
0
-
-
-
-
-
0
0
27
ROM Address Select Register
0
0/1
1/0
1/0
0/1
0/1
0/1
0
28
Power LED Function Select Register
-
1/0
0/1
0
0
0
0
0
29
Muti Function Select 1 Register
0
0
0
0
0
0
0
0
2A
Multi Function Select 2 Register
0
0
0
0
0
0
0
0
2B
Multi Function Select 3 Register
0
0
0
0
0
0
0
0
2C
Multi Function Select 4 Register
0
0
0
0
0
0
0
0
-51-
May, 2008
V0.27P
F71883
2D
Wakeup Control Register
0
-
-
-
1
0
0
0
Device Configuration Registers
“-“ Reserved or Tri-State
FDC Device Configuration Registers (LDN CR00)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
FDC Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
1
1
1
1
0
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
1
1
0
74
DMA Channel Select Register
-
-
-
-
-
0
1
0
F0
FDD Mode Register
-
-
-
-
1
1
1
0
F2
FDD Drive Type Register
-
-
-
-
-
-
1
1
F4
FDD Selection Register
-
-
-
0
0
-
0
0
UART1 Device Configuration Registers (LDN CR01)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
UART1 Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
1
1
1
1
1
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
1
0
0
F0
RS485 Enable Register
-
-
-
0
-
-
-
-
UART2 Device Configuration Registers (LDN CR02)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
UART2 Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
0
61
Base Address Low Register
1
1
1
1
1
0
0
0
70
IRQ Channel Select Register
-
-
-
-
0
0
1
1
F0
RS485 Enable Register
-
-
-
0
0
0
-
-
F1
SIR Mode Control Register
-
-
-
0
0
1
0
0
Parallel Port Device Configuration Registers (LDN CR03)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
Parallel Port Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
1
61
Base Address Low Register
0
1
1
1
1
0
0
0
-52-
May, 2008
V0.27P
F71883
70
IRQ Channel Select Register
-
-
-
-
0
1
1
1
74
DMA Channel Select Register
-
-
-
0
-
0
1
1
F0
PRT Mode Select Register
0
1
0
0
0
0
1
0
Hardware Monitor Device Configuration Registers (LDN CR04)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
H/W Monitor Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
1
0
61
Base Address Low Register
1
0
0
1
0
1
0
1
70
IRQ Channel Select Register
-
-
-
-
0
0
0
0
KBC Device Configuration Registers (LDN CR05)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
KBC Device Enable Register
-
-
-
-
-
-
-
1
60
Base Address High Register
0
0
0
0
0
0
0
0
61
Base Address Low Register
0
1
1
0
0
0
0
0
70
KB IRQ Channel Select Register
-
-
-
-
0
0
0
0
72
Mouse IRQ Channel Select Register
-
-
-
-
0
0
0
0
F0
Clock Select Register
1
0
-
-
-
-
1
1
GPIO Device Configuration Registers (LDN CR06)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
F0
GPIO Output Enable Register
0
0
0
0
0
0
0
0
F1
GPIO Output Data Register
1
1
1
1
1
1
1
1
F2
GPIO Pin Status Register
-
-
-
-
-
-
-
-
F3
GPIO Drive Enable Register
0
0
0
0
0
0
0
0
E0
GPIO1 Output Enable Register
0
0
0
0
0
0
0
0
E1
GPIO1 Output Data Register
1
1
1
1
1
1
1
1
E2
GPIO1 Pin Status Register
-
-
-
-
-
-
-
-
E3
GPIO1 Drive Enable Register
0
0
0
0
0
0
0
0
D0
GPIO2 Output Enable Register
0
0
0
0
0
0
0
0
D1
GPIO2 Output Data Register
1
1
1
1
1
1
1
1
D2
GPIO2 Pin Status Register
-
-
-
-
-
-
-
-
D3
GPIO2 Drive Enable Register
0
0
0
0
0
0
0
0
C0
GPIO3 Output Enable Register
-
-
-
-
0
0
0
0
C1
GPIO3 Output Data Register
-
-
-
-
1
1
1
1
C2
GPIO3 Pin Status Register
-
-
-
-
-
-
-
-
C3
GPIO3 Drive Enable Register
-
-
-
-
0
0
0
0
-53-
May, 2008
V0.27P
F71883
B0
GPIO4 Output Enable Register
-
-
-
-
0
0
0
0
B1
GPIO4 Output Data Register
-
-
-
-
1
1
1
1
B2
GPIO4 Pin Status Register
-
-
-
-
-
-
-
-
B3
GPIO4 Drive Enable Register
-
-
-
-
0
0
0
0
VID Device Configuration Registers (LDN CR07)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
VID Device Enable Register
-
-
-
-
-
-
-
0
60
Base Address High Register
0
0
0
0
0
0
0
0
61
Base Address Low Register
0
0
0
0
0
0
0
0
SPI Device Configuration Registers (LDN CR08)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
F0
SPI Control Register
0
0
0
1
0
0
0
0
F1
SPI Timeout Value Register
0
0
0
0
0
1
0
0
F2
SPI Baud Rate Divisor Register
-
-
-
-
-
0
0
1
F3
SPI Status Register
0
-
-
-
0
-
-
-
F4
SPI High Byte Data Register
0
0
0
0
0
0
0
0
F5
SPI Command Data Register
0
0
0
0
0
0
0
0
F6
SPI Chip Select Register
-
-
-
-
0
0
0
0
F7
SPI Memory Mapping Register
-
-
-
-
-
-
-
-
F8
SPI Operate Register
0
0
0
0
0
0
0
0
FA
SPI Low Byte Data Register
0
0
0
0
0
0
0
0
FB
SPI Address High Byte Register
0
0
0
0
0
0
0
0
FC
SPI Address Medium Byte Register
0
0
0
0
0
0
0
0
FD
SPI Address Low Byte Register
0
0
0
0
0
0
0
0
FE
SPI Program Byte Register
0
0
0
0
0
0
0
0
FF
SPI Write Data Register
0
0
0
0
0
0
0
0
PME and ACPI Device Configuration Registers (LDN CR0A)
Register
0x[HEX]
Register Name
Default Value
MSB
LSB
30
PME Device Enable Register
-
-
-
-
-
-
-
0
F0
PME Event Enable Register
-
0
0
0
0
0
0
0
F1
PME Event Status Register
-
0
0
0
0
0
0
1
F4
ACPI Control Register
-
0
0
0
0
1
1
0
F5
ACPI Control Register
0
-
0
1
1
1
-
-
-54-
May, 2008
V0.27P
F71883
8.1
Global Control Registers
8.1.1
Software Reset Register  Index 02h
Bit
Name
7-1 Reserved
0
8.1.2
SOFT_RST
R/W Default
Description
-
-
Reserved
R/W
0
Write 1 to reset the register and device powered by VDD ( VCC ).
Logic Device Number Register (LDN)  Index 07h
Bit
Name
7-0 LDN
R/W Default
R/W
00h
Description
00h: Select FDC device configuration registers.
01h: Select UART 1 device configuration registers.
02h: Select UART 2 device configuration registers.
03h: Select Parallel Port device configuration registers.
04h: Select Hardware Monitor device configuration registers.
05h: Select KBC device configuration registers.
06h: Select GPIO device configuration registers.
07h: Select VID device configuration registers.
08h: Select SPI device configuration registers.
0ah: Select PME & ACPI device configuration registers.
8.1.3
Bit
Chip ID Register  Index 20h
Name
7-0 CHIP_ID1
8.1.4
Bit
Bit
Name
Bit
05h
Chip ID 1 of F71883.
R/W Default
R
41h
Description
Chip ID2 of F71883.
Vendor ID Register  Index 23h
Name
7-0 VENDOR_ID1
8.1.6
R
Description
Chip ID Register  Index 21h
7-0 CHIP_ID2
8.1.5
R/W Default
R/W Default
R
19h
Description
Vendor ID 1 of Fintek devices.
Vendor ID Register  Index 24h
Name
R/W Default
Description
-55-
May, 2008
V0.27P
F71883
7-0 VENDOR_ID2
8.1.7
Bit
R
34h
Vendor ID 2 of Fintek devices.
Software Power Down Register  Index 25h
Name
7-6 Reserved
R/W Default
Description
-
-
Reserved
5
SOFTPD_KBC
R/W
0
Power down the KBC device. This will stop the KBC clock.
4
SOFTPD_HM
R/W
0
Power down the Hardware Monitor device. This will stop the Hardware Monitor
clock.
3
SOFTPD_PRT
R/W
0
Power down the Parallel Port device. This will stop the Parallel Port clock.
2
SOFTPD_UR2
R/W
0
Power down the UART 2 device. This will stop the UART 2 clock.
1
SOFTPD_UR1
R/W
0
Power down the UART 1 device. This will stop the UART 1 clock.
0
SOFTPD_FDC
R/W
0
Power down the FDC device. This will stop the FDC clock.
8.1.8
Bit
7
UART IRQ Sharing Register  Index 26h
Name
CLK24M_SEL
R/W Default
R/W
0
Description
0: CLKIN is 48MHz
1: CLKIN is 24MHz
6-2 Reserved
1
IRQ_MODE
-
-
Reserved.
R/W
0
0: PCI IRQ sharing mode (low level).
1: ISA IRQ sharing mode (low pulse).
o
IRQ_SHAR
R/W
0
0: disable IRQ sharing of two UART devices.
1: enable IRQ sharing of two UART devices.
8.1.9
Bit
7
ROM Address Select Register  Index 27h
Name
ROM_WR_EN
R/W Default
R/W
0
Description
0: disable ROM writing
1: enable ROM writing
6
SPI_EN
R/W
-
0: SPI disable
1: SPI enable
This register is power on trapped by SOUT2/SPI_TRAP. Pull down to enable
SPI.
-56-
May, 2008
V0.27P
F71883
5
BACKUP_BIOS_EN
R/W
-
0: use SPI as primary BIOS
1: use SPI as backup BIOS
This register is power on trapped by DTR2#/FWH_TRAP. Pull down to select
SPI as primary BIOS.
4
PORT_4E_EN
R/W
-
0: The configuration register port is 2E/2F.
1: The configuration register port is 4E/4F.
This register is power on trapped by SOUT1/ Config4E_2E. Pull down to select
port 2E/2F.
3
SEG_000E_EN
R/W
-
0: disable address 0x000E0000 – 0x000EFFFF decode
1: enable address 0x000E0000 – 0x000EFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
2
SEG_FFF8_EN
R/W
-
0: disable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
1: enable address 0xFFF80000 – 0xFFFFFFFF and 0x000F0000 –
0x000FFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
1
SEG_FFEF_EN
R/W
-
0: disable address 0xFFEE – 0xFFEFFFFF decode
1: enable address 0xFFEE0000 – 0xFFEFFFFF decode
This register is power on trapped by SOUT2/SPI_DIS. Pull down to enable.
0
SEG_FFF0_EN
R/W
0
0: disable address 0xFFF00000 – 0xFFF7FFFF decode
1: enable address 0xFFF00000 – 0xFFF7FFFF decode
8.1.10
Bit
Power LED Function Select Register  Index 28h
Name
7
Reserved
6
VIDOUT_EN
R/W Default
Description
-
-
Reserved.
R/W
-
0:
The
VID_OUT[5:0]/GPIO0[5:0]
functions
as
GPIO0[5:0],
and
the
SLOTOTCC#/GPIO06 functions as GPIO06.
1: The VID_OUT[5:0]/GPIO0[5:0] functions as VID_OUT[5:0], and the
SLOTOTCC#/GPIO06 functions as SLOTOCC#.
This register is power on trapped by RTS1#/VIDOUT_TRAP. Pull down to
select GPIOs function.
-57-
May, 2008
V0.27P
F71883
5
DPORT_EN
R/W
-
0: The 80 port function is disabled.
1: The 80 port function is enabled.
4
Reserved
R/W
-
Reserved.
3
GPIO43_SEL
R/W
0
0: IRRX/GPIO43 functions as IRRX.
1: IRRX/GPIO43 functions as GPIO43.
2
GPIO42_SEL
R/W
0
0: IRTX/GPIO42 functions as IRTX.
1: IRTX/GPIO42 functions as GPIO42.
1
GPIO41_SEL
R/W
0
0: FANCTRL3/GPIO41 functions as FANCTRL3.
1: FANCTRL3/GPIO41 functions as GPIO41.
0
GPIO40_SEL
R/W
0
0: FANIN3/GPIO40 functions as FANIN3.
1: FANIN3/GPIO40 functions as GPIO40.
8.1.11
Bit
Multi Function Select 1 Register  Index 29h (Powered by VSB3V)
Name
7-2 Reserved
1
WDT_GP07_EN
R/W Default
Description
R/W
0
Reserved
R/W
0
0: GPIO07/Turbo1#/WDTRST# will function as GPIO07/Turbo1#.
1: GPIO07/Turbo1#/WDTRST# will function as WDTRST#.
0
ALERT_GP_EN
R/W
0
0: GPIO15/LED_VSB/ALERT# will function as GPIO15/LED_VSB controlled
by GPIO15_SEL register.
1: GPIO15/LED_VSB/ALERT# will function as ALERT#.
8.1.12
Bit
Multi Function Select 2 Register  Index 2Ah (Powered by VSB3V)
Name
7-6 VSBLED_SEL
R/W Default
R/W
Description
2’b00 VSBLED function select, powered by VSB.
00: VSBLED always output low.
01: VSBLED tri-state
10: VSBLED output 0.5Hz clock.
11: VSBLED output 1Hz clock.
( clock output is inverse with VDDLED clock output )
-58-
May, 2008
V0.27P
F71883
5-4 VDDLED_SEL
R/W
2’b00 VDDLED function select, powered by VDD.
00: VDDLED always output low.
01: VDDLED tri-state
10: VDDLED output 0.5Hz clock.
11: VDDLED output 1Hz clock.
( clock output is inverse with VSBLED clock output )
3
GPIO33_SEL
R/W
0
0: RSMRST#/GPIO33 functions as RSMRST#.
1: RSMRST#/GPIO33 functions as GPIO33.
2
GPIO32_SEL
R/W
0
0: PWROK/GPIO32 functions as PWROK.
1: PWROK/GPIO32 functions as GPIO32.
1
GPIO31_SEL
R/W
0
0: PS_ON#/GPIO31 functions as PS_ON#.
1: PS_ON#/GPIO31 functions as GPIO31.
0
GPIO30_SEL
R/W
0
0: S3#/GPIO30 functions as S3#.
1: S3#/GPIO30 functions as GPIO30.
8.1.13
Bit
Multi Function Select 3 Register  Index 2Bh (Powered by VSB3V)
Name
R/W Default
Description
7
Reserved
R/W
0
Dummy register.
6
GPIO16_SEL
R/W
0
0: GPIO16/LED_VCC functions as GPIO16.
1: GPIO16/LED_VCC functions as LED_VCC.
5
GPIO15_SEL
R/W
0
When register ALERT_GP_EN is 0, the register functions as:
0: GPIO15/LED_VSB/ALERT# functions as GPIO15.
1: GPIO15/LED_VSB/ALERT# functions as LED_VSB.
4
GPIO14_SEL
R/W
0
0: GPIO14/FWH_DIS/WDTRST# functions as GPIO14 when SPI is disabled.
1: GPIO14/FWH_DIS/WDTRST# functions as WDTRST# when SPI is
disabled.
3
GPIO13_SEL
R/W
0
0: GPIO13/SPI_MOSI/BEEP functions as GPIO13 when SPI is disabled.
1: GPIO13/SPI_MOSI/BEEP functions as BEEP when SPI is disabled.
2
GPIO12_SEL
R/W
0
0: GPIO12/SPI_MISO/FANCTRL1_1 functions as GPIO12 when SPI is
disabled.
1: GPIO12/SPI_NISO/FANCTRL1_1 functions as FANCTRL1_1 when SPI is
disabled.
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1
GPIO11_SEL
R/W
0
0: GPIO11/SPI_CS/FANCTRL4 functions as GPIO11 when SPI is disabled.
1: GPIO11/SPI_CS/FANCTRL4 functions as FANCTRL4 when SPI is disabled.
0
GPIO10_SEL
R/W
0
0: GPIO10/SPI_CLK/FANIN4 functions as GPIO10 when SPI is disabled.
1: GPIO10/SPI_CLK/FANIN4 functions as FANIN4 when SPI is disabled.
8.1.14
Bit
7
Multi Function Select 4 Register  Index 2Ch (Powered by VSB3V)
Name
GPIO27_SEL
R/W Default
R/W
0
Description
0: PWSOUT#/GPIO27 functions as PWSOUT#.
1: PWSOUT#/GPIO27 functions as GPIO27.
6
GPIO26_SEL
R/W
0
0: PWSIN#/GPIO26 functions as PWSIN#.
1: PWSIN#/GPIO26 functions as GPIO26.
5
GPIO25_SEL
R/W
0
0: PME#/GPIO25 functions as PME#.
1: PME#/GPIO25 functions as GPIO25.
4
GPIO24_SEL
R/W
0
0: ATXPG_IN/GPIO24 functions as ATXPG_IN.
1: ATXPG_IN/GPIO24 functions as GPIO24.
3
GPIO23_SEL
R/W
0
0: RSTCON#/GPIO23 functions as RSTCON#.
1: RSTCON#/GPIO23 functions as GPIO23.
2
GPIO22_SEL
R/W
0
0: PCIRST3#/GPIO22 functions as PCIRST3#.
1: PCIRST3#/GPIO22 functions as GPIO22.
1
GPIO21_SEL
R/W
0
0: PCIRST2#/GPIO21 functions as PCIRST2#.
1: PCIRST2#/GPIO21 functions as GPIO21.
0
GPIO20_SEL
R/W
0
0: PCIRST1#/GPIO20 functions as PCIRST1#.
1: PCIRST1#/GPIO20 functions as GPIO20.
8.1.15
Bit
7
Wakeup Control Register  Index 2Dh (Powered by VBAT)
Name
SPI_CS1_EN
R/W Default
R/W
0
Description
This register decides the architecture of SPI when used as primary BIOS.
1: use two 4Mbits. (FWH_DIS will multi-functions as SPI_CS1#)
0: use one 8Mbits. (Divided into two 4Mbits. Originally use the higher part. If
the higher part is booting fail, the memory address will be auto mapped to
lower part.)
6-4 Reserved
-
-
Reserved.
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3
WAKEUP_EN
R/W
1
0: disable keyboard/mouse wake up.
1: enable keyboard/mouse wake up.
2-1 KEY_SEL
R/W
00
This registers select the keyboard wake up key.
00: Wake up key is Ctrl + Esc.
01: Wake up key is Ctrl + F1.
10: Wake up key is Ctrl + Space.
11: Wake up key is any key.
0
MO_SEL
R/W
0
This register select the mouse wake up key.
0: Wake up by click.
1: Wake up by click and movement.
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8.2
FDC Registers (CR00)
8.2.1 FDC Configuration Registers
FDC Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
FDC_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable FDC.
1: enable FDC.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of FDC base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
F0h
Description
The LSB of FDC base address.
IRQ Channel Select Register  Index 70h
Bit
Name
7-4 Reserved
3-0 SELFDCIRQ
R/W Default
-
-
R/W
06h
Description
Reserved.
Select the IRQ channel for FDC.
DMA Channel Select Register  Index 74h
Bit
Name
7-3 Reserved
2-0 SELFDCDMA
R/W Default
-
-
R/W
010
Description
Reserved.
Select the DMA channel for FDC.
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FDD Mode Register  Index F0h
Bit
Name
R/W Default
7-4 Reserved
-
-
3-2 IF_MODE
R/W
11
Description
Reserved.
00: Model 30 mode.
01: PS/2 mode.
10: Reserved.
11: AT mode (default).
1
FDMAMODE
R/W
1
0: enable burst mode.
1: non-busrt mode (default).
0
EN3MODE
R/W
0
0: normal floppy mode (default).
1: enhanced 3-mode FDD.
FDD Drive Type Register  Index F2h
Bit
Name
7-2 Reserved
1-0 FDD_TYPE
R/W Default
-
-
R/W
11
Description
Reserved.
FDD drive type.
FDD Selection Register  Index F4h
Bit
Name
R/W Default
7-5 Reserved
-
-
4-3 FDD_DRT
R/W
00
Description
Reserved.
Data rate table select, refer to table A.
00: select regular drives and 2.88 format.
01: 3-mode drive.
10: 2 mega tape.
11: reserved.
2
Reserved
1-0 FDD_DT
-
-
R/W
00
Reserved.
Drive type select, refer to table B.
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TABLE A
Data Rate Table Select
FDD_DRT[1]
FDD_DRT[0]
0
0
0
1
1
0
Data Rate
Selected Data Rate
DENSEL
DATARATE1
DATARATE0
MFM
FM
0
0
500K
250K
1
0
1
300K
150K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
0
1
500K
250K
0
1
0
250K
125K
0
1
1
1Meg
---
1
0
0
500K
250K
1
0
1
2Meg
---
0
1
0
250K
125K
0
1
1
1Meg
---
1
TABLE B
Drive Type
FDD_DT1
FDD_DT0
0
DRVDEN0
DENSEL
0
Remark
4/2/1 MB 3.5”
2/1 MB 5.25”
1/1.6/1 MB 3.5” (3-Mode )
0
1
DATARATE1
1
0
DENSEL#
1
1
DATARATE0
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8.3
UART1 Registers (CR01)
8.3.1 UART 1 Configuration Registers
UART 1 Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
UR1_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable UART 1.
1: enable UART 1.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of UART 1 base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
F8h
Description
The LSB of UART 1 base address.
IRQ Channel Select Register  Index 70h
Bit
Name
7-4 Reserved
3-0 SELUR1IRQ
R/W Default
-
-
R/W
4h
Description
Reserved.
Select the IRQ channel for UART 1.
RS485 Enable Register  Index F0h
Bit
Name
7-5 Reserved
4
RS485_EN
3-0 Reserved
R/W Default
Description
-
-
Reserved.
R/W
0
0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
-
-
Reserved.
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8.4
UART 2 Registers (CR02)
8.4.1 UART 2 Configuration Registers
UART 2 Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
UR2_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable UART 2.
1: enable UART 2.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of UART 2 base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
F8h
Description
The LSB of UART 2 base address.
IRQ Channel Select Register  Index 70h
Bit
Name
7-4 Reserved
3-0 SELUR2IRQ
R/W Default
-
-
R/W
3h
Description
Reserved.
Select the IRQ channel for UART 2.
RS485 Enable Register  Index F0h
Bit
Name
7-5 Reserved
4
RS485_EN
R/W Default
Description
-
-
Reserved.
R/W
0
0: RS232 driver.
1: RS485 driver. Auto drive RTS# low when transmitting data.
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3
RXW4C_IR
R/W
0
0: No reception delay when SIR is changed form TX to RX.
1: Reception delays 4 characters time when SIR is changed form TX to RX.
2
TXW4C_IR
R/W
0
0: No transmission delay when SIR is changed form RX to TX.
1: Transmission delays 4 characters time when SIR is changed form RX to TX.
1-0 Reserved
-
-
Reserved.
SIR Mode Control Register  Index F1h
Bit
Name
R/W Default
Description
7
Reserved
-
-
Reserved.
6
Reserved
-
-
Reserved.
5
Reserved
-
-
Reserved.
R/W
00
4-3 IRMODE
00: disable IR function.
01: disable IR function.
10: IrDA function, active pulse is 1.6uS.
11: IrDA function, active pulse is 3/16 bit time.
2
HDUPLX
R/W
1
0: SIR is in full duplex mode for loopbak test. TXW4C_IR and RXW4C_IR are
of no use.
1: SIR is in half duplex mode.
1
TXINV_IR
R/W
0
0: IRTX is in normal condition.
1: inverse the IRTX.
0
RXINV_IR
R/W
0
0: IRRX is in normal condition.
1: inverse the IRRX.
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8.5
Parallel Port Registers (CR03)
8.5.1 Parallel Port Configuration Registers
Parallel Port Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
PRT_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable Parallel Port.
1: enable Parallel Port.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
03h
Description
The MSB of Parallel Port base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
78h
Description
The LSB of Parallel Port base address.
IRQ Channel Select Register  Index 70h
Bit
Name
7-4 Reserved
3-0 SELPRTIRQ
R/W Default
-
-
R/W
7h
Description
Reserved.
Select the IRQ channel for Parallel Port.
DMA Channel Select Register  Index 74h
Bit
Name
7-5 Reserved
R/W Default
Description
-
-
Reserved.
R/W
0
0: non-burst mode DMA.
1: enable burst mode DMA.
Reserved.
4
ECP_DMA_MODE
3
Reserved
-
-
2-0 SELPRTDMA
R/W
011
Select the DMA channel for Parallel Port.
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PRT Mode Select Register  Index F0h
Bit
7
Name
SPP_IRQ_MODE
R/W Default
Description
R/W
0
Interrupt mode in non-ECP mode.
0: Level mode.
1: Pulse mode.
6-3 ECP_FIFO_THR
R/W
1000
ECP FIFO threshold.
2-0 PRT_MODE
R/W
010
000: Standard and Bi-direction (SPP) mode.
001: EPP 1.9 and SPP mode.
010: ECP mode (default).
011: ECP and EPP 1.9 mode.
100: Printer mode.
101: EPP 1.7 and SPP mode.
110: Reserved.
111: ECP and EPP1.7 mode.
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8.6
Hardware Monitor Registers (CR04)
8.6.1 Hardware Monitor Configuration Registers
Hardware Monitor Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
HM_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable Hardware Monitor.
1: enable Hardware Monitor.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
02h
Description
The MSB of Hardware Monitor base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
95h
Description
The LSB of Hardware Monitor base address.
IRQ Channel Select Register  Index 70h
Bit
Name
7-4 Reserved
3-0 SELHMIRQ
R/W Default
-
-
R/W
0000
Description
Reserved.
Select the IRQ channel for Hardware Monitor.
8.6.2 Device Registers
Before the device registers, the following is a register map order which shows a summary of all registers.
Please refer each one register if you want more detail information.
Register CR01 ~ CR03 Æ Configuration Registers
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Register CR10 ~ CR4F Æ Voltage Setting Register
Register CR60 ~ CR8E Æ Temperature Setting Register
Register CR90 ~ CRDF Æ Fan Control Setting Register
ÆFan1 Detail Setting CRA0 ~ CRAF
ÆFan2 Detail Setting CRB0 ~ CRBF
ÆFan3 Detail Setting CRC0 ~ CRCF
ÆFan4 Detail Setting CRD0 ~ CRDF
8.6.2.1 HW Monitor Config. Register  Index 01h
Bit
Name
R/W Default
Description
7-3
Reserved
0h
0
Reserved
2
POWER_DOWN
R/W
0
Hardware monitor function power down.
1
1
FAN_START
R/W
Set one to enable startup of fan monitoring operations; a zero puts the part
0
V_T_START
R/W
in standby mode.
1
Set one to enable startup of temperature and voltage monitoring
operations; a zero puts the part in standby mode.
8.6.2.2 BEEP OVT ALERT Config. Register  Index 02h
Bit
Name
7
Reserved
R/W
6
CASE_BEEP_EN
R/W
OVT_MODE
R/W
5-4
R/W Default
3
Reserved
R/W
2
CASE_SMI_EN
R/W
0
Dummy register.
0
0: Disable case open event output via BEEP.
1: Enable case open event output via BEEP.
0
00: The OVT# will be low active level mode.
01: The OVT# will be high active level mode.
10: The OVT# will indicate by 1Hz LED function.
11: The OVT# will indicate by (400/800HZ) BEEP output.
0
Dummy register.
0
0: Disable case open event output via PME.
1: Enable case open event output via PME.
0
1-0
ALERT_MODE
Description
R/W
00: The ALERT# will be low active level mode.
01: The ALERT# will be high active level mode.
10: The ALERT# will indicate by 1Hz LED function.
11: The ALERT# will indicate by (400/800HZ) BEEP output.
8.6.2.3 Case Open Config. Register  Index 03h
Bit
Name
R/W Default
Description
7-1
Reserved
R/W
0
Return 0 when read.
0
CASE_STS
R/W
0
Case open event status, write 1 to clear if case open event cleared.
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8.6.2.4 PECI AMDSI Select Register  Index 0Ah
Bit
Name
R/W Default
Description
7-6
Reserved
-
00
Reserved.
5
T1_IIR_EN
R/W
0
4
SST_EN
R/W
0
Set 1 to enable IIR for AMDSI/PECI reading.
The reading will be more stable.
Set 1 to enable SST interface.
0
3-2
VTT_SEL
R/W
00
1-0
MEAS_TYPE
R/W
PECI (Vtt) voltage select.
00: Vtt is 1.23V
01: Vtt is 1.13V
10: Vtt is 1.00V
11: Vtt is 1.00V
CPU Temperature Measurement method.
00: with external diode.
01: with PECI interface.
10: with AMDSI interface.
11: reserved.
8.6.2.5 PECI CPU Select Register  Index 0Bh
Bit
Name
R/W Default
0
7-4
CPU_SEL
R/W
3-1
Reserved
-
0
R/W
0
0
DOMAIN1_EN
Description
Select the Intel CPU socket number.
0000: no CPU presented. PECI host will use Ping() command to find CPU
address.
0001: CPU is in socket 0, i.e. PECI address is 0x30.
0010: CPU is in socket 0, i.e. PECI address is 0x31.
0100: CPU is in socket 0, i.e. PECI address is 0x32.
1000: CPU is in socket 0, i.e. PECI address is 0x33.
Otherwise are reserved.
Reserved.
If the CPU selected is dual core. Set this register 1 to read the temperature
of domain1.
8.6.2.6 AMDSI Version Register  Index 0Bh
Bit
Name
7-0
AMDSI_VER
7-0
Name
TCC_TEMP
R
-
Description
Return the AMDSI version.
(MEAS_TYPE == 2’b01)
R/W Default
R/W
Description
8’h55 TCC Activation Temperature.
The absolute value of CPU temperature is calculated by the equation:
CPU_TEMP = TCC_TEMP + PECI Reading.
The range of this register is 0 ~ 255.
8.6.2.8 AMDSI Node ID Register  Index 0Ch
Bit
Name
7-0
NODE_ID
(MEAS_TYPE ==2’b10)
R/W Default
8.6.2.7 TCC Temp. Register  Index 0Ch
Bit
(MEAS_TYPE == 2’b01)
(MEAS_TYPE ==2’b10)
R/W Default
R
-
Description
Return the AMDSI node id.
8.6.2.9 SST Address Register  Index 0Dh
Bit
Name
R/W Default
Description
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7-0
SST_ADDR
R/W
8’h4C Address for SST interface. Programmable.
8.6.2.10 VID Divide Register  Index 0Eh
Bit
Name
R/W Default
0
7-6
VIN6_DIV
R/W
0
5-4
VIN5_DIV
R/W
0
3
PECI_SCALE_ADD
R/W
0
2-0
PECI_SCALE
R/W
Description
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN6.
01: voltage source is divided by 2 and connect to VIN6.
10: voltage source is divided by 4 and connect to VIN6.
11: voltage source is divided by 16 and connect to VIN6.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN5.
01: voltage source is divided by 2 and connect to VIN5.
10: voltage source is divided by 4 and connect to VIN5.
11: voltage source is divided by 16 and connect to VIN5.
This register is used to indicate how to calculate the PECI reading with
PECI_SCALE register.
0: The real value is the reading adds the value calculated by
PECI_SCALE.
1: The real value is the reading adds the value calculated by
PECI_SCALE.
This register is used to control the PECI reading slope. See also
PECI_SCALE_ADD register.
000: The real value is the PECI reading.
001: The real value is (1 ± 1/2) PECI reading.
010: The real value is (1 ± 1/4) PECI reading.
011: The real value is (1 ± 1/8) PECI reading.
100: The real value is (1 ± 1/16) PECI reading.
101: The real value is (1 ± 1/32) PECI reading.
110: The real value is (1 ± 1/64) PECI reading.
111: The real value is (1 ± 1/128) PECI reading.
8.6.2.11 Configuration Register  Index 0Fh
Bit
Name
R/W Default
0
7-6
VIN4_DIV
R/W
0
5-4
VIN3_DIV
R/W
0
3-2
VIN2_DIV
R/W
0
1-0
VIN1_DIV
R/W
Description
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN4.
01: voltage source is divided by 2 and connect to VIN4.
10: voltage source is divided by 4 and connect to VIN4.
11: voltage source is divided by 16 and connect to VIN4.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN3.
01: voltage source is divided by 2 and connect to VIN3.
10: voltage source is divided by 4 and connect to VIN3.
11: voltage source is divided by 16 and connect to VIN3.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN2.
01: voltage source is divided by 2 and connect to VIN2.
10: voltage source is divided by 4 and connect to VIN2.
11: voltage source is divided by 16 and connect to VIN2.
The value indicates the divisor of the voltage source.
00: voltage source is directly connected to VIN1.
01: voltage source is divided by 2 and connect to VIN1.
10: voltage source is divided by 4 and connect to VIN1.
11: voltage source is divided by 16 and connect to VIN1.
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Voltage Setting
8.6.2.12 Voltage1 PME# Enable Register  Index 10h
Bit
Name
7-2
Reserved
EN_V1_PME
1
0
Reserved
R/W Default
--
0
Reserved
0
A one enables the corresponding interrupt status bit for PME# interrupt.
R/W
--
Description
Set this bit 1 to enable PME# function for VIN1.
0
Reserved
8.6.2.13 Voltage1 Interrupt Status Register  Index 11h
Bit
Name
R/W Default
7-2
Reserved
--
1
V1_ EXC _STS
R/W
0
Reserved
--
Description
0
Reserved
0
This bit is set when the VIN1 is over the high limit. Write 1 to clear this bit,
write 0 will be ignored.
0
Reserved
8.6.2.14 Voltage1 Exceeds Real Time Status Register 1  Index 12h
Bit
Name
R/W Default
7-2
Reserved
--
0
1
V1_EXC
RO
0
0
Reserved
--
0
Description
Reserved
A one indicates VIN1 exceeds the high or low limit. A zero indicates VIN1
is in the safe region.
Reserved
8.6.2.15 Voltage1 BEEP Enable Register  Index 13h
Bit
Name
7-2
Reserved
EN_V1_BEEP
1
0
Reserved
R/W Default
--
0
Reserved
0
A one enables the corresponding interrupt status bit for BEEP output of
R/W
--
Description
VIN1.
0
Reserved
8.6.2.16 Voltage reading and limit Index 20h- 4Fh
Address
Attribute
Default
Value
Description
20h
RO
--
VCC3V reading. The unit of reading is 8mV.
21h
RO
--
V1 (Vcore) reading. The unit of reading is 8mV.
22h
RO
--
V2 reading. The unit of reading is 8mV.
-74-
May, 2008
V0.27P
F71883
23h
RO
--
V3 reading. The unit of reading is 8mV.
24h
RO
--
V4 reading. The unit of reading is 8mV.
25h
RO
--
V5 reading. The unit of reading is 8mV.
26h
RO
--
V6 reading. The unit of reading is 8mV.
27h
RO
--
VSB3V reading. The unit of reading is 8mV.
28h
RO
--
VBAT reading. The unit of reading is 8mV.
29~2Fh
RO
FF
Reserved
30~31h
RO
FF
Reserved
32h
R/W
FF
V1 High Limit setting register. The unit is 8mV.
33h
RO
FF
Reserved
34~4Fh
RO
FF
Reserved
Temperature Setting
8.6.2.17 Temperature PME# Enable Register  Index 60h
Bit
7
6
5
4
3
2
1
0
Name
EN_ T3_OVT_PME
EN_ T2_ OVT_PME
EN_ T1_ OVT_PME
Reserved
EN_ T3_EXC_PME
EN_ T2_EXC_PME
EN_ T1_EXC_PME
Reserved
R/W Default
0
R/W
R/W
Description
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds OVT
limit setting.
0
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds OVT
setting.
0
R/W
R/W
setting.
0
Reserved
0
If set this bit to 1, PME# signal will be issued when TEMP3 exceeds high
R/W
R/W
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds OVT
limit setting.
0
If set this bit to 1, PME# signal will be issued when TEMP2 exceeds high
limit setting.
0
R/W
R/W
If set this bit to 1, PME# signal will be issued when TEMP1 exceeds high
limit setting.
0
Reserved
8.6.2.18 Temperature Interrupt Status Register  Index 61h
Bit
Name
R/W Default
Description
-75-
May, 2008
V0.27P
F71883
0
7
T3_OVT_STS
R/W
A one indicates TEMP3 temperature sensor has exceeded OVT limit or
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
6
T2_OVT _STS
R/W
A one indicates TEMP2 temperature sensor has exceeded OVT limit or
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
5
T1_OVT _STS
R/W
A one indicates TEMP1 temperature sensor has exceeded OVT limit or
below the “OVT limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
4
3
Reserved
T3_EXC _STS
R/W
0
Reserved
0
A one indicates TEMP3 temperature sensor has exceeded high limit or
R/W
below the “high limit –hysteresis”. Write 1 to clear this bit, write 0 will be
ignored.
0
2
T2_EXC _STS
R/W
A one indicates TEMP2 temperature sensor has exceeded high limit or
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
0
1
T1_EXC _STS
R/W
A one indicates TEMP1 temperature sensor has exceeded high limit or
below the “high limit –hysteresis” limit. Write 1 to clear this bit, write 0 will
be ignored.
0
Reserved
R/W
0
Reserved
8.6.2.19 Temperature Real Time Status Register  Index 62h
Bit
Name
R/W Default
0
7
T3_OVT
R/W
6
T2_OVT
R/W
5
T1_OVT
R/W
4
Reserved
R/W
3
T3_EXC
R/W
2
T2_EXC
R/W
1
T1_EXC
R/W
Description
Set when the TEMP3 exceeds the OVT limit. Clear when the TEMP3 is
below the “OVT limit –hysteresis” temperature.
0
Set when the TEMP2 exceeds the OVT limit. Clear when the TEMP2 is
below the “OVT limit –hysteresis” temperature.
0
Set when the TEMP1 exceeds the OVT limit. Clear when the TEMP1 is
below the “OVT limit –hysteresis” temperature.
0
Reserved
0
Set when the TEMP3 exceeds the high limit. Clear when the TEMP3 is
below the “high limit –hysteresis” temperature.
0
Set when the TEMP2 exceeds the high limit. Clear when the TEMP2 is
below the “high limit –hysteresis” temperature.
0
Set when the TEMP1 exceeds the high limit. Clear when the TEMP1 is
below the “high limit –hysteresis” temperature.
-76-
May, 2008
V0.27P
F71883
0
Reserved
R/W
0
Reserved
8.6.2.20 Temperature BEEP Enable Register  Index 63h
Bit
7
6
5
4
3
2
1
0
Name
EN_ T3_OVT_BEEP
EN_ T2_ OVT_BEEP
EN_ T1_ OVT_BEEP
Reserved
EN_ T3_EXC_BEEP
EN_ T2_EXC_BEEP
EN_ T1_EXC_BEEP
Reserved
R/W Default
0
R/W
R/W
Description
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds OVT
limit setting.
0
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds OVT
limit setting.
0
R/W
R/W
limit setting.
0
Reserved
0
If set this bit to 1, BEEP signal will be issued when TEMP3 exceeds high
R/W
R/W
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds OVT
limit setting.
0
If set this bit to 1, BEEP signal will be issued when TEMP2 exceeds high
limit setting.
0
R/W
R/W
If set this bit to 1, BEEP signal will be issued when TEMP1 exceeds high
limit setting.
0
Reserved
8.6.2.21 OVT Output Enable Register 1  Index 66h
Bit
Name
R/W Default
Description
7
EN_T3_ALERT
R
0
6
EN_T2_ALERT
R
0
5
EN_T1_ALERT
R
0
4
Reserved
R
0
Enable temperature 3 alert event (asserted when temperature over high
limit)
Enable temperature 2 alert event (asserted when temperature over high
limit)
Enable temperature 1 alert event (asserted when temperature over high
limit)
Reserved
3
EN_T3_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature3.
2
EN_T2_OVT
R/W
0
Enable over temperature (OVT) mechanism of temperature2.
1
EN_T1_OVT
R/W
1
Enable over temperature (OVT) mechanism of temperature1.
0
Reserved
R
0h
Reserved.
8.6.2.22 Temperature Sensor Type Register  Index 6Bh
Bit
Name
7-4
Reserved
RO
0
--
T3_MODE
R/W
1
0: TEMP3 is connected to a thermistor
1: TEMP3 is connected to a BJT.(default)
3
R/W Default
Description
-77-
May, 2008
V0.27P
F71883
2
T2_MODE
R/W
1
1
T1_MODE
R/W
1
0
Reserved
R
0h
0: TEMP2 is connected to a thermistor.
1: TEMP2 is connected to a BJT. (default)
0: TEMP1 is connected to a thermistor
1: TEMP1 is connected to a BJT.(default)
--
8.6.2.23 TEMP1 Limit Hystersis Select Register -- Index 6Ch
Bit
Name
R/W Default
4h
7-4
TEMP1_HYS
R/W
3-0
Reserved
R
Description
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
0h
--
8.6.2.24 TEMP2 and TEMP3 Limit Hystersis Select Register -- Index 6Dh
Bit
Name
R/W Default
2h
7-4
TEMP3_HYS
R/W
3-0
TEMP2_HYS
R/W
Description
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
4h
Limit hysteresis. (0~15 degree C)
Temperature and below the ( boundary – hysteresis ).
8.6.2.25 DIODE OPEN Status Register -- Index 6Fh
Bit
Name
7-4
Reserved
R/W Default
Description
RO
0h
Reserved
3
T3_DIODE_OPEN
RO
0h
External diode 3 is open
2
T2_DIODE_OPEN
RO
0h
External diode 2 is open
1
T1_DIODE_OPEN
RO
0h
This register indicates the abnormality of temperature 1 measurement.
When AMDSI interface is enabled, it indicates the error of not receiving
ACK bit when read TCON command is asserted.
When PECI interface is enabled, it indicates a error code is received from
PECI slave.
When external diode is used, it indicates the BJT is open or short.
R
0h
--
0
Reserved
Temperature  Index 70h- 8Fh
Default
Value
Address
Attribute
70h
Reserved
FFh
71h
Reserved
FFh
Description
Reserved
Reserved
-78-
May, 2008
V0.27P
F71883
72h
RO
--
º
Temperature 1 reading. The unit of reading is 1 C.At the moment of reading this
register.
73h
RO
--
Reserved
74h
RO
--
º
Temperature 2 reading. The unit of reading is 1 C.At the moment of reading this
register.
75h
RO
--
Reserved
76h
RO
--
º
Temperature 3 reading. The unit of reading is 1 C.At the moment of reading this
register.
77-7Bh
RO
--
Reserved
7C-7Fh
RO
FFh
Reserved
80h
Reserved
FFh
81h
Reserved
FFh
82h
R/W
64h
Temperature sensor 1 OVT limit. The unit is 1ºC.
83h
R/W
55h
Temperature sensor 1 high limit. The unit is 1ºC.
84h
R/W
64h
Temperature sensor 2 OVT limit. The unit is 1ºC.
85h
R/W
55h
Temperature sensor 2 high limit. The unit is 1ºC.
86h
R/W
55h
Temperature sensor 3 OVT limit. The unit is 1ºC.
87h
R/W
46h
Temperature sensor 3 high limit. The unit is 1ºC.
88-8Bh
RO
--
Reserved
8C~8Dh
RO
FFH
Reserved
Reserved
Reserved
8.6.2.26 Temperature Filter Select Register -- Index 8Eh
Bit
Name
R/W Default
Description
The queue time for second filter to quickly update values.
00: disable.
7-6
IIR-QUEUR3
R/W
0h
01: 16 times.
10: 32 times. (default)
11: 48 times.
-79-
May, 2008
V0.27P
F71883
The queue time for second filter to quickly update values.
00: disable.
5-4
IIR-QUEUR2
R/W
0h
01: 16 times.
10: 32 times. (default)
11: 48 times.
The queue time for second filter to quickly update values.
00: disable.
3-2
IIR-QUEUR1
R/W
0h
01: 16 times.
10: 32 times. (default)
11: 48 times.
0
Reserved
R
0h
--
Fan Control Setting
8.6.2.27 FAN PME# Enable Register  Index 90h
Bit
Name
7-4 Reserved
3
2
R/W Default
RO
EN_FAN4_PME
R/W
EN_FAN3_PME
R/W
Reserved
0h
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan4.
0h
0
A one enables the corresponding interrupt status bit for PME# interrupt..
Set this bit 1 to enable PME# function for Fan3.
0h
1
Description
0h
EN_FAN2_PME
R/W
EN_FAN1_PME
R/W
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan2.
0h
A one enables the corresponding interrupt status bit for PME# interrupt.
Set this bit 1 to enable PME# function for Fan1.
8.6.2.28 FAN Interrupt Status Register  Index 91h
Bit
7-4
Name
Reserved
R/W Default
RO
0
3
FAN4_STS
R/W
--
2
FAN3_STS
R/W
--
1
FAN2_STS
R/W
--
Description
Reserved
This bit is set when the fan4 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan3 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
This bit is set when the fan2 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
-80-
May, 2008
V0.27P
F71883
0
FAN1_STS
R/W
--
This bit is set when the fan1 count exceeds the count limit. Write 1 to
clear this bit, write 0 will be ignored.
8.6.2.29 FAN Real Time Status Register  Index 92h
Bit
Name
R/W Default
7-4
Reserved
--
0
3
FAN4_EXC
RO
--
2
FAN3_EXC
RO
--
1
FAN2_EXC
RO
--
0
FAN1_EXC
RO
--
Description
Reserved
This bit set to high mean that fan4 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan3 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan2 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
This bit set to high mean that fan1 count can’t meet expect count over than
SMI time(CR9F) or when duty not zero but fan stop over then 3 sec.
8.6.2.30 FAN BEEP# Enable Register  Index 93h
Bit
Name
R/W Default
Description
7
FULL_WITH_T3_EN R/W
0
Set one will enable FAN to force full speed when T3 over high limit.
6
FULL_WITH_T2_EN R/W
0
Set one will enable FAN to force full speed when T2 over high limit.
5
FULL_WITH_T1_EN R/W
0
Set one will enable FAN to force full speed when T1 over high limit.
4
Reserved
R/W
0
Reserved for local temperature.
3
EN_FAN4_BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
2
EN_FAN3_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
1
EN_FAN2_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
0
EN_FAN1_ BEEP
R/W
0
A one enables the corresponding interrupt status bit for BEEP.
8.6.2.31 Fan Type Select Register -- Index 94h
Bit
Name
R/W Default
Description
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
7-6
FAN4_TYPE
R/W
2’b0S terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
-81-
May, 2008
V0.27P
F71883
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
5-4
FAN3_TYPE
R/W
2’b 0S terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (pushpull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
3-2
FAN2_TYPE
R/W
2’b 0S terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
00: Output PWM mode (push pull) to control fans.
01: Use linear fan application circuit to control fan speed by fan’s power
1-0
FAN1_TYPE
R/W
2’b 0S terminal .
10: Output PWM mode (open drain) to control Intel 4-wire fans.
11: Reserved.
S: Register default values are decided by trapping.
8.6.2.32 Fan mode Select Register -- Index 96h
Bit
Name
R/W Default
Description
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xD6-0xDE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xD6-0xDE.
7-6
FAN4_MODE
R/W
1h
10: Manual mode fan control, user can write expect RPM count to
0xD2-0xD3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xD3, and F71883 will output this value
duty or voltage to control fan speed.
-82-
May, 2008
V0.27P
F71883
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xC6-0xCE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xC6-0xCE.
5-4
FAN3_MODE
R/W
1h
10: Manual mode fan control, user can write expect RPM count to
0xC2-0xC3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xC3, and F71883 will output this value
duty or voltage to control fan speed.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xB6-0xBE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle (voltage)
3-2
FAN2_MODE
R/W
1h
that define in 0xB6-0xBE.
10: Manual mode fan control, user can write expect RPM count to
0xB2-0xB3, and F71883 will auto control duty cycle (PWM fan type) or
voltage (linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage (linear fan type) to 0xB3, and F71883 will output this value
duty or voltage to control fan speed.
00: Auto fan speed control, fan speed will follow different temperature by
different RPM that define in 0xA6-0xAE.
01: Auto fan speed control, fan speed will follow different temperature by
different duty cycle that define in 0xA6-0xAE.
1-0
FAN1_MODE
R/W
1h
10: Manual mode fan control, user can write expect RPM count to
0xA2-0xA3, and F71883 will auto control duty cycle (PWM fan type) or
voltage(linear fan type) to control fan speed.
11: Manual mode fan control, user can write expect duty cycle (PWM fan
type) or voltage(linear fan type) to 0xA3, and F71883 will output this value
duty or voltage to control fan speed.
8.6.2.33 Auto Fan1 and Fan2 Boundary Hystersis Select Register -- Index 98h
Bit
Name
R/W Default
4h
7-4
FAN2_HYS
R/W
Description
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
-83-
May, 2008
V0.27P
F71883
4h
3-0
FAN1_HYS
R/W
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
8.6.2.34 Auto Fan3 and Fan4 Boundary Hystersis Select Register -- Index 99h
Bit
Name
R/W Default
2h
7-4
FAN4_HYS
R/W
Description
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
2h
3-0
FAN3_HYS
R/W
0000: Boundary hysteresis. (0~15 degree C)
Segment will change when the temperature over the boundary
temperature and below the ( boundary – hysteresis ).
8.6.2.35 Auto Fan Duty Update Rate Select Register -- Index 9Bh
Bit
Name
R/W Default
1h
7-6
FAN4_RATE_SEL
R/W
1h
5-4
FAN3_RATE_SEL
R/W
1h
3-2
FAN2_RATE_SEL
R/W
1h
1-0
FAN1_RATE_SEL
R/W
Description
Fan4 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan3 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan2 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
Fan1 duty update rate:
00: 2Hz
01: 5Hz (default)
10: 10Hz
11: 20Hz
8.6.2.36 FAN1 and FAN2 START UP DUTY-CYCLE/VOLTAGE  Index 9Ch
Bit
Name
R/W Default
5h
7-4
FAN2_STOP_DUTY
R/W
Description
When fan start, the FAN_CTRL2 will increase duty-cycle from 0 to this
(value x 8) directly. And if fan speed is down, the FAN_CTRL 2 will
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
-84-
May, 2008
V0.27P
F71883
5h
3-0
FAN1_STOP_DUTY
When fan start, the FAN_CTRL 1 will increase duty-cycle from 0 to this
(value x 8 directly. And if fan speed is down, the FAN_CTRL 1 will
R/W
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
8.6.2.37 FAN3 and FAN4 START UP DUTY-CYCLE/VOLTAGE  Index 9Dh
Bit
Name
R/W Default
5h
7-4
FAN4_STOP_DUTY
Description
When fan start, the FAN_CTRL 4 will increase duty-cycle from 0 to this
(value x 8) directly. And if fan speed is down, the FAN_CTRL 4 will
R/W
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
5h
3-0
FAN3_STOP_DUTY
When fan start, the FAN_CTRL 3 will increase duty-cycle from 0 to this
(value x 8 directly. And if fan speed is down, the FAN_CTRL 3 will
R/W
decrease duty-cycle to 0 when the PWM duty cycle is less than this (value
x 4).
8.6.2.38 Fan Fault Time Register -- Index 9Fh
Bit
Name
R/W Default
7-5
Reserved
--
4
FULL_DUTY_SEL
R/W
Description
--
Reservd
--
0: the full duty is 100%.
1: the full duty is 60% (default).
This register is power on trap by DTR1#.
This register determines the time of fan fault. The condition to cause fan
fault event is:
When PWM_Duty reaches FFh, if the fan speed count can’t reach the fan
expect count in time.
3-0
F_FAULT_TIME
R/W
Ah
The unit of this register is 1 second. The default value is 11 seconds.
(Set to 0 , means 1 seconds. ; Set to 1, means 2 seconds.
Set to 2, means 3 seconds. …. )
Another condition to cause fan fault event is fan stop and the PWM duty is
greater than the minimum duty programmed by the register index 9C-9Dh.
Fan1 Index A0h- AFh
Default
Address
Description
Attribute
Value
-85-
May, 2008
V0.27P
F71883
A0h
RO
8’h0f
FAN1 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
A1h
RO
8’hff
FAN1 count reading (LSB).
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (MSB), in auto fan mode (CR96 bit1Î0) this
A2h
R/W
8’h00
register is auto updated by hardware.
Duty mode(CR96 bit0=1):
This byte is reserved byte.
RPM mode(CR96 bit0=0):
FAN1 expect speed count value (LSB) or expect PWM duty, in auto fan mode
this register is auto updated by hardware and read only.
A3h
R/W
8’h01
Duty mode(CR96 bit0=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
bit1Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
A4h
R/W
8’h03
FAN1 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
A5h
R/W
8’hff
FAN1 full speed count reading (LSB).
8.6.2.39 VT1 BOUNDARY 1 TEMPERATURE – Index A6h
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
3Ch The 1st BOUNDARY temperature for VT1 in temperature mode.
(60oC)
When VT1 temperature is exceed this boundary, FAN1 expect value will
6-0
BOUND1TMP1
R/W
load from segment 1 register (index AA)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 2 register (index AAh).
8.6.2.40 VT1 BOUNDARY 2 TEMPERATURE – Index A7
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
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st
32
The 2 BOUNDARY temperature for VT1 in temperature mode.
o
(50 C)
When VT1 temperature is exceed this boundary, FAN1 expect value will
6-0
BOUND2TMP1
R/W
load from segment 2 register (index AB)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 3 register (index ABh).
8.6.2.41 VT1 BOUNDARY 3 TEMPERATURE – Index A8h
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
28h The 3st BOUNDARY temperature for VT1 in temperature mode.
(40oC)
When VT1 temperature is exceed this boundary, FAN1 expect value will
6-0
BOUND3TMP1
R/W
load from segment 3 register (index AC)h.
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 4 register (index ACh).
8.6.2.42 VT1 BOUNDARY 4 TEMPERATURE – Index A9
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
1Eh The 4st BOUNDARY temperature for VT1 in temperature mode.
(30oC)
When VT1 temperature is exceed this boundary, FAN1 expect value will
6-0
BOUND4TMP1
R/W
load from segment 4 register (index ADh).
When VT1 temperature is below this boundary – hysteresis, FAN1 expect
value will load from segment 5 register (index ADh).
8.6.2.43 FAN1 SEGMENT 1 SPEED COUNT – Index AAh
Bit
Name
R/W Default
Description
FFh The meaning of this register is depending on the FAN1_MODE(CR96)
(100%)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
7-0
SEC1SPEED1
R/W
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
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8.6.2.44 FAN1 SEGMENT 2 SPEED COUNT
Bit
Name
– Index ABh
R/W Default
Description
D9h The meaning of this register is depending on the FAN1_MODE(CR96)
(85%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC2SPEED1
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.45 FAN1 SEGMENT 3 SPEED COUNT
Bit
Name
– Index ACh
R/W Default
Description
B2h The meaning of this register is depending on the FAN1_MODE(CR96)
(70%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC3SPEED1
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.46 FAN1 SEGMENT 4 SPEED COUNT
Bit
Name
– Index ADh
R/W Default
Description
99h The meaning of this register is depending on the FAN1_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC4SPEED1
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.47 FAN1 SEGMENT 5 SPEED COUNT
Bit
Name
– Index AEh
R/W Default
Description
80h The meaning of this register is depending on the FAN1_MODE(CR96)
(50%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC5SPEED1
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.48 FAN1 Temperature Mapping Select
– Index AFh
Bit
Name
R/W Default
Description
7-6
Reserved
--
0
Reserved
5
FAN1_UP_T_EN
R/W
0
Set 1 to force FAN1 to full speed if any temperature over its high limit.
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4
FAN1_INTERPOLATION_EN R/W
3
0
Set 1 will enable the interpolation of the fan expect table.
0
This register controls the FAN1 duty movement when temperature over
highest boundary.
0: The FAN1 duty will increases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC1SPEED1
register.
This bit only activates in duty mode.
This register controls the FAN1 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN1 duty will decreases with the slope selected by
FAN1_RATE_SEL register.
1: The FAN1 duty will directly jumps to the value of SEC2SPEED1
register.
This bit only activates in duty mode.
FAN1_JUMP_HIGH_EN R/W
0
2
FAN1_JUMP_LOW_EN
R/W
0: reserved.
1-0
Fan1_temp_sel
R/W
1
1: fan1 follow temperature 1.
2: fan1 follow temperature 2.
3: fan1 follow temperature 3.
Fan2 Index B0h- BFh
Default
Address
Description
Attribute
Value
B0h
RO
8’h0f
FAN2 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
B1h
RO
8’hff
FAN2 count reading (LSB).
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (MSB), in auto fan mode(CR96 bit3Î0) this
B2h
R/W
8’h00
register is auto updated by hardware.
Duty mode(CR96 bit2=1):
This byte is reserved byte.
RPM mode(CR96 bit2=0):
FAN2 expect speed count value (LSB) or expect PWM duty , in auto fan mode
this register is auto updated by hardware and read only.
B3h
R/W
8’h01
Duty mode(CR96 bit2=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
bit3Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
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B4h
R/W
8’h03
FAN2 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
B5h
R/W
8’hff
FAN2 full speed count reading (LSB).
8.6.2.49 VT2 BOUNDARY 1 TEMPERATURE – Index B6h
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
3Ch The 1st BOUNDARY temperature for VT2 in temperature mode.
(60oC)
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0
BOUND1TMP2
R/W
load from segment 1 register (index BA)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 2 register (index BAh).
8.6.2.50 VT2 BOUNDARY 2 TEMPERATURE – Index B7
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
st
32
The 2 BOUNDARY temperature for VT2 in temperature mode.
o
(50 C)
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0
BOUND2TMP2
R/W
load from segment 2 register (index BB)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 3 register (index BBh).
8.6.2.51 VT2 BOUNDARY 3 TEMPERATURE – Index B8h
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
28h The 3st BOUNDARY temperature for VT2 in temperature mode.
(40oC)
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0
BOUND3TMP2
R/W
load from segment 3 register (index BC)h.
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 4 register (index BCh).
8.6.2.52 VT2 BOUNDARY 4 TEMPERATURE – Index B9
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
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1Eh The 4st BOUNDARY temperature for VT2 in temperature mode.
(30oC)
When VT2 temperature is exceed this boundary, FAN2 expect value will
6-0
BOUND4TMP2
R/W
load from segment 4 register (index BDh).
When VT2 temperature is below this boundary – hysteresis, FAN2 expect
value will load from segment 5 register (index BDh).
8.6.2.53 FAN2 SEGMENT 1 SPEED COUNT
Bit
Name
– Index BAh
R/W Default
Description
FFh The meaning of this register is depending on the FAN2_MODE(CR96)
(100%)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
7-0
SEC1SPEED2
R/W
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.54 FAN2 SEGMENT 2 SPEED COUNT – Index BBh
Bit
Name
R/W Default
Description
D9h The meaning of this register is depending on the FAN2_MODE(CR96)
(85%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC2SPEED2
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.55 FAN2 SEGMENT 3 SPEED COUNT
Bit
Name
– Index BCh
R/W Default
Description
B2h The meaning of this register is depending on the FAN2_MODE(CR96)
(70%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC3SPEED2
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.56 FAN2 SEGMENT 4 SPEED COUNT
Bit
Name
– Index BDh
R/W Default
Description
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99h The meaning of this register is depending on the FAN2_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC4SPEED2
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.57 FAN2 SEGMENT 5 SPEED COUNT
Bit
Name
– Index BEh
R/W Default
Description
80h The meaning of this register is depending on the FAN2_MODE(CR96)
(50%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC5SPEED2
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.58 FAN2 Temperature Mapping Select
– Index BFh
Bit
Name
7-6
Reserved
--
0
Reserved
5
FAN2_UP_T_EN
R/W
0
Set 1 to force FAN2 to full speed if any temperature over its high limit.
FAN2_INTERPOLATION_EN R/W
0
Set 1 will enable the interpolation of the fan expect table.
0
This register controls the FAN2 duty movement when temperature over
highest boundary.
0: The FAN2 duty will increases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC1SPEED2
register.
This bit only activates in duty mode.
This register controls the FAN2 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN2 duty will decreases with the slope selected by
FAN2_RATE_SEL register.
1: The FAN2 duty will directly jumps to the value of SEC2SPEED2
register.
This bit only activates in duty mode.
4
3
R/W Default
FAN2_JUMP_HIGH_EN R/W
0
2
FAN2_JUMP_LOW_EN
R/W
Description
0: reserved.
1-0
Fan2_temp_sel
R/W
2
1: fan2 follow temperature 1.
2: fan2 follow temperature 2.
3: fan2 follow temperature 3.
Fan3 Index C0h- CFh
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Default
Address
Description
Attribute
Value
C0h
RO
8’h0F
C1h
RO
8’hff
FAN3 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
FAN3 count reading (LSB).
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (MSB), in auto fan mode(CR96 bit5Î0) this
C2h
R/W
8’h00
register is auto updated by hardware.
Duty mode(CR96 bit4=1):
This byte is reserved byte.
RPM mode(CR96 bit4=0):
FAN3 expect speed count value (LSB) or expect PWM duty , in auto fan mode
this register is auto updated by hardware and read only.
C3h
R/W
8’h01
Duty mode(CR96 bit4=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
bit5Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
C4h
R/W
8’h03
FAN3 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
C5h
R/W
8’hff
FAN3 full speed count reading (LSB).
8.6.2.59 VT3 BOUNDARY 1 TEMPERATURE – Index C6h
Bit
7
Name
Reserved
R/W Default
RO
0
Description
Return 0 when read.
3Ch The 1st BOUNDARY temperature for VT3 in temperature mode.
(60oC)
When VT3 temperature is exceed this boundary, FAN3 expect value will
6-0
BOUND1TMP3
R/W
load from segment 1 register (index CA)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 2 register (index CAh).
8.6.2.60 VT3 BOUNDARY 2 TEMPERATURE – Index C7
Bit
7
Name
Reserved
R/W Default
RO
0
Description
Return 0 when read.
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st
32
The 2 BOUNDARY temperature for VT3 in temperature mode.
o
(50 C)
When VT3 temperature is exceed this boundary, FAN3 expect value will
6-0
BOUND2TMP3
R/W
load from segment 2 register (index CB)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 3 register (index CBh).
8.6.2.61 VT3 BOUNDARY 3 TEMPERATURE – Index C8h
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
28h The 3st BOUNDARY temperature for VT3 in temperature mode.
(40oC)
When VT3 temperature is exceed this boundary, FAN3 expect value will
6-0
BOUND3TMP3
R/W
load from segment 3 register (index CC)h.
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 4 register (index CCh).
8.6.2.62 VT3 BOUNDARY 4 TEMPERATURE – Index C9
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
1Eh The 4st BOUNDARY temperature for VT3 in temperature mode.
(30oC)
When VT3 temperature is exceed this boundary, FAN3 expect value will
6-0
BOUND4TMP3
R/W
load from segment 4 register (index CDh).
When VT3 temperature is below this boundary – hysteresis, FAN3 expect
value will load from segment 5 register (index CDh).
8.6.2.63 FAN3 SEGMENT 1 SPEED COUNT
Bit
Name
– Index CAh
R/W Default
Description
FFh The meaning of this register is depending on the FAN3_MODE(CR96)
(100%)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
7-0
SEC1SPEED3
R/W
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
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8.6.2.64 FAN3 SEGMENT 2 SPEED COUNT – Index CBh
Bit
Name
R/W Default
Description
D9h The meaning of this register is depending on the FAN3_MODE(CR96)
(85%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC2SPEED3
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.65 FAN3 SEGMENT 3 SPEED COUNT
Bit
Name
– Index CCh
R/W Default
Description
B2h The meaning of this register is depending on the FAN3_MODE(CR96)
(70%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC3SPEED3
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.66 FAN3 SEGMENT 4 SPEED COUNT
Bit
Name
– Index CDh
R/W Default
Description
99h The meaning of this register is depending on the FAN3_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC4SPEED3
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.67 FAN3 SEGMENT 5 SPEED COUNT
Bit
Name
– Index CEh
R/W Default
Description
80h The meaning of this register is depending on the FAN3_MODE(CR96)
(50%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC5SPEED3
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.68 FAN3 Temperature Mapping Select
– Index CFh
Bit
Name
R/W Default
Description
7-6
Reserved
--
0
Reserved
5
FAN3_UP_T_EN
R/W
0
Set 1 to force FAN3 to full speed if any temperature over its high limit.
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FAN3_INTERPOLATION_
R/W
EN
4
3
0
Set 1 will enable the interpolation of the fan expect table.
0
This register controls the FAN3 duty movement when temperature over
highest boundary.
0: The FAN3 duty will increases with the slope selected by
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC1SPEED3
register.
This bit only activates in duty mode.
This register controls the FAN3 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN3 duty will decreases with the slope selected by
FAN3_RATE_SEL register.
1: The FAN3 duty will directly jumps to the value of SEC2SPEED3
register.
This bit only activates in duty mode.
FAN3_JUMP_HIGH_EN R/W
0
2
FAN3_JUMP_LOW_EN
R/W
0: reserved.
1-0
Fan3_temp_sel
R/W
3
1: fan3 follow temperature 1.
2: fan3 follow temperature 2.
3: fan3 follow temperature 3.
Fan4 Index D0h- DFh
Default
Address
Description
Attribute
Value
D0h
RO
8’h0f
FAN4 count reading (MSB). At the moment of reading this register, the LSB will
be latched. This will prevent from data updating when reading. To read the fan
count correctly, read MSB first and followed read the LSB.
D1h
RO
8’hff
FAN4 count reading (LSB).
RPM mode(CR96 bit6=0):
FAN4 expect speed count value (MSB), in auto fan mode(CR96 bit7Î0) this
D2h
R/W
8’h00
register is auto updated by hardware.
Duty mode(CR96 bit6=1):
This byte is reserved byte.
RPM mode(CR96 bit6=0):
FAN4 expect speed count value (LSB) or expect PWM duty , in auto fan mode
D3h
R/W
8’h01
this register is auto updated by hardware and read only.
Duty mode(CR96 bit6=1):
The Value programming in this byte is duty value. In auto fan mode(CR96
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bit7Î0) this register is updated by hardware.
Ex: 5Î 5*100/255 %
255 Î 100%
D4h
R/W
8’h03
FAN4 full speed count reading (MSB). At the moment of reading this register,
the LSB will be latched. This will prevent from data updating when reading. To
read the fan count correctly, read MSB first and followed read the LSB.
D5h
R/W
8’hff
FAN4 full speed count reading (LSB).
8.6.2.69 VT4 BOUNDARY 1 TEMPERATURE – Index D6h
Bit
7
Name
Reserved
R/W Default
RO
0
Description
Return 0 when read.
3Ch The 1st BOUNDARY temperature for VT4 in temperature mode.
(60oC)
When VT4 temperature is exceed this boundary, FAN4 expect value will
6-0
BOUND1TMP4
R/W
load from segment 1 register (index DA)h.
When VT4 temperature is below this boundary – hysteresis, FAN4 expect
value will load from segment 2 register (index DAh).
8.6.2.70 VT4 BOUNDARY 2 TEMPERATURE – Index D7
Bit
7
Name
Reserved
R/W Default
RO
0
Description
Return 0 when read.
st
32
The 2 BOUNDARY temperature for VT4 in temperature mode.
o
(50 C)
When VT4 temperature is exceed this boundary, FAN4 expect value will
6-0
BOUND2TMP4
R/W
load from segment 2 register (index DB)h.
When VT4 temperature is below this boundary – hysteresis, FAN4 expect
value will load from segment 3 register (index DBh).
8.6.2.71 VT4 BOUNDARY 3 TEMPERATURE – Index D8h
Bit
7
Name
Reserved
R/W Default
RO
0
Description
Return 0 when read.
28h The 3st BOUNDARY temperature for VT4 in temperature mode.
(40oC)
When VT4 temperature is exceed this boundary, FAN4 expect value will
6-0
BOUND3TMP4
R/W
load from segment 3 register (indexDC)h.
When VT4 temperature is below this boundary – hysteresis, FAN4 expect
value will load from segment 4 register (index DCh).
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8.6.2.72 VT4 BOUNDARY 4 TEMPERATURE – Index D9
Bit
Name
7
Reserved
R/W Default
RO
0
Description
Return 0 when read.
1Eh The 4st BOUNDARY temperature for VT4 in temperature mode.
(30oC)
When VT4 temperature is exceed this boundary, FAN4 expect value will
6-0
BOUND4TMP4
R/W
load from segment 4 register (index ADh).
When VT4 temperature is below this boundary – hysteresis, FAN4 expect
value will load from segment 5 register (index DDh).
8.6.2.73 FAN4 SEGMENT 1 SPEED COUNT
Bit
Name
– Index DAh
R/W Default
Description
FFh The meaning of this register is depending on the FAN4_MODE(CR96)
(100%)
2’b00: The value that set in this byte is the relative expect fan speed % of
the full speed in this temperature section.
Ex:
7-0
SEC1SPEED4
R/W
100%:full speed: User must set this register to 0.
60% full speed: (100-60)*32/60, so user must program 21 to this reg.
X% full speed: The value programming in this byte is Î (100-X)*32/X
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.74 FAN4 SEGMENT 2 SPEED COUNT – Index DBh
Bit
Name
R/W Default
Description
D9h The meaning of this register is depending on the FAN4_MODE(CR96)
(85%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC2SPEED4
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.75 FAN4 SEGMENT 3 SPEED COUNT
Bit
Name
– Index DCh
R/W Default
Description
B2h The meaning of this register is depending on the FAN4_MODE(CR96)
(70%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC3SPEED4
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
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8.6.2.76 FAN4 SEGMENT 4 SPEED COUNT
Bit
Name
– Index DDh
R/W Default
Description
99h The meaning of this register is depending on the FAN4_MODE(CR96)
(60%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC4SPEED4
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.77 FAN4 SEGMENT 5 SPEED COUNT
Bit
Name
– Index DEh
R/W Default
Description
80h The meaning of this register is depending on the FAN4_MODE(CR96)
(50%)
2’b00: The value that set in this byte is the relative expect fan speed % of
7-0
SEC5SPEED4
R/W
the full speed in this temperature section.
2’b01: The value that set in this byte is mean the expect PWM duty-cycle
in this temperature section.
8.6.2.78 FAN4 Temperature Mapping Select
– Index DFh
Bit
Name
7-6
Reserved
--
0
Reserved
5
FAN4_UP_T_EN
R/W
0
Set 1 to force FAN4 to full speed if any temperature over its high limit.
FAN4_INTERPOLATION_
R/W
EN
0
Set 1 will enable the interpolation of the fan expect table.
0
This register controls the FAN4 duty movement when temperature over
highest boundary.
0: The FAN4 duty will increases with the slope selected by
FAN4_RATE_SEL register.
1: The FAN4 duty will directly jumps to the value of SEC1SPEED4
register.
This bit only activates in duty mode.
This register controls the FAN4 duty movement when temperature under
(highest boundary – hysteresis).
0: The FAN4 duty will decreases with the slope selected by
FAN4_RATE_SEL register.
1: The FAN4 duty will directly jumps to the value of SEC2SPEED4
register.
This bit only activates in duty mode.
4
3
R/W Default
FAN4_JUMP_HIGH_EN R/W
0
2
FAN4_JUMP_LOW_EN
R/W
Description
0: reserved.
1-0
Fan4_temp_sel
R/W
0
1: fan4 follow temperature 1.
2: fan4 follow temperature 2.
3: fan4 follow temperature 3.
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8.7
KBC Registers (CR05)
8.7.1 KBC Configuration Registers
KBC Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
KBC_EN
R/W Default
Description
-
-
Reserved
R/W
1
0: disable KBC.
1: enable KBC.
When the DTR1# is pulled down. KBC_EN is reset to 0.DTR1# is internal pull
up.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of KBC command port address. The address of data port is
command port address + 4;
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
60h
Description
The LSB of KBC command port address. The address of data port is command
port address + 4.
KB IRQ Channel Select Register  Index 70h
Bit
Name
R/W Default
7-4 Reserved
-
-
3-0 SELKIRQ
R/W
0h
Description
Reserved.
Select the IRQ channel for keyboard interrupt.
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Mouse IRQ Channel Select Register  Index 72h
Bit
Name
R/W Default
7-4 Reserved
-
-
3-0 SELMIRQ
R/W
0h
Description
Reserved.
Select the IRQ channel for PS/2 mouse interrupt.
Clock Select Register  Index F0h
Bit
Name
7-6 SELCLK_KBC
R/W Default
R/W
10
Description
00: select 6MHz clock as KBC clock input.
01: select 8MHz clock as KBC clock input.
10: select 12MHz clock as KBC clock input (default).
11: select 16MHz clock as KBC clock input.
5-2 Reserved
1
GA20_EN
-
-
Reserved.
R/W
1
0: GATE20# software control.
1: GATE20# hardware speed up.
0
HKBRST
R/W
1
0: KBRST# software control.
1: KBRST# hardware speed up.
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8.8
GPIO Registers (CR06)
8.8.1 Configuration Registers
GPIO Output Enable Register  Index F0h
Bit
Name
R/W Default
Description
7
GPIO7_OE
R/W
0
0: GPIO7 is in input mode.
1: GPIO7 is in output mode.
6
GPIO6_OE
R/W
0
0: GPIO6 is in input mode.
1: GPIO6 is in output mode.
5
GPIO5_OE
R/W
0
0: GPIO5 is in input mode.
1: GPIO5 is in output mode.
4
GPIO4_OE
R/W
0
0: GPIO4 is in input mode.
1: GPIO4 is in output mode.
3
GPIO3_OE
R/W
0
0: GPIO3 is in input mode.
1: GPIO3 is in output mode.
2
GPIO2_OE
R/W
0
0: GPIO2 is in input mode.
1: GPIO2 is in output mode.
1
GPIO1_OE
R/W
0
0: GPIO1 is in input mode.
1: GPIO1 is in output mode.
0
GPIO0_OE
R/W
0
0: GPIO0 is in input mode.
1: GPIO0 is in output mode.
GPIO Output Data Register  Index F1h
Bit
Name
R/W Default
Description
7
GPIO7_VAL
R/W
1
0: GPIO7 outputs 0 when in output mode.
1: GPIO7 outputs1 when in output mode.
6
GPIO6_VAL
R/W
1
0: GPIO6 outputs 0 when in output mode.
1: GPIO6 outputs1 when in output mode.
5
GPIO5_VAL
R/W
1
0: GPIO5 outputs 0 when in output mode.
1: GPIO5 outputs 1 when in output mode.
4
GPIO4_VAL
R/W
1
0: GPIO4 outputs 0 when in output mode.
1: GPIO4 outputs 1 when in output mode.
3
GPIO3_VAL
R/W
1
0: GPIO3 outputs 0 when in output mode.
1: GPIO3 outputs 1 when in output mode.
2
GPIO2_VAL
R/W
1
0: GPIO2 outputs 0 when in output mode.
1: GPIO2 outputs 1 when in output mode.
1
GPIO1_VAL
R/W
1
0: GPIO1 outputs 0 when in output mode.
1: GPIO1 outputs 1 when in output mode.
0
GPIO0_VAL
R/W
1
0: GPIO0 outputs 0 when in output mode.
1: GPIO0 outputs 1 when in output mode.
GPIO Pin Status Register  Index F2h
Bit
Name
R/W Default
Description
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7
GPIO7_IN
R
-
The pin status of GPIO07/Turbo1#.
6
GPIO6_IN
R
-
The pin status of SLOTOCC#/GPIO06.
5
GPIO5_IN
R
-
The pin status of VIDOUT5/GPIO05/SIC.
4
GPIO4_IN
R
-
The pin status of VIDOUT4/GPIO04.
3
GPIO3_IN
R
-
The pin status of VIDOUT3/GPIO03.
2
GPIO2_IN
R
-
The pin status of VIDOUT2/GPIO02.
1
GPIO1_IN
R
-
The pin status of VIDOUT1/GPIO01.
0
GPIO0_IN
R
-
The pin status of VIDOUT0/GPIO00.
GPIO Drive Enable Register  Index F3h
Bit
Name
R/W Default
Description
7
GPIO7_DRV_EN
R/W
0
0: GPIO7 is open drain in output mode.
1: GPIO7 is push pull in output mode.
6
GPIO6_DRV_EN
R/W
0
0: GPIO6 is open drain in output mode.
1: GPIO6 is push pull in output mode.
5
GPIO5_DRV_EN
R/W
0
0: GPIO5 is open drain in output mode.
1: GPIO5 is push pull in output mode.
4
GPIO4_DRV_EN
R/W
0
0: GPIO4 is open drain in output mode.
1: GPIO4 is push pull in output mode.
3
GPIO3_DRV_EN
R/W
0
0: GPIO3 is open drain in output mode.
1: GPIO3 is push pull in output mode.
2
GPIO2_DRV_EN
R/W
0
0: GPIO2 is open drain in output mode.
1: GPIO2 is push pull in output mode.
1
GPIO1_DRV_EN
R/W
0
0: GPIO1 is open drain in output mode.
1: GPIO1 is push pull in output mode.
0
GPIO0_DRV_EN
R/W
0
0: GPIO0 is open drain in output mode.
1: GPIO0 is push pull in output mode.
GPIO1 Output Enable Register  Index E0h
Bit
Name
R/W Default
Description
7
GPIO17_OE
R/W
0
0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
6
GPIO16_OE
R/W
0
0: GPIO16 is in input mode.
1: GPIO16 is in output mode.
5
GPIO15_OE
R/W
0
0: GPIO15 is in input mode.
1: GPIO15 is in output mode.
4
GPIO14_OE
R/W
0
0: GPIO14 is in input mode.
1: GPIO14 is in output mode.
3
GPIO13_OE
R/W
0
0: GPIO13 is in input mode.
1: GPIO13 is in output mode.
2
GPIO12_OE
R/W
0
0: GPIO12 is in input mode.
1: GPIO12 is in output mode.
1
GPIO11_OE
R/W
0
0: GPIO11 is in input mode.
1: GPIO11 is in output mode.
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0
GPIO10_OE
R/W
0
0: GPIO10 is in input mode.
1: GPIO10 is in output mode.
GPIO1 Output Data Register  Index E1h
Bit
Name
R/W Default
Description
7
GPIO17_VAL
R/W
1
0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
6
GPIO16_VAL
R/W
1
0: GPIO16 outputs 0 when in output mode.
1: GPIO16 outputs1 when in output mode.
5
GPIO15_VAL
R/W
1
0: GPIO15 outputs 0 when in output mode.
1: GPIO15 outputs 1 when in output mode.
4
GPIO14_VAL
R/W
1
0: GPIO14 outputs 0 when in output mode.
1: GPIO14 outputs 1 when in output mode.
3
GPIO13_VAL
R/W
1
0: GPIO13 outputs 0 when in output mode.
1: GPIO13 outputs 1 when in output mode.
2
GPIO12_VAL
R/W
1
0: GPIO12 outputs 0 when in output mode.
1: GPIO12 outputs 1 when in output mode.
1
GPIO11_VAL
R/W
1
0: GPIO11 outputs 0 when in output mode.
1: GPIO11 outputs 1 when in output mode.
0
GPIO10_VAL
R/W
1
0: GPIO10 outputs 0 when in output mode.
1: GPIO10 outputs 1 when in output mode.
GPIO1 Pin Status Register  Index E2h
Bit
Name
R/W Default
Description
7
GPIO17_IN
R
-
The pin status of GPIO17.
6
GPIO16_IN
R
-
The pin status of GPIO16/LED_VCC/Turbo2#
5
GPIO15_IN
R
-
The pin status of GPIO15/LED_VSB.
4
GPIO14_IN
R
-
The pin status of GPIO14/FWH_DIS/WDTRST#.
3
GPIO13_IN
R
-
The pin status of GPIO13/SPI_MOSI/BEEP.
2
GPIO12_IN
R
-
The pin status of GPIO12/SPI_MISO/FANCTRL1_1.
1
GPIO11_IN
R
-
The pin status of GPIO11/SPI_CS/FANCTRL4.
0
GPIO10_IN
R
-
The pin status of GPIO10/SPI_CLK/FANIN4.
GPIO1 Drive Enable Register  Index E3h
Bit
Name
R/W Default
Description
7
GPIO17_DRV_EN
R/W
0
0: GPIO17 is open drain in output mode.
1: GPIO17 is push pull in output mode.
6
GPIO16_DRV_EN
R/W
0
0: GPIO16 is open drain in output mode.
1: GPIO16 is push pull in output mode.
5
GPIO15_DRV_EN
R/W
0
0: GPIO15 is open drain in output mode.
1: GPIO15 is push pull in output mode.
4
GPIO14_DRV_EN
R/W
0
0: GPIO14 is open drain in output mode.
1: GPIO14 is push pull in output mode.
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3
GPIO13_DRV_EN
R/W
0
0: GPIO13 is open drain in output mode.
1: GPIO13 is push pull in output mode.
2
GPIO12_DRV_EN
R/W
0
0: GPIO12 is open drain in output mode.
1: GPIO12 is push pull in output mode.
1
GPIO11_DRV_EN
R/W
0
0: GPIO11 is open drain in output mode.
1: GPIO11 is push pull in output mode.
0
GPIO10_DRV_EN
R/W
0
0: GPIO10 is open drain in output mode.
1: GPIO10 is push pull in output mode.
GPIO2 Output Enable Register  Index D0h
Bit
Name
R/W Default
Description
7
GPIO27_OE
R/W
0
0: GPIO27 is in input mode.
1: GPIO27 is in output mode.
6
GPIO26_OE
R/W
0
0: GPIO26 is in input mode.
1: GPIO26 is in output mode.
5
GPIO25_OE
R/W
0
0: GPIO25 is in input mode.
1: GPIO25 is in output mode.
4
GPIO24_OE
R/W
0
0: GPIO24 is in input mode.
1: GPIO24 is in output mode.
3
GPIO23_OE
R/W
0
0: GPIO23 is in input mode.
1: GPIO23 is in output mode.
2
GPIO22_OE
R/W
0
0: GPIO22 is in input mode.
1: GPIO22 is in output mode.
1
GPIO21_OE
R/W
0
0: GPIO21 is in input mode.
1: GPIO21 is in output mode.
0
GPIO20_OE
R/W
0
0: GPIO20 is in input mode.
1: GPIO20 is in output mode.
GPIO2 Output Data Register  Index D1h
Bit
Name
R/W Default
Description
7
GPIO27_VAL
R/W
1
0: GPIO27 outputs 0 when in output mode.
1: GPIO27 outputs1 when in output mode.
6
GPIO26_VAL
R/W
1
0: GPIO26 outputs 0 when in output mode.
1: GPIO26 outputs1 when in output mode.
5
GPIO25_VAL
R/W
1
0: GPIO25 outputs 0 when in output mode.
1: GPIO25 outputs 1 when in output mode.
4
GPIO24_VAL
R/W
1
0: GPIO24 outputs 0 when in output mode.
1: GPIO24 outputs 1 when in output mode.
3
GPIO23_VAL
R/W
1
0: GPIO23 outputs 0 when in output mode.
1: GPIO23 outputs 1 when in output mode.
2
GPIO22_VAL
R/W
1
0: GPIO22 outputs 0 when in output mode.
1: GPIO22 outputs 1 when in output mode.
1
GPIO21_VAL
R/W
1
0: GPIO21 outputs 0 when in output mode.
1: GPIO21 outputs 1 when in output mode.
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0
GPIO20_VAL
R/W
1
0: GPIO20 outputs 0 when in output mode.
1: GPIO20 outputs 1 when in output mode.
GPIO2 Pin Status Register  Index D2h
Bit
Name
R/W Default
Description
7
GPIO27_IN
R
-
The pin status of PWSOUT#/GPIO27.
6
GPIO26_IN
R
-
The pin status of PWSIN#/GPIO26.
5
GPIO25_IN
R
-
The pin status of PME#/GPIO25.
4
GPIO24_IN
R
-
The pin status of ATXPG_IN/GPIO24.
3
GPIO23_IN
R
-
The pin status of RSTCON#/GPIO23.
2
GPIO22_IN
R
-
The pin status of PCIRST3#/GPIO22.
1
GPIO21_IN
R
-
The pin status of PCIRST2#/GPIO21.
0
GPIO20_IN
R
-
The pin status of PCIRST1#/GPIO20.
GPIO2 Drive Enable Register  Index D3h
Bit
Name
R/W Default
Description
7
GPIO27_DRV_EN
R/W
0
0: GPIO27 is open drain in output mode.
1: GPIO27 is push pull in output mode.
6
GPIO26_DRV_EN
R/W
0
0: GPIO26 is open drain in output mode.
1: GPIO26 is push pull in output mode.
5
GPIO25_DRV_EN
R/W
0
0: GPIO25 is open drain in output mode.
1: GPIO25 is push pull in output mode.
4
GPIO24_DRV_EN
R/W
0
0: GPIO24 is open drain in output mode.
1: GPIO24 is push pull in output mode.
3
GPIO23_DRV_EN
R/W
0
0: GPIO23 is open drain in output mode.
1: GPIO23 is push pull in output mode.
2
GPIO22_DRV_EN
R/W
0
0: GPIO22 is open drain in output mode.
1: GPIO22 is push pull in output mode.
1
GPIO21_DRV_EN
R/W
0
0: GPIO21 is open drain in output mode.
1: GPIO21 is push pull in output mode.
0
GPIO20_DRV_EN
R/W
0
0: GPIO20 is open drain in output mode.
1: GPIO20 is push pull in output mode.
GPIO3 Output Enable Register  Index C0h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO33_OE
R/W
0
0: GPIO33 is in input mode.
1: GPIO33 is in output mode.
2
GPIO32_OE
R/W
0
0: GPIO32 is in input mode.
1: GPIO32 is in output mode.
1
GPIO31_OE
R/W
0
0: GPIO31 is in input mode.
1: GPIO31 is in output mode.
0
GPIO30_OE
R/W
0
0: GPIO30 is in input mode.
1: GPIO30 is in output mode.
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GPIO3 Output Data Register  Index C1h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO33_VAL
R/W
1
0: GPIO33 outputs 0 when in output mode.
1: GPIO33 outputs 1 when in output mode.
2
GPIO32_VAL
R/W
1
0: GPIO32 outputs 0 when in output mode.
1: GPIO32 outputs 1 when in output mode.
1
GPIO31_VAL
R/W
1
0: GPIO31 outputs 0 when in output mode.
1: GPIO31 outputs 1 when in output mode.
0
GPIO30_VAL
R/W
1
0: GPIO30 outputs 0 when in output mode.
1: GPIO30 outputs 1 when in output mode.
GPIO3 Pin Status Register  Index C2h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO33_IN
R
-
The pin status of RSMRST#/GPIO33.
2
GPIO32_IN
R
-
The pin status of PWROK/GPIO32.
1
GPIO31_IN
R
-
The pin status of PS_ON#/GPIO31.
0
GPIO30_IN
R
-
The pin status of S3#/GPIO30.
GPIO3 Drive Enable Register  Index C3h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO33_DRV_EN
R/W
0
0: GPIO33 is open drain in output mode.
1: GPIO33 is push pull in output mode.
2
GPIO32_DRV_EN
R/W
0
0: GPIO32 is open drain in output mode.
1: GPIO32 is push pull in output mode.
1
GPIO31_DRV_EN
R/W
0
0: GPIO31 is open drain in output mode.
1: GPIO31 is push pull in output mode.
0
GPIO30_DRV_EN
R/W
0
0: GPIO30 is open drain in output mode.
1: GPIO30 is push pull in output mode.
GPIO4 Output Enable Register  Index B0h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO43_OE
R/W
0
0: GPIO43 is in input mode.
1: GPIO43 is in output mode.
2
GPIO42_OE
R/W
0
0: GPIO42 is in input mode.
1: GPIO42 is in output mode.
1
GPIO41_OE
R/W
0
0: GPIO41 is in input mode.
1: GPIO41 is in output mode.
0
GPIO40_OE
R/W
0
0: GPIO40 is in input mode.
1: GPIO40 is in output mode.
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GPIO4 Output Data Register  Index B1h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO43_VAL
R/W
1
0: GPIO43 outputs 0 when in output mode.
1: GPIO43 outputs 1 when in output mode.
2
GPIO42_VAL
R/W
1
0: GPIO42 outputs 0 when in output mode.
1: GPIO42 outputs 1 when in output mode.
1
GPIO41_VAL
R/W
1
0: GPIO41 outputs 0 when in output mode.
1: GPIO41 outputs 1 when in output mode.
0
GPIO40_VAL
R/W
1
0: GPIO40 outputs 0 when in output mode.
1: GPIO40 outputs 1 when in output mode.
GPIO4 Pin Status Register  Index B2h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO43_IN
R
-
The pin status of IRRX/GPIO43
2
GPIO42_IN
R
-
The pin status of IRTX/GPIO42.
1
GPIO41_IN
R
-
The pin status of FANCTRL3/GPIO41.
0
GPIO40_IN
R
-
The pin status of FANIN3/GPIO40.
GPIO4 Drive Enable Register  Index B3h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved.
3
GPIO43_DRV_EN
R/W
0
0: GPIO43 is open drain in output mode.
1: GPIO43 is push-pull in output mode.
2
GPIO42_DRV_EN
R/W
0
0: GPIO42 is open drain in output mode.
1: GPIO42 is push-pull in output mode.
1
GPIO41_DRV_EN
R/W
0
0: GPIO41 is open drain in output mode.
1: GPIO41 is push-pull in output mode.
0
GPIO40_DRV_EN
R/W
0
0: GPIO40 is open drain in output mode.
1: GPIO40 is push-pull in output mode.
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8.9
VID Registers (CR07)
8.9.1 VID Configuration Registers
VID Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
VID_EN
R/W Default
Description
-
0
Reserved
R/W
0
0: disable VID.
1: enable VID.
Base Address High Register  Index 60h
Bit
Name
7-0 BASE_ADDR_HI
R/W Default
R/W
00h
Description
The MSB of VID base address.
Base Address Low Register  Index 61h
Bit
Name
7-0 BASE_ADDR_LO
R/W Default
R/W
00h
Description
The LSB of VID base address.
8.9.2 Device Registers
8.9.2.1
Configuration Register  Index 00h ( * cleared by slotocc_n and watch dog timeout)
Bit
Name
7
WDOUT_EN
R/W
0
6*
GP_OTF_EN1
R/W
0
5*
GP_SWITCH1_EN
R/W
0
4*
GP_SWITCH0_EN
R/W
0
3*
GP_OTF_EN0
R/W
0
2*
OTF_EN
R/W
0
R/W Default
Description
If this bit is set to 1 and watchdog timeout event occurs, RSTOUT# output
is enabled.
If this bit is set to 1 and OTF_EN is also set to 1, users can control vid
on-the-fly by GPIO16/LED_VCC/Turbo2#.
If this bit is set to 1, users can select “SWITCH_SEL” by controlling
GPIO16/LED_VCC/Turbo2#.
If this bit is set to 1, users can select “SWITCH_SEL” by controlling
GPIO07/Turbo1#.
If this bit is set to 1 and OTF_EN is also set to 1, users can control vid
on-the-fly by GPIO07/Turbo1#.
This bit is used to enable vid on-the-fly function.
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0: Intel VRM10.0
1:0
VRM_SEL
R/W
0
1: Intel VRM11.0
2: AMD VRM
3: Reserved
8.9.2.2
VID Offset Register 0  Index 01h
Bit
Name
7:6
Reserved
5-0
VID_OFFSET0
R/W Default
Description
R
-
Reserved
R/W
0
VID offset. VID_OFFSET[5] is sign bit.
8.9.2.3
VID Manual Register  Index 02h
Bit
Name
R/W Default
Description
7
MANUAL_MODE
R/W
0
If this bit is set to 1 and OTF_EN is 0, VIDOUT will be VID_MANUAL
6
KEY_OK
R
-
This bit is 1 represents that the serial key is entered correctly.
R/W
0
Manually assigned VIDOUT value
5-0
VID_MANUAL
8.9.2.4
Serial Key Data Register  Index 03h
Bit
Name
R/W Default
0
7-0
KEY_DATA
Description
Write serial data to this register correctly, the KEY_OK bit will be set to 1.
Hence, users are able to write key protected registers. The sequence to
R/W
enable KEY_OK is 0x32, 0x5D, 0x42, 0xAC. When KEY_OK is set, write
this register 0x35 will clear KEY_OK.
8.9.2.5
VIDIN Register  Index 04h
Bit
Name
( * cleared by slotocc_n and watch dog timeout)
R/W Default
Description
1: VIDIN will be pin status of P_VIDIN
7*
VIDIN_MODE
R/W
1
0: P_VIDIN value will be latched when this bit is set to 0 (from 1). At the
same time, P_VIDIN will turn to output mode and VID_MANUAL will be
output from P_VIDIN.
6
Reserved
R
0
Reserved
VIDIN
R
-
The value of this register depends on the VIDIN_MODE register:
VIDIN_MODE is 1: the register indicates the VID reading from CPU (the
pin status of VID_IN[5:0]).
5:0
VIDIN_MODE is 0: the register latches the value of VID_IN[5:0] when
VIDIN_MODE changed from 1 to 0.
8.9.2.6
Watchdog Timer Configuration Register 1 Index 05h
Bit
Name
7
Reserved
R/W Default
R
0
Description
Reserved
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If watchdog timeout event occurs, this bit will be set to 1. Write a 1 to this
6
WDTMOUT_STS
R/W
0
5
WD_EN
R/W
0
If this bit is set to 1, the counting of watchdog time is enabled.
4
WD_PULSE
R/W
0
Select output mode (0: level, 1: pulse) of RSTOUT# by setting this bit.
3
WD_UNIT
R/W
0
Select time unit (0: 1sec, 1: 60 sec) of watchdog timer by setting this bit.
2
WD_HACTIVE
R/W
0
bit will clear it to 0.
Select output polarity of RSTOUT# (1: high active, 0: low active) by setting
this bit.
Select output pulse width of RSTOUT#
1:0
WD_PSWIDTH
R/W
0
0: 1 ms
1: 25 ms
2: 125 ms
3: 5 sec
8.9.2.7
Watchdog Timer Configuration Register 2  Index 06h
Bit
Name
7:0
WD_TIME
R/W Default
R/W
0
Description
Time of watchdog timer
8.9.2.8
Output Voltage Control Register 1  Index 07h
Bit
Name
7*
SWITCH_EN
R/W
0
6
OVER_VOL_EN
R/W
1
If this bit is 1, AVOUT function is enabled.
5:4
Reserved
R/W
0
Reserved
3:0*
SWITCH_SEL0
R/W
7
SWITCH_SEL0 is used to control AVOUT according to AVIN.
R/W Default
( * cleared by slotocc_n and watch dog timeout)
Description
0: If OVER_VOL_EN is 0, AVOUT equals to AVIN.
1: If OVER_VOL_EN is 1, AVOUT is controlled by SWITCH_SEL.
8.9.2.9
Output Voltage Control Register 2  Index 08h
Bit
Name
7:4*
SWITCH_SEL2
R/W
7
SWITCH_SEL2 is used to control AVOUT according to AVIN.
3:0*
SWITCH_SEL1
R/W
7
SWITCH_SEL1 is used to control AVOUT according to AVIN.
R/W Default
( * cleared by slotocc_n and watch dog timeout)
Description
8.9.2.10
Output Voltage Control Register 3  Index 09h
Bit
Name
7:4*
Reserved
R
0
Reserved
3:0*
SWITCH_SEL3
R/W
7
SWITCH_SEL3 is used to control AVOUT according to AVIN.
R/W Default
Description
8.9.2.11
P_VIDIN Output Mode Control Register  Index 0Ah ( * cleared by slotocc_n and watch dog timeout)
Bit
Name
7:6
Reserved
R/W Default
R/W
0
Description
Reserved
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If VID_IN_MODE is set to 0, P_VIDIN will be output and the output value is
5:0*
VIDIN_OD
R/W
3Fh
VID_MANUAL. VIDIN_OD can individually control the P_VIDIN output
mode (1: open drain; 0: push pull)
8.9.2.12
VID Offset Register 1  Index 0Bh
Bit
Name
7:6
Reserved
5-0
VID_OFFSET1
R/W Default
Description
R
-
Reserved
R/W
0
VID offset. VID_OFFSET[5] is sign bit.
8.9.2.13
VID Offset Register 2  Index 0Ch
Bit
Name
7:6
Reserved
5-0
VID_OFFSET2
R/W Default
Description
R
-
Reserved
R/W
0
VID offset. VID_OFFSET[5] is sign bit.
8.9.2.14
VID Offset Register 3  Index 0Ch
Bit
Name
7:6
Reserved
5-0
VID_OFFSET3
R/W Default
Description
R
-
Reserved
R/W
0
VID offset. VID_OFFSET[5] is sign bit.
8.9.2.15
Turbo Invert Register  Index 0Eh
Bit
Name
7:4
Reserved
R/W Default
Description
R
-
Reserved
3
GP_SWITCH_INV1
R/W
1
This bit can invert Turbo2 signals when GP_SWITCH1_EN is set to 1.
2
GP_SWITCH_INV0
R/W
1
This bit can invert Turbo1 signals when GP_SWITCH0_EN is set to 1.
1
GP_OTF_INV1
R/W
1
This bit can invert Turbo2 signals when GP_OTF_EN1 is set to 1.
0
GP_OTF_INV0
R/W
1
This bit can invert Turbo2 signals when GP_OTF_EN0 is set to 1.
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8.10 SPI Registers (CR08)
8.10.1 Configuration Register
SPI Control Register  Index F0h
Bit
Name
7-6 Reserved
5
SPTIE
R/W Default
Description
-
-
Reserved.
R/W
0
SPI interrupt enable. Set to 1, SPIE interrupt enabled, set to 0 spie interrupt
disabled.
4
MSTR
R/W
1
Master mode select. Set to 1, SPI function is master mode; set to 0 is disable
SPI function
3
CPOL
R/W
0
Clock polarity this bit selects inverted or non-inverted SPI clock. Set to 1, active
low clock selected; SCK idles high. Set to 0, active high clock selected; SCK
idles low.
2
CPHA
R/W
0
Clock phase. This bit is used to shift the SCK serial clock. Set to 1, the first
SCK edge is issued at the beginning of the transfer operation. Set to 0, the first
SCK edge is issued one-half cycle into the transfer operation.
1
Reserved
0
LSBFE
-
0
Reserved
R/W
0
This bit control data shift from lsb or msb. Set to 1, data is transferred from lsb
to msb. Set to 0, data is transferred from msb to lsb.
SPI Timeout Register  Index F1h
Bit
Name
7-0 TIMER_VAL
R/W Default
R/W
Description
8’h04 The time in second to assert FWH_DIS signal when SPI in used as backup
BIOS.
SPI Baud Rate Divisor Register  Index F2h
Bit
Name
7-3 Reserved
R/W Default
-
0
Description
Reserved
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2-0 Baud_val
R/W
1
This register decides to SCK frequency. Baud rate divisor equation is
33MHz/2*(BAUD_VAL).
00: 33MHz.
01: 16.7MHz.
SPI Status Register  Index F3h
Bit
7
Name
SPIE
R/W Default
R/W
0
Description
SPI interrupt status. When SPI is transferred or received data from device
finish, this bit will be set. Write 1 to clear this bit.
6
FWH_DIS
5
SPE
4
SPI0_TIMER_DIS
3
SPTEF
R/W
-
When SPI is used as backup BIOS, this bit will set when time in second
reaches the value programmed in TIMER_VAL (CRF1). Write one to clear this
register.
When SPI is used as primary BIOS, this register will always be 1.
R
-
This bit reflects the SPI_EN register. (which will be 1 when SPI is enabled.)
R/W
-
When SPI is used as primary BIOS, it will also have backup function as used in
backup BIOS. The bit will set to 1 when the time in second reaches the value
programmed in TIMER_VAL (CRF1). That is the first SPI could not function
well. Then a reset signal will asserted and reboot the system with the second
SPI. (I could be another SPI with chip-selected by FWH_DIS or another 4Mbits
of an 8Mbits SPI. The SPI_CS1_EN (CR2D[4]) determines the method). Write
one to clear this bit.
R
0
SPI operation status. When SPI is transferred or received data from device,
this bit will be set 1, Clear by SPI operation finish.
2-0 Reserved
-
-
Reserved
SPI High Byte Data Register  Index F4h
Bit
Name
7-0 H_DATA
R/W Default
R
0
Description
When SPI is received 16 bits data from device. This register saves high byte
data.
SPI command data Register  Index F5h
Bit
Name
7-0 CMD_DATA
R/W Default
R/W
0
Description
This register provides command value for flash command.
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SPI chip select Register  Index F6h
Bit
Name
7-4 Reserved
R/W Default
Description
-
-
Reserved
3
CS3
R/W
0
Chip select 3. To select device 3
2
CS2
R/W
0
Chip select 2. To select device 2
1
CS1
R/W
0
Chip select 1. To select device 1
0
CS0
R/W
0
Chip select 0. To select device 0
SPI memory mapping Register  Index F7h
Bit
Name
R/W Default
Description
7-3 Reserved
-
0
Reserved
2-0 Mem_map
R/W
-
This register decides memory size.
3’b000: one of the memory sizes is 512k bytes.
3’b001: one of the memory sizes is 1024k bytes.
3’b100: one of the memory sizes is 2048k bytes.
3’b011: one of the memory sizes is 4096k bytes.
3’b100: one of the memory sizes if 8092k bytes.
The default value is power on strap by SOUT2.
Pull down to select 4096k bytes size, else select 512k bytes size.
SPI operate Register  Index F8h
Bit
7
Name
TYPE
R/W Default
R/W
0
Description
This bit decide flash continuous programming mode. Set to 1, if programming
continuous mode is same as the SST flash. Set to 0 if programming continuous
mode is same as the ATMEL flash
6
IO_SPI
R/W
0
This bit control SPI function transfer 8 bit command to device. Clear 0 by
operation finish.
5
RDSR
R/W
0
This bit control SPI function read status from to device. Clear 0 by operation
finish.
4
WRSR
R/W
0
This bit control SPI function write status to device. Clear 0 by operation finish.
3
SECTOR_ERASE
R/W
0
This bit control SPI function sector erase device. Clear 0 by operation finish.
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2
READ_ID
R/W
0
This bit control SPI function read id from device. Clear 0 by operation finish.
1
PROG
R/W
0
This bit control SPI function program data to device or set to 1 when memory
cycle for LPC interface program flash. Clear 0 by operation finish.
0
READ
R/W
0
This bit control SPI function read data from device or set to 1 when memory
cycle for LPC interface read flash. Clear 0 by operation finish.
SPI Low Byte Data Register  Index FAh
Bit
Name
7-0 L_DATA
R/W Default
R
0
Description
When SPI is received 16 bits or 8 bits data from device. This register saves low
byte data.
SPI address high byte Register  Index FBh
Bit
Name
7-0 Addr_H_byte
R/W Default
R/W
0
Description
This register provides high byte address for sector erase, program, read
operation.
SPI address medium byte Register  Index FCh
Bit
Name
7-0 Addr_M_byte
R/W Default
R/W
0
Description
This register provides medium byte address for sector erase, program, read
operation.
SPI address low byte Register  Index FDh
Bit
Name
7-0 Addr_L_byte
R/W Default
R/W
0
Description
This register provides low byte address for sector erase, program, read
operation.
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SPI program byte Register  Index FEh
Bit
Name
7-0 PORG_BYTE
R/W Default
R/W
0
Description
This register provides number to program flash for continuous mode.
SPI write data Register  Index FFh
Bit
Name
7-0 WR_dat
R/W Default
R/W
0
Description
This register provides data to write flash for program, write status function.
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8.11 PME and ACPI Registers (CR0A)
8.11.1 Configuration Register
Device Enable Register  Index 30h
Bit
Name
7-1 Reserved
0
PME_EN
R/W Default
Description
-
-
Reserved
R/W
0
0: disable PME.
1: enable PME.
PME Event Enable Register  Index F0h
Bit
Name
7
Reserved
6
R/W Default
Description
-
-
Reserved
MO_PME_EN
R/W
0
Mouse PME event enable.
0: disable mouse PME event.
1: enable mouse PME event.
5
KB_PME_EN
R/W
0
Keyboard PME event enable.
0: disable keyboard PME event.
1: enable keyboard PME event.
4
HM_PME_EN
R/W
0
Hardware monitor PME event enable.
0: disable hardware monitor PME event.
1: enable hardware monitor PME event.
3
PRT_PME_EN
R/W
0
Parallel port PME event enable.
0: disable parallel port PME event.
1: enable parallel port PME event.
2
UR2_PME_EN
R/W
0
UART 2 PME event enable.
0: disable UART 2 PME event.
1: enable UART 2 PME event.
1
UR1_PME_EN
R/W
0
UART 1 PME event enable.
0: disable UART 1 PME event.
1: enable UART 1 PME event.
0
FDC_PME_EN
R/W
0
FDC PME event enable.
0: disable FDC PME event.
1: enable FDC PME event.
PME Event Status Register  Index F1h
Bit
7
Name
Reserved
R/W Default
-
-
Description
Reserved
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6
MO_PME_ST
R/W
0
Mouse PME event status.
0: Mouse has no PME event.
1: Mouse has a PME event to assert. Write 1 to clear to be ready for next PME
event.
5
KB_PME_ST
R/W
0
Keyboard PME event status.
0: Keyboard has no PME event.
1: Keyboard has a PME event to assert. Write 1 to clear to be ready for next
PME event.
4
HM_PME_ST
R/W
0
Hardware monitor PME event status.
0: Hardware monitor has no PME event.
1: Hardware monitor has a PME event to assert. Write 1 to clear to be ready for
next PME event.
3
PRT_PME_ST
R/W
0
Parallel port PME event status.
0: Parallel port has no PME event.
1: Parallel port has a PME event to assert. Write 1 to clear to be ready for next
PME event.
2
UR2_PME_ST
R/W
0
UART 2 PME event status.
0: UART 2 has no PME event.
1: UART 2 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
1
UR1_PME_ST
R/W
0
UART 1 PME event status.
0: UART 1 has no PME event.
1: UART 1 has a PME event to assert. Write 1 to clear to be ready for next
PME event.
0
FDC_PME_ST
R/W
1
FDC PME event status.
0: FDC has no PME event.
1: FDC has a PME event to assert. Write 1 to clear to be ready for next PME
event.
ACPI Control Register  Index F4h
Bit
Name
R/W Default
Description
7
Reserved
R/W
0
Dummy registers.
6
SPI_RST_EN
R/W
0
Set one to enable the reset signal from SPI via the PWROK or PCIRST#. (SPI
as backup BIOS will assert a reset signal when FWH doesn’t response in 4
seconds)
5
KEY_SEL_ADD
R/W
0
Set this bit one and KEY_SEL (CR2D[2:1]) 2’b00 will select windows 98
wakeup key as keyboard wakeup key.
4
EN_KBWAKEUP
R/W
0
Set one to enable keyboard wakeup event asserted via PWSOUT#.
3
EN_MOWAKEUP
R/W
0
Set one to enable mouse wakeup event asserted via PWSOUT#.
R/W
11
The ACPI Control the PSON_N to always on or always off or keep last state
00 : keep last state
10 : Always on
01 : Reserved (always on)
11: Always off
R/W
0
When VSB 3V comes, it will set to 1, and write 1 to clear it
2-1 PWRCTRL
0
VSB_PWR_LOSS
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ACPI Control Register  Index F5h
Bit
Name
7
SOFT_RST_ACPI
6
Reserved
5
RSTCON_EN
4-3 DELAY
R/W Default
Description
R/W
0
Software Reset to ACPI (auto clear after reset)
-
-
Reserved
R/W
0
0: Enable RSTCON# output via PWROK.
1: Enable RSTCON# output via PCIRST#.
R/W
11
The PWROK delay timing from VDD3VOK by followed setting
00 : 100ms
01 : 200ms
10 : 300ms
11 : 400ms
2
VINDB_EN
R/W
1
Enable the PCIRSTIN_N and ATXPWGD debounce
1
PCIRST_DB_EN
R/W
0
Enable the LRESET_N de-bounce.
0
Reserved
-
-
Reserved.
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9. Electron Characteristic
9.1
Absolute Maximum Ratings
PARAMETER
Power Supply Voltage
Input Voltage
Operating Temperature
Storage Temperature
RATING
-0.5 to 5.5
-0.5 to VDD+0.5
0 to 70
-55 to 150
UNIT
V
V
°C
°C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may
adversely affect the life and reliability of the device
9.2
DC Characteristics
(TA = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V )
Parameter
Conditions
o
Temperature Error, Remote Diode 60 C < TD < 145 oC, VCC = 3.0V to 3.6V
0 oC <TD < 60oC 100 oC <TD < 145oC
Supply Voltage range
Average operating supply current
Standby supply current
Resolution
Power on reset threshold
Diode source current
High Level
Low Level
9.3
MIN
3.0
TYP
±1
±1
3.3
10
5
1
2.2
95
10
MAX
±3
±3
3.6
2.4
Unit
o
C
V
mA
uA
o
C
V
uA
uA
DC Characteristics Continued
(Ta = 0° C to 70° C, VDD = 3.3V ± 10%, VSS = 0V)
PARAMETER
SYM. MIN. TYP.
MAX.
UNIT
CONDITIONS
I/OD12ts5v-TTL level bi-directional pin with schmitt trigger, Open-drain output with12 mA sink
capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+12
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0V
I/OD16t5v-TTL level bi-directional pin, Open-drain output with16 mA sink capability, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Output Low Current
IOL
+16
mA
VOL = 0.4V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0V
I/OOD12t-TTL level bi-directional pin, Output pin with 12mA source-sink capability, and can
programming to open-drain function.
Input Low Threshold Voltage
Vt0.8
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
2.0
V
VDD = 3.3 V
Output Low Current
IOL
-12
-9
mA
VOL = 0.4 V
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Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0V
I/O12t- TTL level bi-directional pin, Output pin with 12mA source-sink capability.
Input Low Threshold Voltage
Vt0.6
V
VDD = 3.3 V
Input High Threshold Voltage
Vt+
0.9
V
VDD = 3.3 V
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
Input High Leakage
ILIH
+1
µA
VIN = 1.2V
Input Low Leakage
ILIL
-1
µA
VIN = 0V
INts - TTL level input pin with schmitt trigger
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0 V
INt5v - TTL level input pin with 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0 V
INts5v - TTL level input pin with schmitt trigger, 5V tolerance.
Input Low Voltage
VIL
0.8
V
Input High Voltage
VIH
2.0
V
Input High Leakage
ILIH
+1
µA
VIN = VDD
Input Low Leakage
ILIL
-1
µA
VIN = 0 V
OD12-Open-drain output with12 mA sink capability.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD12-5v-Open-drain output with12 mA sink capability, 5V tolerance.
Output Low Current
IOL
-12
mA
VOL = 0.4V
OD24-Open-drain output with 24 mA sink capability.
Output Low Current
IOL
-24
mA
VOL = 0.4V
OD16-u10-5v-Open-drain output with 16 mA sink capability, pull-up 10k ohms, 5V tolerance.
Output Low Current
IOL
-16
mA
VOL = 0.4V
O8- Output pin with 8 mA source-sink capability.
Output High Current
IOH
+6
+8
mA
VOH = 2.4V
O8-u47-5v- Output pin with 8 mA source-sink capability, pull-up 47k ohms, 5V tolerance.
Output High Current
IOH
+6
+8
mA
VOH = 2.4V
O12- Output pin with 12 mA source-sink capability.
Output High Current
IOH
+9
+12
mA
VOH = 2.4V
O30- Output pin with 30 mA source-sink capability.
Output High Current
IOH
+26
+30
mA
VOH = 2.4V
10. Ordering Information
Part Number
Package Type
Production Flow
F71883FG
128-PQFP Green Package
Commercial, 0°C to +70°C
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11. Package Dimensions
Feature Integration Technology Inc.
Headquarters
Taipei Office
3F-7, No 36, Tai Yuan St.,
Bldg. K4, 7F, No.700, Chung Cheng Rd.,
Chupei City, Hsinchu, Taiwan 302, R.O.C.
Chungho City, Taipei, Taiwan 235, R.O.C.
TEL : 886-3-5600168
TEL : 866-2-8227-8027
FAX : 886-3-5600166
FAX : 866-2-8227-8037
www: http://www.fintek.com.tw
Please note that all datasheet and specifications are subject to change without notice. All the trade
marks of products and companies mentioned in this datasheet belong to their respective owner
-123-
May, 2008
V0.27P
F71883
12. Application Circuit
(GND close to IC)
VCC3V
VBAT
VSB3V
RSMRST#
COPEN#
DD3+
D2+
D1+
VREF
VIN6
VIN5
VIN4
VIN3
VIN2
VIN1
SLCT
PE
BUSY
GPIO
R1
R2
R4
R3
R5
1K
1K
1K
1K
1K
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
WPT#
INDEX#
TRK0#
RDATA#
DSKCHG#
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
BUSY
PE
SLCT
VCC
VIN1(Vcore)
VIN2
VIN3
VIN4
VIN5
VIN6
VREF
D1+(CPU)
D2+
D3+(System)
AGND(D-)
COPEN#
VBAT
RSMRST#/GPIO33
PWOK/GPIO32
PS_ON#/GPIO31
S3#/GPIO30
PWSOUT#/GPIO27
PWSIN#/GPIO26
PME#/GPIO25
ATXPG_IN/GPIO24
RSTCON#/GPIO23
PCIRST3#/GPIO22
PCIRST2#/GPIO21
PCIRST1#/GPIO20
GND
MCLK
MDATA
KCLK
KDATA
VSB
OVT#
GPIO17/SEGA
GPIO16/LED_VCC
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
GND
DCD1#
RI1#
CTS1#
DTR1#
RTS1#/VIDOUT_TRAP
DSR1#
SOUT1/Conf ig4E_2E
SIN1
DCD2#/SEGG
RI2#/SEGF
CTS2#/H#
F71883F
1
3
5
7
9
11
13
15
17
19
21
23
25
27
29
31
33
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
DENSEL#
2
4
6
8
10
12
14
16
18
20
22
24
26
28
30
32
34
INDEX#
MOA#
DRVA#
DIR#
STEP#
WDATA#
WGATE#
TRK0#
WPT#
RDATA#
HDSEL#
DSKCHG#
HEADER 17X2
FLOPPY CONN.
GPIO15/LED_VSB
GPIO14/FWH_DIS/WDTRST#
GPIO13/SPI_MOSI/BEEP
GPIO12/SPI_MISO/FANCTL1_1
GPIO11/SPI_CS/FANCTL4
GPIO10/SPI_CLK/FANIN4
VSO
VSI
GPIO07/T1#
SLOTOCC#/GPIO06
VIDOUT5/GPIO05
VIDOUT4/GPIO04
VIDOUT3/GPIO03
VIDOUT2/GPIO02
VIDOUT1/GPIO01
VIDOUT0/GPIO00
GND
VIDIN5/OUT5
VIDIN4/OUT4
VIDIN3/OUT3
VIDIN2/OUT2
VIDIN1/OUT1
VIDIN0/OUT0
GA20
KBRST#
CLKIN
DTR2#/RTS_DRV/SEGD
RTS2#/PWM_DC/SEGC
DSR2#/L#
VCC
SOUT2/SPI_TRAP/SEGB
SIN2/SEGE
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
INDEX#
WPT#
DSKCHG#
GND
FANIN1
FANCTL1
FANIN2
FANCTL2
FANIN3/GPIO40
FANCTL3/GPIO41
IRTX/GPIO42
IRRX/GPIO43
LRESET#
LDRQ#
SERIRQ
LFRAM#
LAD0
LAD1
LAD2
LAD3
VCC
PCICLK
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
J1
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
LED_VSB
FWH_DIS
MOSI
MISO
SPI_CS0#
SCK
VSO
VSI
TURBO1#
SLOTOCC#
SOUT2
SOUT1
RTS1
RTS2
DTR2
VIDOUT5
VIDOUT4
VIDOUT3
VIDOUT2
VIDOUT1
VIDOUT0
GA20
KBRST#
CLK_24/48M
R7
1K
VID5
VID4
VID3
VID2
VID1
VID0
R8
1K
R9
1K
R10
1K
R11
1K
POWER TRIP R
R8
R9
OFF: PWM FAN
ON: Linear FAN
OFF: PIN49-54=VID_OUT
ON: PIN49-54=GPIO
PIN42-47=VIDIN
PIN42-47=VIDIN/OUT
R10
OFF: 4E
ON: 2E
R7&R11 OFF: SPI_DISABLE
ON: SPI_ENABLE
VCC3V
VCC3V
C3
1
0.1U
0.1UF
0.1U
1
1
C2
VBAT
C4
C5
0.1U
2
0.1U
VSB3V
2
C1
2
1
VCC3V VCC3V VCC3V
IRRX
IRTX
FANCTL3
FANIN3
FANCTL2
FANIN2
FANCTL1
FANIN1
2
PCICLK
LAD3
LAD2
LAD1
LAD0
LFRAME#
SERIRQ
LDRQ#
LRESET#
DENSEL#
MOA#
DRVA#
WDATA#
DIR#
STEP#
HDSEL#
WGATE#
RDATA#
TRK0#
INDEX#
WPT#
DSKCHG#
2
DTR2#
RTS2#
DSR2#
SOUT2
SIN2
1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
DCD1#
RI1#
CTS1#
DTR1#
RTS1#
DSR1#
SOUT1
SIN1
DCD2#
RI2#
CTS2#
VCC5V
LED_VCC
U1
ACK#
SLIN#
INIT#
ERR#
AFD#
STB#
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
PWOK
PSON#
S3#
PWSOUT#
PWSIN#
PME#
ATXPG_IN
RSTCON#
PCIRST3#
PCIRST2#
PCIRST1#
MCLK
MDAT
KCLK
KDAT
OVT#
Title
Feature Integration Technology Inc.
(Place capacitor close to IC)
Size
B
Date:
Document Number
F71883F&FDD
Thursday , October 20, 2005
Rev
0.1
Sheet
1
of
6
Document Number
F71883 & FDD
124
May, 2008
V.27P
F71883
RN6
RN7
RN8
D7
1
VCC5V
1N5819
FOR LEKAGE TO POWER
2
4
6
8
2
4
6
8
2
4
6
8
2
4
6
8
2
20
RN9
VCC5V
1
3
5
7
1
3
5
7
1
3
5
7
1
3
5
7
R72
2.7K
RN10
1
3
5
7
STB#
AFD#
INIT#
SLIN#
2
4
6
8
1
14
2
15
3
16
4
17
5
18
6
19
7
20
8
21
9
22
10
23
11
24
12
25
13
33-8P4R
RN11
1
3
5
7
PD0
PD1
PD2
PD3
2
4
6
8
33-8P4R
RN12
1
3
5
7
PD4
PD5
PD6
PD7
2
4
6
8
33-8P4R
ERR#
ACK#
BUSY
PE
SLCT
19
18
17
16
15
14
13
12
RI1#
CTS1#
DSR1#
RTS1#
DTR1#
SIN1
SOUT1
DCD1#
2.7K-8P4R 2.7K-8P4R 2.7K-8P4R 2.7K-8P4R
J2
11
C25
C26
C27
C28
C29
C30
180p
180p
180p
180p
180p
180p
180pC32
180p
VCC
+12V
RY1
RY2
RY3
DA1
DA2
RY4
DA3
RY5
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
-12V
UART
20
VCC5V
19
18
17
16
15
14
13
12
RI2#
CTS2#
DSR2#
RTS2#
DTR2#
SIN2
SOUT2
DCD2#
11
DB25
(FEMALE)
C24
U4
1
+12V
GND
RIN1
DTRN1
CTSN1
SOUTN1
RTSN1
SINN1
DSRN1
DCDN1
RIN1
CTSN1
DSRN1
RTSN1
DTRN1
SINN1
SOUTN1
DCDN1
2
3
4
5
6
7
8
9
10
P1
5
9
4
8
3
7
2
6
1
UART DB9
-12V
1 PORT INTERFACE
U5
VCC
+12V
RY 1
RY 2
RY 3
DA1
DA2
RY 4
DA3
RY 5
RA1
RA2
RA3
DY 1
DY 2
RA4
DY 3
RA9
GND
-12V
UART
1
+12V
GND
RIN2
DTRN2
CTSN2
SOUTN2
RTSN2
SINN2
DSRN2
DCDN2
RIN2
CTSN2
DSRN2
RTSN2
DTRN2
SINN2
SOUTN2
DCDN2
2
3
4
5
6
7
8
9
10
5
9
4
8
3
7
2
6
1
UART DB9
-12V
2
P2
PORT INTERFACE
C31
C33
C34
C35
C36
C37
C38
180p
C39
C40 180p
180p
180p
180p
180p
180p
180p
180p
VCC5V/3V
PARALLEL PORT INTERFACE
JP7
1
2
3
4
5
VSB5V
IRTX
J3
IRRX
1
2
3
HEADER 5
C41
F1
CON3
VCC5V
R92
4.7K
1
2
3
FUSE
R93
4.7K
F2
M-DIN_6-R JS1
6
5
4
R94
4.7K
MDAT
6
5
4
L2
KDAT
FB
IR INTERFACE
FB
L3
MCLK
1
2
3
FUSE
R95
4.7K
L1
0.1U
M-DIN_6-R JS2
L4
KCLK
FB
FB
C45
C43
C44
C46
C48
C47
100P
100P
0.1U
100P
100P
0.1U
PS2 MOUSE INTERFACE
Title
Feature Integration Technology Inc.
Size
B
PS2 KEYBOARD INTERFACE
Document Number
Printer &UART
Rev
0.1
Monday , July 11, 2005
Date:
2
Sheet
of
4
VBAT
R60
2M
COPEN# 2
COPEN#
SW1
1
C23
1000P
CASE OPEN CIRCUIT
D1+
D1+
C20
VIN1
100K
VIN2
D2+
VIN2
C21
R58
47K
R57
100K
VIN3
VIN3
D3+
R63
200K
R59
100K
VIN4
VIN4
VCC5V
+12V
R62
47K
R64
U6
1
2
3
4
SPI_CS0#
MISO
Q12
PNP
3906
3300P
for
SYSTEM
VCC3V
S#
Q
W#
VSS
VCC
HOLD#
C
D
8
7
6
5
R73
4.7K
R107
4.7K
SCK
MOSI
SPI FLASH MEMORY
SPI
DIODE SENSING CIRCUIT
VIN5
VIN5
20K
10K
VCC3V
R74
4.7K
D-
VREF
R65
for
SYSTEM
D3+
C22
200K
VCC3V
Q11
PNP
3906
3300P
D-
VCHIPSET
R61
from CPU
D-
D2+
VIN6
VIN6
VCC1.5V
R66
10K 1%
R69
10K 1%
VREF
D3+
RT2
R71
10K 1%
RT3
(for system)
10K 1%
THERMISTOR
D2+
VOLTAGE SENSING.
10K 1%
THERMISTOR
D1+
VREF
RT1
T
R56
VRAM
3300P
D-
VIN1
T
10K
(for system)
10K 1%
T
R55
VCORE
D+
THERMISTOR
(for system)
The best voltage input level is about 1V.
THERMISTOR SENSING CIRCUIT
Temperature Sensing
U7
DCD2#
GPIO17#
RI2#
DSR2#
R111 100
1
2
3
4
5
SEGG
NC
SEGA
SEGF
L#
H#
SEGB
SEGC
SEGE
SEGD
10
9
8
7
6
R112 100
CTS2#
SOUT2
RTS2#
SIN2
DTR2#
Dual Digit Display
80 PORT
Title
Feature Integration Technology Inc
Size
B
Date:
125
Document Number
Hardware Monitor, SPI Flash
Monday , September 04, 2006
Rev
0.17
Sheet
3
of
7
May, 2008
V.27P
F71883
+12V
Q2
PNP
4.7K
R114
4.7K
R23
FANCTL1
330
D1
1N4148
4 HEADER
C8
Q3
+
MOSFET N
2N7002 47U
8
R20
VCC3V
12V
4.7K
R21
4.7K
R24
MISO
VCC5V
0
27K
FANIN1
0
R32
10K
U2A
NDS0605/SOT
Q4
D2
1N4148
1
-
C9
0.1U
R22
4.7K
LM358
JP2
R26 10K
4FANCTL
R31
+
R25
10K
JP1
R30
2
FANCTL1
4FANCTL
4
3
2
1
3
4
R19
C10
47u
R27 27K
3
2
1
0.1u R29
10K
CON3
R28
3.9K
FANIN1
C11
DC FAN Control with OP 1
(4 PIN FAN Control)
PWM FAN 1
SPEED CONTROL
12V
The C10 is reserved for FAN noise dis-bounce.
+12V
R33
4.7K
R34
4.7K
8
VCC3V
Q5
PNP
FANCTL2
C12
Q7
+
MOSFET N
2N7002 47U
330
R35
4.7K
JP3
FANCTL2
R38
3
2
1
27K
+
U2B
NDS0605/SOT
D4
1N4148
R36
4.7K
LM358
JP4
R40 10K
R39
10K
C13
47u
R41 27K
3
2
1
C15
FANIN2
0.1u R43
10K
CON3
R42
3.9K
SPEED CONTROL
Q6
7
-
FANIN2
C14
0.1U
HEADER 3
PWM FAN 2
6
4
R115
4.7K
R37
5
D3
1N4148
DC FAN Control with OP 2
The C13 is reserved for FAN noise dis-bounce.
12V
R45
4.7K
Q8
PNP
D5
1N4148
R116
4.7K
FANCTL3
R49
C16
Q10
+
MOSFET N
2N7002 47U
330
3
R46
4.7K
JP5
R48
3
2
1
2
FANCTL3
+
27K
NDS0605/SOT
U3A
Q9
D6
1N4148
1
4
VCC3V
4.7K
8
+12V
R44
JP6
R52 10K
C17
0.1U
HEADER 3
SPEED CONTROL
C18
47u
R51 27K
3
2
1
FANIN3
C19
0.1u R54
10K
CON3
R53
3.9K
PWM FAN 3
R47
4.7K
LM358
FANIN3
R50
10K
DC FAN Control with OP 3
The C17 is reserved for FAN noise dis-bounce.
FAN CONTROL FOR PWM OR DC
Title
Feature Integration Technology Inc.
Size
B
Document Number
FAN Control
Date:
CPU
Sheet
4
of
6
CPU
PWM Controller
R75
R76
R77
R78
R79
R82
R81
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
R67
4.7k
R68
4.7k
R70
4.7k
R97
4.7k
CPU_VID7
CPU_VID6
CPU_VID5
CPU_VID4
CPU_VID3
CPU_VID2
VTT1.2
R99
4.7k
CPU_VID1
CPU_VID0
PWM_VID0
PWM_VID1
PWM_VID2
PWM_VID3
PWM_VID4
PWM_VID5
PWM_VID6
VCC3V(or VCC1.2)
VID0
VID1
R80
4.7k
VID2
R18
4.7k
VID3
R17
4.7k
VID4
VID5
R16
4.7k
PWM_VID7
PWM Controller
VCC3V
R83
4.7k
Rev
0.1
Wednesday , October 05, 2005
VTT1.2
R100
R103
R102
R104
R106
R105
R108
R101
R98
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
4.7k
IO_VIDIN5
IO_VIDIN4
F71883
VIDOUT3
IO_VIDIN3
VIDOUT2
IO_VIDIN2
VIDOUT1
IO_VIDIN1
IO_VIDIN0
VIDOUT0
IO_VIDOUT0
VIDOUT4
IO_VIDOUT1
VIDOUT5
IO_VIDOUT2
F71883
IO_VIDOUT3
For VRM 10.0
IO_VIDOUT4
IO_VIDOUT5
For VRM 11
PWM Controller
R96
0
R109
0
VSI
R110
0
VCORE controlled by F71883
R109:ON R110:ON R96:OFF
VSO
VCORE
CPU
VCORE by-pass
R109:OFF R110:OFF R96:ON
F71883
Title
VSI/VSO
Size
B
Date:
126
Feature Integration Technology Inc.
Document Number
VID
Wednesday , December 14, 2005 Sheet
Rev
0.1
6
of
6
May, 2008
V.27P
F71883
VDDIO
R31
300
R88
300
VIDOUT5
VSO
SIC
VID5
PECI_Client
R108
100K
(avoid pre-bios floating)
SID
Client
AMDSI
Client
PECI
VSI
SST_Host
R109
100K
(avoid pre-bios floating)
Host
SST
Title
Feature Integration Technology Inc.
Size
A
Date:
127
Document Number
AMDSI/PECI/SST
Thursday , January 19, 2006
Rev
0.14
Sheet
6
of
6
May, 2008
V.27P