FAIRCHILD FSB50450S_07

FSB50450S
Smart Power Module (SPM)
Features
General Description
• 500V 3.0A 3-phase FRFET inverter including high voltage
integrated circuit (HVIC)
FSB50450S is a tiny smart power module (SPM) based on
FRFET technology as a compact inverter solution for small
power motor drive applications such as fan motors and water
suppliers. It is composed of 6 fast-recovery MOSFET (FRFET),
and 3 half-bridge HVICs for FRFET gate driving. FSB50450S
provides low electromagnetic interference (EMI) characteristics
with optimized switching speed. Moreover, since it employs
FRFET as a power switch, it has much better ruggedness and
larger safe operation area (SOA) than that of an IGBT-based
power module or one-chip solution. The package is optimized
for the thermal performance and compactness for the use in the
built-in motor application and any other application where the
assembly space is concerned. FSB50450S is the most solution
for the compact inverter providing the energy efficiency,
compactness, and low electromagnetic interference.
• 3 divided negative dc-link terminals for inverter current sensing applications
• HVIC for gate driving and undervoltage protection
• 3/5V CMOS/TTL compatible, active-high interface
• Optimized for low electromagnetic interference
• Isolation voltage rating of 1500Vrms for 1min.
• Surface mounted device package
• Moisture Sensitive Level (MSL) 3
FSB50450S Smart Power Module (SPM)
March 2007
Absolute Maximum Ratings
Symbol
Parameter
Conditions
Rating
Units
500
V
VPN
DC Link Input Voltage,
Drain-source Voltage of each FRFET
ID25
Each FRFET Drain Current, Continuous
TC = 25°C
1.5
A
ID80
Each FRFET Drain Current, Continuous
TC = 80°C
1.0
A
IDP
Each FRFET Drain Current, Peak
TC = 25°C, PW < 100μs
3.0
A
PD
Maximum Power Dissipation
TC = 25°C, Each FRFET
10
W
VCC
Control Supply Voltage
Applied between VCC and COM
20
V
VBS
High-side Bias Voltage
Applied between VB(U)-U, VB(V)-V, VB(W)-W
20
V
VIN
Input Signal Voltage
Applied between IN and COM
-0.3 ~ VCC+0.3
V
TJ
Operating Junction Temperature
-20 ~ 150
°C
TSTG
Storage Temperature
-50 ~ 150
°C
RθJC
Junction to Case Thermal Resistance
Each FRFET under inverter operating condition (Note 1)
8.9
°C/W
VISO
Isolation Voltage
60Hz, Sinusoidal, 1 minute, Connection
pins to heatsink
1500
Vrms
©2007 Fairchild Semiconductor Corporation
FSB50450S Rev. A1
1
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FSB50450S Smart Power Module (SPM)
Pin Descriptions
Pin Number
Pin Name
Pin Description
1
COM
IC Common Supply Ground
2
VB(U)
Bias Voltage for U Phase High Side FRFET Driving
3
VCC(U)
Bias Voltage for U Phase IC and Low Side FRFET Driving
4
IN(UH)
Signal Input for U Phase High-side
5
IN(UL)
Signal Input for U Phase Low-side
6
VS(U)
Bias Voltage Ground for U Phase High Side FRFET Driving
7
VB(V)
Bias Voltage for V Phase High Side FRFET Driving
8
VCC(V)
Bias Voltage for V Phase IC and Low Side FRFET Driving
9
IN(VH)
Signal Input for V Phase High-side
10
IN(VL)
Signal Input for V Phase Low-side
11
VS(V)
Bias Voltage Ground for V Phase High Side FRFET Driving
12
VB(W)
Bias Voltage for W Phase High Side FRFET Driving
13
VCC(W)
Bias Voltage for W Phase IC and Low Side FRFET Driving
14
IN(WH)
Signal Input for W Phase High-side
15
IN(WL)
Signal Input for W Phase Low-side
16
VS(W)
Bias Voltage Ground for W Phase High Side FRFET Driving
17
P
Positive DC–Link Input
18
U
Output for U Phase
19
NU
Negative DC–Link Input for U Phase
20
NV
Negative DC–Link Input for V Phase
21
V
Output for V Phase
22
NW
Negative DC–Link Input for W Phase
23
W
Output for W Phase
(1) COM
(17) P
(2) VB(U)
(3) VCC(U)
VCC
VB
(4) IN(UH)
HIN
HO
(5) IN(UL)
LIN
VS
COM
LO
(18) U
(6) VS(U)
(19) NU
(7) VB(V)
(8) VCC(V)
VCC
VB
(9) IN(VH)
HIN
HO
LIN
VS
COM
LO
(10) IN(VL)
(20) NV
(21) V
(11) VS(V)
(12) VB(W)
(13) VCC(W)
VCC
VB
(14) IN(WH)
HIN
HO
(15) IN(WL)
LIN
VS
COM
LO
(22) NW
(23) W
(16) VS(W)
Note:
Source terminal of each low-side MOSFET is not connected to supply ground or bias voltage ground inside SPM. External connections should be made as indicated in Figure
2 and 5.
Figure 1. Pin Configuration and Internal Block Diagram (Bottom View)
2
FSB50450S Rev. A1
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Inverter Part (Each FRFET Unless Otherwise Specified)
Symbol
BVDSS
Parameter
Conditions
Min Typ Max Units
Drain-Source Breakdown
VIN= 0V, ID = 250μA (Note 2)
Voltage
500
-
-
V
Breakdown Voltage TemID = 250μA, Referenced to 25°C
perature Coefficient
-
0.53
-
V
IDSS
Zero Gate Voltage
Drain Current
VIN= 0V, VDS = 500V
-
-
250
μA
RDS(on)
Static Drain-Source
On-Resistance
VCC = VBS = 15V, VIN = 5V, ID = 1.0A
-
1.9
2.4
Ω
VSD
Drain-Source Diode
Forward Voltage
VCC = VBS = 15V, VIN = 0V, ID = -1.0A
-
-
1.2
V
VPN = 300V, VCC = VBS = 15V, ID = 1.0A
VIN = 0V ↔ 5V
Inductive load L=3mH
High- and low-side FRFET switching
-
1152
-
ns
-
600
-
ns
-
185
-
ns
-
85
-
μJ
-
11
-
μJ
ΔBVDSS/
ΔTJ
tON
tOFF
trr
Switching Times
EON
(Note 3)
EOFF
RBSOA
V = 400V, VCC = VBS = 15V, ID = IDP, VDS=BVDSS,
Reverse-bias Safe Oper- PN
TJ = 125°C
ating Area
High- and low-side FRFET switching (Note 4)
Full Square
Control Part (Each HVIC Unless Otherwise Specified)
Symbol
IQCC
Parameter
Quiescent VCC Current
Conditions
Min Typ Max Units
VCC=15V, VIN=0V
Applied between VCC and COM
-
-
160
μA
Applied between VB(U)-U,
VB(V)-V, VB(W)-W
-
-
100
μA
IQBS
Quiescent VBS Current
VBS=15V, VIN=0V
UVCCD
Low-side Undervoltage
Protection (Figure 6)
VCC Undervoltage Protection Detection Level
7.4
8.0
9.4
V
VCC Undervoltage Protection Reset Level
8.0
8.9
9.8
V
High-side Undervoltage
Protection (Figure 7)
VBS Undervoltage Protection Detection Level
7.4
8.0
9.4
V
VBS Undervoltage Protection Reset Level
8.0
8.9
9.8
V
VIH
ON Threshold Voltage
Logic High Level
3.0
-
-
V
VIL
OFF Threshold Voltage
Logic Low Level
-
-
0.8
V
-
10
20
μA
-
-
2
μA
UVCCR
UVBSD
UVBSR
IIH
IIL
Input Bias Current
VIN = 5V
Applied between IN and COM
Applied between IN and COM
VIN = 0V
Note:
1. For the measurement point of case temperature TC, please refer to Figure 3 in page 4.
2. BVDSS is the absolute maximum voltage rating between drain and source terminal of each FRFET inside SPM. VPN should be sufficiently less than this value considering the
effect of the stray inductance so that VDS should not exceed BVDSS in any case.
3. tON and tOFF include the propagation delay time of the internal drive IC. Listed values are measured at the laboratory test condition, and they can be different according to the
field applcations due to the effect of different printed circuit boards and wirings. Please see Figure 4 for the switching time definition with the switching test circuit of Figure 5.
4. The peak current and voltage of each FRFET during the switching operation should be included in the safe operating area (SOA). Please see Figure 5 for the RBSOA test circuit that is same as the switching test circuit.
Package Marking & Ordering Information
Device Marking
Device
Package
Reel Size
Packing Type
Quantity
FSB50450S
FSB50450S
SPM23BA
330mm
Tape & reel
450
3
FSB50450S Rev. A1
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FSB50450S Smart Power Module (SPM)
Electrical Characteristics (TJ = 25°C, VCC=VBS=15V Unless Otherwise Specified)
Symbol
Parameter
Value
Conditions
Units
Min.
Typ.
Max.
-
300
400
V
VPN
Supply Voltage
Applied between P and N
VCC
Control Supply Voltage
Applied between VCC and COM
13.5
15
16.5
V
VBS
High-side Bias Voltage
Applied between VB and output(U, V, W)
13.5
15
16.5
V
3.0
-
VCC
V
0
-
0.6
V
1.0
-
-
μs
VIN(ON)
Input ON Threshold Voltage
VIN(OFF)
Input OFF Threshold Voltage
Applied between IN and COM
tdead
Blanking Time for Preventing
VCC=VBS=13.5 ~ 16.5V, TJ ≤ 125°C
Arm-short
fPWM
PWM Switching Frequency
TJ ≤ 125°C
-
15
-
kHz
Case Temperature
TJ ≤ 125°C
-20
-
100
°C
TC
These values depend on PWM
control algorithm
R2
15-V Line
R1
P
D1
R5
Micom
C5
VCC
VB
HIN
HO
LIN
VS
COM
LO
Inverter
Output
C3
N
C2
10μF
VDC
R3
One-Leg Diagram of SPM
C1
HIN
LIN
Output
Note
0
0
Z
Both FRFET Off
0
1
0
Low-side FRFET On
1
0
VDC
High-side FRFET On
1
1
Forbidden
Shoot-through
Open
Open
Z
Same as (0, 0)
* Example of bootstrap paramters:
C1 = C2 = 1μF ceramic capacitor,
R1 = 56Ω, R2 = 20Ω
Note:
(1) It is recommended the bootstrap diode D1 to have soft and fast recovery characteristics with 600-V rating
(2) Parameters for bootsrap circuit elements are dependent on PWM algorithm. For 15 kHz of switching frequency, typical example of parameters is shown above.
(3) RC coupling(R5 and C5) at each input (indicated as dotted lines) may be used to prevent improper input signal due to surge noise. Signal input of SPM is compatible with standard CMOS or LSTTL outptus.
(4) Bold lines should be short and thick in PCB pattern to have small stray inductance of circuit, which results in the reduction of surge voltage. Bypass capacitors such as C1, C2
and C3 should have good high-frequency characteristics to absorb high-frequency ripple current.
Figure 2. Recommended CPU Interface and Bootstrap Circuit with Parameters
14.50mm
3.80mm
Case Temperature(Tc)
Detecting Point
MOSFET
Note:
Attach the thermocouple on top of the heatsink-side of SPM (between SPM and heatsink if applied) to get the correct temperature measurement.
Figure 3. Case Temperature Measurement
4
FSB50450S Rev. A1
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FSB50450S Smart Power Module (SPM)
Recommended Operating Conditions
FSB50450S Smart Power Module (SPM)
VIN
VIN
Irr
120% of ID
100% of ID
VDS
ID
10% of ID
ID
VDS
tON
trr
tOFF
(a) Turn-on
(b) Turn-off
Figure 4. Switching Time Definition
REH
VCC
ID
RBS
CBS
VCC
VB
HIN
HO
LIN
VS
COM
LO
L
VDC
+
VDS
-
One-leg Diagram of SPM
Figure 5. Switching and RBSOA(Single-pulse) Test Circuit (Low-side)
Input Signal
UV Protection
Status
Low-side Supply, VCC
RESET
DETECTION
RESET
UVCCR
UVCCD
MOSFET Current
Figure 6. Undervoltage Protection (Low-side)
Input Signal
UV Protection
Status
High-side Supply, VBS
RESET
DETECTION
RESET
UVBSR
UVBSD
MOSFET Current
Figure 7. Undervoltage Protection (High-side)
5
FSB50450S Rev. A1
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(1) COM
R1
(3) VCC(U)
R5
(4) IN(UH)
(5) IN(UL)
C5
C2
C1
R1
(6) VS(U)
VCC
VB
HIN
HO
LIN
VS
COM
LO
(18) U
C3
(9) IN(VH)
(10) IN(VL)
C2
C1
R1
(11) VS(V)
VDC
(19) NU
(7) VB(V)
(8) VCC(V)
Micom
(17) P
(2) VB(U)
VCC
VB
HIN
HO
LIN
VS
COM
LO
VCC
VB
HIN
HO
LIN
VS
COM
LO
(20) NV
(21) V
M
(12) VB(W)
(13) VCC(W)
(14) IN(WH)
(15) IN(WL)
C2
C1
(16) VS(W)
(22) NW
(23) W
For 3-phase current sensing and protection
15-V
Supply
C4
R4
R3
Figure 8. Example of Application Circuit
6
FSB50450S Rev. A1
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FSB50450S Smart Power Module (SPM)
R2
FSB50450S Smart Power Module (SPM)
Detailed Package Outline Drawings
Max 1.00
0.60±0.10
(1.165)
15*1.778=26.67±0.30
15*1.778=26.67
13.34±0.30
13.34±0.30
#1
#1
#16
#16
12.30
4.43
17.90
12.00±0.20
1.30
#17
2.80
2.48
#23
12.23±0.30
13.13±0.30
7.80
15.60
29.00±0.20
LAND PATTERN RECOMMENDATIONS
2x3.90=7.80±0.30
(2.275)
0.508
Max 3.50
Max 1.00
GAGE PLANE
(1.00)
0
0.50+0.1
-0.05
0.60±0.10
17.00±0.20
(1.80)
3.10±0.20
1.95
(1.30)
(1.80)
4x3.90=15.60±0.30
(2.50)
0.15±0.05
(1.30)
5°
±3
°
SEATING PLANE
1.50±0.20
7
FSB50450S Rev. A1
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HEREIN TO IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE
APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER
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WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS.
LIFE SUPPORT POLICY
FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR
SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION.
As used herein:
1. Life support devices or systems are devices or systems
which, (a) are intended for surgical implant into the body or
(b) support or sustain life, and (c) whose failure to perform
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.
2. A critical component in any component of a life support,
device, or system whose failure to perform can be
reasonably expected to cause the failure of the life support
device or system, or to affect its safety or effectiveness.
PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative or In Design
This datasheet contains the design specifications for product
development. Specifications may change in any manner without notice.
Definition
Preliminary
First Production
This datasheet contains preliminary data; supplementary data will be
published at a later date. Fairchild Semiconductor reserves the right to
make changes at any time without notice to improve design.
No Identification Needed
Full Production
This datasheet contains final specifications. Fairchild Semiconductor
reserves the right to make changes at any time without notice to improve
design.
Obsolete
Not In Production
This datasheet contains specifications on a product that has been
discontinued by Fairchild Semiconductor. The datasheet is printed for
reference information only.
Rev. I24
© 2007 Fairchild Semiconductor Corporation
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