GP214D 1.4GHz DUAL PLL DESCRIPTION The GP214D is a dual frequency synthesizer designed for RF operation up to 1.4GHz. The device contains prescalers, programmable reference, and feedback frequency dividers, phase detectors, and charge pumps necessary for the precision control of dual VCO loops. Data transfer is made via a simple serial data interface. The GP214D is fabricated using advanced CMOS process and available in a 16-pin TSSOP plastic package with 0.65mm pitch. FEATURES ▪ Two systems for transmitter and receiver ▪ 2.4V to 5.0V operation (100MHz to 1.4GHz) ▪ Low current consumption 8.5mA @ 3.0V (Typ.) ▪ Modulus prescaler, 64 / 66 ▪ Selectable charge pump current ± 0.2mA, ± 0.4mA, ± 0.8mA, ± 1.6mA Pb 16TSSOP APPLICATIONS ▪ Portable wireless communications (PCS, cordless) ▪ Other wireless communication systems BLOCK DIAGRAM Version 1.2 (Jan. 2006) 1 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL PIN DESCRIPTION Pin No. Symbol Function Description I/O 1 Fin1 RF input, channel 1. I 2, 15 Vcc Power supply. Two pins are connected each other. Charge pump output, channel 1. Charge pump current is selected by the input serial data. - 3 CP1 4, 13 GND Ground. Two pins are connected. - 5 LD Output of lock detection. It is the open drain output. O 6 7 8 CK DATA EN Clock input. Serial data input. Input of enable signal. I 9 BO Output of buffer amplifier. The local signal passes through the buffer amplifier. O 10 OSCO Oscillator output. O 11 OSCI I 12 SW PLL reference input. Typically connected to a TCXO output. Switchover terminal to control time constant of loop filter. It is the open drain output. When switched off, it’s normal output. 14 CP2 Charge pump output, channel 2. O 16 Fin2 RF input, channel 2. I Serial data interface. O O ABSOLUTE MAXIMUM RATINGS Parameters Symbol Value Unit Power supply voltage Vcc 5.5 V Operating temperature TOPR -30 to +85 °C Storage temperature TSTG -35 to +150 °C 2000 V ESD (Human body model) Note: This device is ESD sensitive. Appropriate ESD protection is required for device handling and assembly. Version 1.2 (Jan. 2006) 2 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL ELECTRICAL CHARACTERISTICS (Unless otherwise specified, Vcc = 3.0V, Ta = 25°C) Characteristic Operating power supply voltage Operating current consumption Symbol Test Condition Min. Typ. Max. Unit Vcc Fin1= Fin2= 200MHz~1.4GHz 2.4 3.0 5.0 V Icc Fin1= Fin2= 800MHz/ -5dBm input 7.0 8.5 14.5 mA Standby current ISB Standby mode - 0 80 µA Fin operating frequency Fin Fin1=Fin2= -5dBm 200 - 1400 MHz Vcc = 2.4V -15 - 10 Vcc = 3.0V -15 - 10 Vcc = 5.0V -15 - 10 Vcc = 2.4V -15 - 0 Vcc = 3.0V -15 - 0 Vcc = 5.0V -15 - 0 4 - 40 Fin1= Fin2= 200~1200MHz Fin input sensitivity Fin dBm Fin1= Fin2= 1200~1400MHz OSCI operating frequency FOSC OSCI input voltage VOSC VFin= 0dBm, sinewave FOSC= 4~10MHz Vcc= 2.4~3.7V -10 0 10 FOSC= 10~40MHz Vcc= 2.4~5.0V -15 0 20 Vcc - V - 0 0.2 V dBm Vcc – Serial data input high voltage (CK, DATA, EN) VIH Serial data input low voltage (CK, DATA, EN) VIL Vcc= 1.7 to 5.0V ICP1 CP1= 0, CP2= 0 (VCP= 1/2 Vcc) - 15% ± 1.6 + 15% ICP2 CP1= 1, CP2= 0 (VCP= 1/2 Vcc) - 15% ± 0.2 + 15% ICP3 CP1= 0, CP2= 1 (VCP= 1/2 Vcc) - 15% ± 0.4 +15% ICP4 CP1= 1, CP2= 1 (VCP= 1/2 Vcc) - 15% ± 0.8 +15% ICPL Standby mode (VCP= 1/2 Vcc) -1 - 1 Charge pump output current Charge pump leakage MHz Vcc= 1.7 to 5.0V 0.2 mA µA Version 1.2 (Jan. 2006) 3 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL PROGRAMMING DESCRIPTION SERIAL DATA INPUT AND TIMING The programmable functions are accessed through the MCU serial data interface. The interface includes clock (CK, pin 6), data (DATA, pin 7) and enable signal (EN, pin 8). Serial data controls programmable reference counter and programmable counters in channel 1 and channel 2. The serial data is clocked in on the rising edge of clock and transferred into the shift register composed of 17-bit data field and 2-bit control field. When EN is high, stored data is latched. Data is entered LSB first. ≥0.1us ≥0.2us ≥0.2us CK LSB DATA MSB ≥0.2us N1(R1) N2(R2) N17(R12) ≥0.1us GC2 GC1 ≥0.1us ≥0.2us ≥0.2us EN GROUP CODE AND LOCATION The data stored in the shift register is loaded into one of four appropriate latches depending on the state of group code (control bits) listed below. Control Bits Data Location GC2(MSB-1) GC1(MSB) 0 0 Control Latch 1 0 Ch 1 N Latch 0 1 Ch 2 N Latch 1 1 OSC R Latch Version 1.2 (Jan. 2006) 4 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL OPTIONAL CONTROL The control register enables various functions shown in the table below. LSB Bit1 Channel 1 Channel 2 MSB Bit2 Bit3 Bit4 Bit5 Bit6 Bit7 Bit8 Bit9 Bit10 Bit11 T CP CP1 CP2 SB1 CP1 CP2 SB2 SBR LD1 LD2 Test Mode Charge Pump Polarity Ch2 Standby Ref. Divider Standby Charge Pump Output Current Ch 1 Standby Charge Pump Output Current Lock Detector Bit12 Bit13 Bit14 SW GC2 GC1 Filter Switch Group Code “0”, “0” ▪ Test mode selection (T) H: test mode, L: normal mode ▪ Output polarity of charge pump (CP) CP is set to “0” at normal and changed to “1” when reverse operation, according to the dependence of VCO output frequency upon VCO input voltage. “Normal” denotes proportional response in the frequency to the VCO input voltage. ▪ Charge pump output current (CP1 and CP2) Charge pump employs circuits characterized by constant output current. The output current can be selected for the best performance. Control Bits Charge Pump Output Current CP1 CP2 0 0 ±1600µA 0 1 ±200µA 1 0 ±400µA 1 1 ±800µA Version 1.2 (Jan. 2006) 5 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL ▪ Test mode and lock detector output (T, LD1 and LD2) The LD state can be changed via controlling SB1, SB2, LD1 and LD2. T SB1 SB2 LD1 LD2 LD Output State 0 0 low 0 1 channel2 1 0 channel1 1 1 channel 1 and channel2 0 0 low 0 1 high 1 0 channel1 1 1 channel1 0 0 low 0 1 channel2 1 0 high 1 1 channel2 0 0 low 0 1 high 1 0 high 1 1 high 0 0 low 0 1 pres2 1 0 fpll2 1 1 fref 0 0 div4 0 1 pres1 1 0 fpll1 1 1 fosc/2 0 0 1 0 0 1 1 1 0 1 0 1 1 1 × × low 0 0 × × low Version 1.2 (Jan. 2006) 6 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL ▪ Lock detector output When the phase difference is detected, LD (pin 5) goes “L”. When locked or at standby, LD changes to H”. In case where the time difference, “T” less than 2/fosc (T<2/fosc) continues for more than three cycles of reference counter output, LD goes “H”. Fosc: OSCI operating frequency (LOCAL OSC) T: time difference of the pulse between reference divider output and channel divider output Number of divisions by reference dividers fosc 2 B= fosc A= A Reference Divider Output B Channel Divider Output T Charge pump Output T<2/fosc Lock Detector Output ▪ Programmable standby mode (SB1, SB2 and SBR) Standby mode is controlled by three control bits of SB1, SB2 and SBR. The standby control of channel 1 and channel 2 can be made by SB1 and SB2. The on/off of reference divider is controlled by SBR. SB1 0 0 1 1 1 Control Bit SB2 0 1 0 1 1 SBR 0 0 0 0 1 CH1 ON ON OFF OFF OFF Standby Mode Status CH2 REF ON ON OFF ON ON ON OFF ON OFF OFF Mode Status Inter-locking CH1 locking CH2 locking REF ON Standby Version 1.2 (Jan. 2006) 7 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL ▪ Filter switch control (SW) SW terminal, for switching time constant of loop filter is controlled by “SW” bit. High lock mode and normal lock mode can be arbitrarily selected by filter switch control (SW) with the charge pump output current. Control Bits CP1 CP2 0 0 0 1 1 0 1 1 0 0 0 1 1 0 1 1 SW 0 0 0 0 1 1 1 1 Mode High Lock Normal Lock CRYSTAL OSCILLATOR CIRCUIT (OSCI, OSCO) AND BUFFER OUT (BO) Reference frequency input is made directly to OSCI (pin 11). Buffer output (BO, pin 9) can be used for the 2nd mixer input. REFERENCE COUNTER When the control bits (GC1, GC2) are “11”, data is transferred from shift register into the OSC R latch which sets the divide ratio of 12-bit reference counter. The divide ratio is programmed using the bits as shown in the table below. LSB R1 R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 Reference Counter GC2 “1” MSB GC1 “1” Group Code Divide ratio: 2×R = 2×(3 to 4095) = 6 to 8190 Divide Ratio 3 4 ・ 4095 R12 R11 R10 R9 R8 R7 R6 R5 R4 R3 R2 R1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 1 ・ 1 1 0 ・ 1 1 0 ・ 1 Version 1.2 (Jan. 2006) 8 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL PROGRAMMABLE N-COUNTER, CH1 AND CH2 These counters consist of the 5-bit swallow counter, the 12-bit programmable main counter, and two modulus prescaler providing divisions of 64 and 66. The swallow counter and main counter enable to set any of 192 to 262142 divisions. LSB MSB Swallow counter N1 N2 N3 N4 Main counter N5 N6 N7 N8 N9 N10 N11 N12 N13 N14 N15 N16 N17 N18 N19 N-Counter divide ratio, N Group code CH1, “10” CH2, “01" 5-BIT SWALLOW COUNTER DIVIDE RATIO (A COUNTER) Divide ratio: 0 to 31, B≥A Divide N5 Ratio (A) 0 0 1 0 ・ ・ 31 1 N4 N3 N2 N1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 1 ・ 1 12-BIT MAIN COUNTER DIVIDE RATIO (B COUNTER) Divide ratio: 3 to 4095 Divide Ratio (B) 3 4 ・ 4095 N17 N16 N15 N14 N13 N12 N11 N10 N9 N8 N7 N6 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 0 ・ 1 0 1 ・ 1 1 0 ・ 1 1 0 ・ 1 Divide ratio of channel 1 and 2 = N N = 2×(32×B+A), B≥A Divide ratio: 192 to 262142 Version 1.2 (Jan. 2006) 9 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL TEST CIRCUIT ▪ Sensitivity measurement - RF signal input is to be matched to 50Ohm and short line is recommended. - R1 and R2 (51Ohm) are connected to GND. - Tests at different bias and power levels are normally conducted. - Turn on DC voltage and RF signal before the data programming. - Frequency is monitored from TP1 (test point, 1) via frequency counter or oscilloscope. ▪ Charge pump current measurement - VCP can be fixed to 1/2 VCC or varied from 0 to maximum VCC. - Charge pump polarity is changed from normal to reverse. Version 1.2 (Jan. 2006) 10 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL APPLICATION CIRCUIT - R3~R6 & C1~C6: Loop filter components (depending on frequency, phase noise and lock time) - SW turns on when R7 is connected. PACKAGE DEMENSIONS 16-pin TSSOP (Unit: Millimeters) Version 1.2 (Jan. 2006) 11 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL Version 1.2 (Jan. 2006) 12 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL Version 1.2 (Jan. 2006) 13 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL Version 1.2 (Jan. 2006) 14 GAINTECH INCORPORATED GP214D 1.4GHz DUAL PLL Version 1.2 (Jan. 2006) 15 GAINTECH INCORPORATED