ETC HD151TS306RP

HD151TS306RP
Spread Spectrum Clock for EMI Solution
ADE-205-659C (Z)
Preliminary
Rev.3
Jun. 2002
Description
The HD151TS306 is a high-performance Spread Spectrum Clock modulator. It is suitable for low EMI
solution.
Features
• Supports 40 MHz to 140 MHz operation. (Designed @ SSCCLKOUT = 48 MHz and 72 MHz)
• 1 copy of finx4 clock out with Spread Spectrum Modulation @3.3 V
• 1 copy of reference clock @3.3 V
• Programmable Spread Spectrum Modulation (-0.5%, -1.0%, -3.0% Down Spread Modulation and
Spread Spectrum disable mode)
• SOP-8pin
Key Specifications
• Supply Voltages: VDD = 3.3 V ±0.165 V
• 0 to 70°C (Ta) Operating Range
• 50 ± 5% Outputs Clock Duty Cycle
• Cycle to Cycle jitter = ±250ps typ.
HD151TS306RP
Block Diagram
VDD
GND
CLKOUT (12MHz typ.)
XIN
OSC
1/m
SSCCLKOUT (48MHz typ.)
Synthesizer
XOUT R=1 MΩ
1/n
SSC Modulator
SEL0
R=100 kΩ
Mode Control
SEL1
R=100 kΩ
Pin Arrangement
SSCCLKOUT
1
8
SEL1
VDD
2
7
CLKOUT
GND
3
6
SEL0
XIN
4
5
XOUT
(Top view)
Rev.3, Jun. 2002, page 2 of 10
HD151TS306RP
SSC Function Table
SEL1 :0
Spread Percentage
00
-1.0%
01
-3.0%
10
SSC OFF
11
-0.5%
Note: -0.5% SSC is selected for default by internal pull-up & down resistors.
Clock Frequency Table
XIN(MHz)
SSCCLKOUT(MHz)
*1
10
40
35
140
*1
CLKOUT(MHz)
10
*2
35
*2
Notes: 1. With spread spectrum modulation.
2. Without spread spectrum modulation.
Pin Descriptions
Pin name
No.
Type
Description
GND
3
Ground
GND pin
VDD
2
Power
Power supplies pin. Normally 3.3 V.
CLKOUT
7
Output
Normally 3.3 V reference clock output.
SSCCLKOUT
1
Output
Spread spectrum modulated clock output.
XIN
4
Input
Oscillator input.
XOUT
5
Output
Oscillator output.
SEL0
6
Input
SSC mode select pin. LVCMOS level input.
Pull-up by internal resistor (100 kΩ).
SEL1
8
Input
SSC mode select pin. LVCMOS level input.
Pull–up by internal resistor (100 kΩ).
Rev.3, Jun. 2002, page 3 of 10
HD151TS306RP
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
VDD
–0.5 to 4.6
V
VI
–0.5 to 4.6
V
VO
–0.5 to
VDD+0.5
V
Input clamp current
IIK
–50
mA
VI < 0
Output clamp current
IOK
–50
mA
VO < 0
Continuous output current
IO
±50
mA
VO = 0 to VDD
0.7
W
–65 to +150
°C
Input voltage
Output voltage
*1
Maximum power dissipation
at Ta = 55°C (in still air)
Storage temperature
Notes:
Tstg
Conditions
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage
to the device. These are stress ratings only, and functional operation of the device at these or
any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute maximum rated conditions for extended periods may affect device
reliability.
1. The input and output negative voltage ratings may be exceeded if the input and output clamp
current ratings are observed.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit Conditions
Supply voltage
VDD
3.135
3.3
3.465
V
–0.3
—
VDD+0.3
V
DC input signal voltage
High level input voltage
VIH
2.0
—
VDD+0.3
V
Low level input voltage
VIL
–0.3
—
0.8
V
Operating temperature
Ta
0
—
70
°C
45
50
55
%
Input clock duty cycle
Rev.3, Jun. 2002, page 4 of 10
HD151TS306RP
DC Electrical Characteristics
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Symbol
Min
Typ
Input low voltage
VIL
—
Input high voltage
VIH
Input current
II
Input slew rate
Input capacitance
CI
Operating current
Note:
*1
Max
Unit
Test Conditions
—
0.8
V
2.0
—
—
V
—
—
±10
µA
—
—
±100
1
—
4
V / ns 20% – 80%
—
—
4
pF
SEL0, SEL1
—
20
—
mA
XIN = 24 MHz, CL = 0 pF,
VDD = 3.3 V
VI = 0 V or 3.465 V,
VDD = 3.465 V, XIN pin
VI = 0 V or 3.465 V,
VDD = 3.465 V,
SEL0, SEL1 pins
1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
DC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 0 to 70°C, VDD = 3.3 V±5%
Item
Symbol Min
Typ
Output voltage
VOH
3.1
VOL
—
Note:
*1
Max
Unit
Test Conditions
—
—
V
IOH = –1 mA, VDD = 3.3 V
—
50
mV
IOL = 1 mA, VDD = 3.3 V
1. For conditions shown as Min or Max, use the appropriate value specified under recommended
operating conditions.
Rev.3, Jun. 2002, page 5 of 10
HD151TS306RP
AC Electrical Characteristics / Clock Output & SSC Clock Output
Ta = 25°C, VDD = 3.3 V, CL = 15 pF
Item
Cycle to cycle jitter
*1, 2
Symbol
Min
Typ
Max
Unit Test Conditions Notes
tCCS
—
| 250 |
| 300 |
ps
—
| 250 |
—
SSCCLKOUT
= 48MHz,
XIN = 12 MHz
SSC = 0%
SEL1:0 = 10
Fig1
| 300 |
SSCCLKOUT
= 48MHz,
XIN = 12 MHz
SSC = -0.5%
SEL1:0 = 11
Fig1
| 250 |
| 300 |
SSCCLKOUT
= 72MHz,
XIN = 18 MHz
SSC = 0%
SEL1:0 = 10
Fig1
—
| 250 |
| 300 |
SSCCLKOUT
= 72MHz,
XIN = 18 MHz
SSC = -0.5%
SEL1:0 = 11
Fig1
—
| 250 |
| 300 |
47.3
—
48.7
MHz SSCCLKOUT
= 48MHz,
XIN = 12 MHz
SSC = 0%
SEL1:0 = 10
47.1
—
48.7
SSCCLKOUT
= 48MHz,
XIN = 12 MHz
SSC = -0.5%
SEL1:0 = 11
70.4
—
73.6
SSCCLKOUT
= 72MHz,
XIN = 18 MHz
SSC = 0%
SEL1:0 = 10
70.1
—
73.6
SSCCLKOUT
= 72MHz,
XIN = 18 MHz
SSC = -0.5%
SEL1:0 = 11
0.8
—
—
V/ns XIN = 12 MHz
CLKOUT
0.4 V to 2.4 V
45
50
55
%
—
40
—
Ω
Spread spectrum
*1
modulation frequency
—
33
—
KHz SSCCLKOUT
= 96MHz,
XIN = 24 MHz
Input clock frequency
10
—
35
MHz
—
—
2
ms
Output frequency
*1, 2
*1
Slew rate
Clock duty cycle
tSL
*1
Output impedance
Stabilization time
Note:
*1
*1,3
CLKOUT=12MHz Fig1
1. Parameters are target of design. Not 100% tested in production.
2. Cycle to cycle jitter and output frequency are included spread spectrum modulation.
3. Stabilization time is the time required for the integrated circuit to obtain phase lock of its input
signal after power up.
Rev.3, Jun. 2002, page 6 of 10
HD151TS306RP
SSCCLKOUT
(or CLKOUT)
tcycle n
tcycle n+1
t CCS = (tcycle n) - (tcycle n+1)
Figure 1 Cycle to cycle jitter
Rev.3, Jun. 2002, page 7 of 10
HD151TS306RP
Application Information
Recommended Circuit Configuration
The power supply circuit of the optimal performance on the application of a system should refer to Fig. 2.
VDD decoupling is important to both reduce Jitter and EMI radiation.
The C1 decoupling capacitor should be placed as close to the VDD pin as possible, otherwise the increased
trace inductance will negate its decoupling capability.
The C2 decoupling capacitor shown should be a tantalum type.
R1
SSCCLKOUT
1
8
VDD
2
7
SEL1
R2
C2
CLKOUT
C1
3
6
SEL0
TS306
GND GND
4
5
GND
Notes:
XIN
XOUT
(Crystal or
Reference input)
(Crystal or
Not connection)
C1 = High frequency supply decoupling capacitor.
(0.1 µF recommended)
C2 = Low frequency supply decoupling capacitor.
(22 µF tantalum type recommended)
R1, R2 = Match value to line impedance.
Figure 2 Recommended circuit configuration
Rev.3, Jun. 2002, page 8 of 10
HD151TS306RP
Package Dimensions
As of January, 2002
Unit: mm
3.95
4.90
5.3 Max
5
8
*0.22 ± 0.03
0.20 ± 0.03
4
1.75 Max
1
0.75 Max
+ 0.10
6.10 – 0.30
1.08
0.14 – 0.04
*0.42 ± 0.08
0.40 ± 0.06
+ 0.11
0˚ – 8˚
1.27
+ 0.67
0.60 – 0.20
0.15
0.25 M
*Dimension including the plating thickness
Base material dimension
Hitachi Code
JEDEC
JEITA
Mass (reference value)
FP-8DC
Conforms
—
0.085 g
Rev.3, Jun. 2002, page 9 of 10
HD151TS306RP
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received the latest product standards or specifications before final design, purchase or use.
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contact Hitachi’s sales office before using the product in an application that demands especially high
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4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly
for maximum rating, operating supply voltage range, heat radiation characteristics, installation
conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used
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failure rates or failure modes in semiconductor devices and employ systemic measures such as failsafes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other
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Copyright © Hitachi, Ltd., 2002. All rights reserved. Printed in Japan.
Colophon 6.0
Rev.3, Jun. 2002, page 10 of 10