HD74HC259 8-bit Addressable Latch REJ03D0603–0200 (Previous ADE-205-480) Rev.2.00 Jan 31, 2006 Description The HD74HC259 has a single data input (D), 8 latch outputs (Q0-Q7), 3 address inputs (A, B, and C), a common enable input (E), and a common clear input. To operate this device as an addressable latch, data is held on the D input, and the address of the latch into which the data is to be entered is held on the A, B and C inputs. When enable is taken low the data flows through to the addressed output. The data is stored when enable transitions from low to high. All unaddressed latches will remain unaffected. With enable in the high state the device is deselected, and all latches remain in their previous state, unaffected by changes on the data or address inputs. To eliminate the possibility of entering erroneous data into the latches, the enable should be held high (inactive) while the address lines are changing. If enable is held high and clear is taken low all eight latches are cleared to a low state. If enable is low all latches except the addressed latch will be cleared. The addressed latch will instead follow the D input, effectively implementing a 3to-8 line decoder. Features • • • • • • High Speed Operation: tpd (Data to Output) = 16 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C) Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74HC259P DILP-16 pin PRDP0016AE-B (DP-16FV) P — HD74HC259FPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) HD74HC259RPEL SOP-16 pin (JEDEC) PRSP0016DG-A (FP-16DNV) RP EL (2,500 pcs/reel) Note: Please consult the sales office for the above package availability. Rev.2.00 Jan 31, 2006 page 1 of 9 HD74HC259 Function Table Inputs Clear H H L L G L H L H Output of Addressed Latch Each Other Output D Qio D L Qio Qio L L Select Inputs Function Addressable latch Memory 8-line demultiplexer Clear Latch Addressed C B A L L L L L H 1 L H L 2 L H H 3 H L L 4 H L H 5 H H L 6 H H H 7 0 Notes: 1. D: the level at the data input 2. Qio: the level of Qi (i = 0, 1, ···7, as appropriate) before the indicated steady-state input conditions were established. Pin Arrangement Latch select 16 VCC A 1 B 2 B C 3 C G 14 Enable Q0 4 Q0 D 13 Q1 5 Q1 Q7 12 Q7 Q2 6 Q2 Q6 11 Q6 Q3 7 Q3 Q5 10 Q5 GND 8 A CLR 15 Clear Data input Outputs Outputs Q4 9 Q4 (Top view) Rev.2.00 Jan 31, 2006 page 2 of 9 HD74HC259 Absolute Maximum Ratings Item Supply voltage range Input / Output voltage Input / Output diode current Output current VCC, GND current Power dissipation Storage temperature Symbol VCC VIN, VOUT IIK, IOK IO ICC or IGND PT Tstg Ratings –0.5 to 7.0 –0.5 to VCC +0.5 ±20 ±25 ±50 500 –65 to +150 Unit V V mA mA mA mW °C Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. Recommended Operating Conditions Item Supply voltage Input / Output voltage Operating temperature Input rise / fall time*1 Symbol VCC VIN, VOUT Ta tr, tf Ratings 2 to 6 0 to VCC –40 to 85 0 to 1000 0 to 500 0 to 400 Unit V V °C ns Conditions VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V Notes: 1. This item guarantees maximum limit when one input switches. Waveform: Refer to test circuit of switching characteristics. Electrical Characteristics Item Input voltage Symbol VCC (V) VIH VIL Output voltage VOH VOL Input current Iin Quiescent supply current ICC Min Ta = 25°C Typ Max Ta = –40 to+85°C Unit Min Max 2.0 4.5 6.0 2.0 4.5 1.5 3.15 4.2 — — — — — — — — — — 0.5 1.35 1.5 3.15 4.2 — — — — — 0.5 1.35 6.0 2.0 4.5 6.0 4.5 6.0 — 1.9 4.4 5.9 4.18 5.68 — 2.0 4.5 6.0 — — 1.8 — — — — — — 1.9 4.4 5.9 4.13 5.63 1.8 — — — — — 2.0 4.5 6.0 4.5 6.0 6.0 6.0 — — — — — — — 0.0 0.0 0.0 — — — — 0.1 0.1 0.1 0.26 0.26 ±0.1 4.0 — — — — — — — 0.1 0.1 0.1 0.33 0.33 ±1.0 40 Rev.2.00 Jan 31, 2006 page 3 of 9 Test Conditions V V V Vin = VIH or VIL IOH = –20 µA IOH = –4 mA IOH = –5.2 mA V Vin = VIH or VIL IOL = 20 µA IOL = 4 mA IOL = 5.2 mA µA Vin = VCC or GND µA Vin = VCC or GND, Iout = 0 µA HD74HC259 Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns) Item Propagation delay time Symbol VCC (V) tPHL tPLH tPHL Pulse width tw Setup time tsu Hold time th Output rise/fall time tTLH tTHL Input capacitance Cin 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 4.5 6.0 2.0 Ta = 25°C Min Typ Max — — 185 — 16 37 — — 31 — — 215 — 20 43 — — 37 — — 200 — 17 40 — — 34 — — 155 — 15 31 — — 26 80 — — 16 6 — 14 — — 100 — — Ta = –40 to +85°C Unit Test Conditions Min Max — 230 ns Data to output — 46 — 39 — 270 ns Latch select to output — 54 — 46 — 250 ns Enable to output — 50 — 43 — 195 ns Clear to output — 39 — 33 100 — ns Clear, Enable 20 — 17 — 125 — ns Latch select or data to enable 4.5 6.0 20 17 5 — — — 25 21 — — 2.0 4.5 6.0 2.0 4.5 6.0 — 5 5 5 — — — — — –1 — — 5 — 5 — — — 75 15 13 10 5 5 5 — — — — — — — 95 19 16 10 ns Latch select or data to enable ns pF Test Circuit VCC VCC Pulse Generator Zout = 50 Ω See Function Table G Input Output Clear A Q0 to Q7 B C D Note : 1. CL includes probe and jig capacitance. Rev.2.00 Jan 31, 2006 page 4 of 9 CL = 50 pF HD74HC259 Waveforms • Waveform – 1 tf tr VCC 90% 90% Enable G 10% 10% 0V tf tr 90% 50% Clear 90% 50% 10% 10% VCC 0V tw (Clear) tPHL VOH 90% 50% Addressed Output Q 10% VOL tTHL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. D = VCC , Unaddressed Q = L • Waveform – 2 tr tf 90% 50% Data 10% 10% 0V tPHL tPLH 90% Output Q VCC 90% 50% 50% 10% tTLH VOH 90% 50% 10% tTHL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Other input : G = GND, Clear = Vcc, A to C = Address Rev.2.00 Jan 31, 2006 page 5 of 9 VOL HD74HC259 • Waveform – 3 VCC Data 0V tr tf 90 % 50 % Address (A to C) VCC 90 % 50 % 50 % 10 % 10 % 0V t PLH Addressed Output Q t PHL 90 % VOH 90 % 50 % 10 % 50 % 10 % t TLH VOL t THL VOH Addressed Output Q VOL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Other input : G = GND, Clear = VCC, A to C = Address • Waveform – 4 VCC Data 50% 50% tsu(H) 90% 50% 10% tsu(L) th(L) 90% 50% 50% 50% tPLH 90% 50% 10% tTLH 0V tPHL VOH 90% 50% 10% tTHL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Other input : Clear = VCC, A to C = Address Rev.2.00 Jan 31, 2006 page 6 of 9 0V VCC 10% tw(G) Qn th(H) tr tf G 50% VOL HD74HC259 • Waveform – 5 VCC Data 0V Address Input VCC 50 % 50 % 50 % 50 % 0V tsu th tsu th VCC G 50 % 50 % 0V VOH Qn VOL Notes : 1. Input pulse : PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 6 ns, tf ≤ 6 ns 2. Other input : Clear = VCC 3. Address inputs except appropriate inputs are set to address to appropriate Q outputs. Rev.2.00 Jan 31, 2006 page 7 of 9 HD74HC259 Package Dimensions JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B MASS[Typ.] 1.05g Previous Code DP-16FV D 9 E 16 1 8 b3 0.89 Z A1 A Reference Symbol L e Nom θ c e1 D 19.2 E 6.3 JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV 7.4 A1 0.51 b p 0.40 b 3 0.48 0.56 1.30 c 0.19 θ 0° e 2.29 0.25 0.31 2.54 2.79 15° 1.12 L 2.54 MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 20.32 5.06 Z ( Ni/Pd/Au plating ) Max 7.62 1 A bp e Dimension in Millimeters Min 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.20 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.2.00 Jan 31, 2006 page 8 of 9 8° 0.50 1 0.70 1.15 0.90 HD74HC259 JEITA Package Code P-SOP16-3.95x9.9-1.27 RENESAS Code PRSP0016DG-A *1 Previous Code FP-16DNV MASS[Typ.] 0.15g D NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F 16 9 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 9.90 10.30 E 3.95 A2 8 1 Z e *3 bp x A1 0.10 0.14 0.25 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 1.75 A M L1 bp b1 c A c A1 θ L y Detail F 1 θ 0° HE 5.80 e 1.27 x 0.25 y 0.15 0.635 Z 0.40 L L Rev.2.00 Jan 31, 2006 page 9 of 9 8° 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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