HOLTIC HI-8282APJI

HI-8282A
May 2001
ARINC 429 SERIAL TRANSMITTER AND DUAL RECEIVER
GENERAL DESCRIPTION
FEATURES
The HI-8282A is a silicon gate CMOS device for interfacing
the ARINC 429 serial data bus to a 16-bit parallel data bus.
Two receivers and an independent transmitter are
provided. The receiver input circuitry and logic are
designed to meet the ARINC 429 specifications for loading,
level detection, timing, and protocol. The transmitter
section provides the ARINC 429 communication protocol.
Additional interface circuitry such as the Holt HI-8585,
HI-8586 or HI-3182 is required to translate the 5 volt logic
outputs to ARINC 429 drive levels.
The 16-bit parallel data bus exchanges the 32-bit ARINC
data word in two steps when either loading the transmitter
or interrogating the receivers. The data bus interfaces with
CMOS and TTL.
! ARINC specification 429 compatible
! 16-Bit parallel data bus
! Direct receiver interface to ARINC bus
! Timing control 10 times the data rate
! Selectable data clocks
! Receiver error rejection per ARINC
specification 429
! Automatic transmitter data timing
! Self test mode
! Parity functions
! Low power, single 5 volt supply
! Industrial & full military temperature ranges
Timing of all the circuitry begins with the master clock input,
CLK. For ARINC 429 applications, the master clock
frequency is 1 MHz.
Each independent receiver monitors the data stream with a
sampling rate 10 times the data rate. The sampling rate is
software selectable at either 1MHz or 125KHz. The results
of a parity check are available as the 32nd ARINC bit. The
HI-8282A examines the null and data timings and will reject
erroneous patterns. For example, with a 125 KHz clock
selection, the data frequency must be between 10.4 KHz
and 15.6 KHz.
The transmitter has a First In, First Out (FIFO) memory to
store 8 ARINC words for transmission. The data rate of the
transmitter is software selectable by dividing the master
clock, CLK, by either 10 or 80. The master clock is used to
set the timing of the ARINC transmission within the required
resolution.
PIN CONFIGURATION (Top View)
N/C - 1
D/R1 - 2
D/R2 - 3
SEL - 4
EN1 - 5
EN2 - 6
BD15 - 7
BD14 - 8
BD13 - 9
BD12 - 10
BD11 - 11
HI-8282APQI
&
HI-8282APQT
33 - N/C
32 - N/C
31 - CWSTRX
30 - ENTX
29 - 429DO
28 - 429DO
27 - TX/R
26 - PL2
25 - PL1
24 - BD00
23 - BD01
APPLICATIONS
! Avionics data communication
! Serial to parallel conversion
! Parallel to serial conversion
(DS8282A Rev. New)
44-Pin Plastic Quad Flat Pack (PQFP)
(See page 10 for additional Package Pin Configurations)
HOLT INTEGRATED CIRCUITS
1
05/01
HI-8282A
PIN DESCRIPTION
SYMBOL
FUNCTION
DESCRIPTION
VCC
POWER
429DI1 (A)
INPUT
ARINC receiver 1 positive input
+5V ±5%
429DI1 (B)
INPUT
ARINC receiver 1 negative input
429DI2 (A)
INPUT
ARINC receiver 2 positive input
429DI2 (B)
INPUT
ARINC receiver 2 negative input
D/R1
OUTPUT
Receiver 1 data ready flag
D/R2
OUTPUT
Receiver 2 data ready flag
SEL
INPUT
Receiver data byte selection (0 = BYTE 1) (1 = BYTE 2)
EN1
INPUT
Data Bus control, enables receiver 1 data to outputs
EN2
INPUT
Data Bus control, enables receiver 2 data to outputs if EN1 is high
BD15
I/O
Data Bus
BD14
I/O
Data Bus
BD13
I/O
Data Bus
BD12
I/O
Data Bus
BD11
I/O
Data Bus
BD10
I/O
Data Bus
BD09
I/O
Data Bus
BD08
I/O
Data Bus
BD07
I/O
Data Bus
BD06
I/O
Data Bus
GND
POWER
BD05
I/O
Data Bus
BD04
I/O
Data Bus
BD03
I/O
Data Bus
BD02
I/O
Data Bus
BD01
I/O
Data Bus
0V
BD00
I/O
PL1
INPUT
Latch enable for byte 1 entered from data bus to transmitter FIFO.
Data Bus
Latch enable for byte 2 entered from data bus to transmitter FIFO. Must follow PL1.
PL2
INPUT
TX/R
OUTPUT
Transmitter ready flag. Goes low when ARINC word loaded into FIFO. Goes high
after transmission and FIFO empty.
429DO
OUTPUT
"ONES" data output from transmitter.
429DO
OUTPUT
"ZEROES" data output from transmitter.
ENTX
INPUT
Enable Transmission
CWSTR
INPUT
Clock for control word register
CLK
INPUT
Master Clock input
TX CLK
OUTPUT
MR
INPUT
Transmitter Clock equal to Master Clock (CLK), divided by either 10 or 80.
Master Reset, active low
HOLT INTEGRATED CIRCUITS
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HI-8282A
FUNCTIONAL DESCRIPTION
ARINC 429 DATA FORMAT
The following table shows the bit positions in exchanging data with
the receiver or the transmitter. ARINC bit 1 is the first bit
transmitted or received.
CONTROL WORD REGISTER
The HI-8282A contains 10 data flip flops whose D inputs are connected to the data bus and clocks connected to CWSTR. Each
flip flop provides options to the user as follows:
DATA
BUS
PIN
FUNCTION CONTROL
BDO5
SELF TEST
0 = ENABLE
DESCRIPTION
If enabled, an internal connection
is made passing 429DO and
429DO to the receiver logic inputs
BDO6
RECEIVER 1
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and,
10 must match the next two
control word bits
BDO7
-
-
If Receiver 1 Decoder is
enabled, the ARINC bit 9
must match this bit
-
If Receiver 1 Decoder is
enabled, the ARINC bit 10
must match this bit
BDO8
-
BDO9
RECEIVER 2
DECODER
1 = ENABLE
If enabled, ARINC bits 9 and
10 must match the next two
control word bits
BD10
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 9
must match this bit
BD11
-
-
If Receiver 2 Decoder is
enabled, then ARINC bit 10
must match this bit
INVERT
XMTR
PARITY
1 = ENABLE
Logic 0 enables normal odd parity
and Logic 1 enables even parity
output in transmitter 32nd bit
BD13
XMTR DATA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain XMTR data clock
BD14
RCVR DTA
CLK SELECT
0 = ÷10
1 = ÷80
CLK is divided either by 10 or
80 to obtain RCVR data clock
BD12
BYTE 1
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
13 12 11 10
DATA
BUS
BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD BD
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
ARINC
BIT
29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14
9
31 30 32
1
2
3
4
5
6
7
8
BYTE 2
THE RECEIVERS
ARINC BUS INTERFACE
Figure 1 shows the input circuit for each receiver. The ARINC 429
specification requires the following detection levels:
STATE
ONE
NULL
ZERO
DIFFERENTIAL VOLTAGE
+6.5 Volts to +13 Volts
+2.5 Volts to -2.5 Volts
-6.5 Volts to -13 Volts
The HI-8282A guarantees recognition of these levels with a common
mode Voltage with respect to GND less than ±5V for the worst case
condition (4.75V supply and 13v signal level).
The tolerances in the design guarantee detection of the above
levels, so the actual acceptance ranges are slightly larger. If the
ARINC signal is out of the actual acceptance ranges, including the
nulls, the chip rejects the data.
HOLT INTEGRATED CIRCUITS
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HI-8282A
FUNCTIONAL DESCRIPTION (con't)
RECEIVER LOGIC OPERATION
3. Each data bit must follow its predecessor by not less than
8 samples and no more than 12 samples. In this manner the
bit rate is checked. With exactly 1MHz input clock frequency,
the acceptable data bit rates are as follows:
Figure 2 shows a block diagram of the logic section of each receiver.
BIT TIMING
HIGH SPEED
LOW SPEED
83K BPS
125K BPS
10.4K BPS
15.6K BPS
DATA BIT RATE MIN
DATA BIT RATE MAX
The ARINC 429 specification contains the following timing
specification for the received data:
BIT RATE
PULSE RISE TIME
PULSE FALL TIME
PULSEWIDTH
HIGH SPEED
LOW SPEED
100K BPS ± 1% 12K -14.5K BPS
1.5 ± 0.5 µsec
10 ± 5 µsec
1.5 ± 0.5 µsec
10 ± 5 µsec
5 µsec ± 5%
34.5 to 41.7 µsec
4. The Word Gap timer samples the Null shift register every
10 input clocks (80 for low speed) after the last data bit of a
valid reception. If the Null is present, the Word Gap counter is
incremented. A count of 3 will enable the next reception.
RECEIVER PARITY
Again the HI-8282A accepts signals that meet these specifications
and rejects outside the tolerances. The way the logic operation
achieves this is described below:
1. Key to the performance of the timing checking logic is an accurate 1MHz clock source.
Less than 0.1% error is
recommmended.
2. The sampling shift registers are 10 bits long and must show
three consecutive Ones, Zeros or Nulls to be considered valid
data. Additionally, for data bits, the One or Zero in the upper bits
of the sampling shift registers must be followed by a Null in the
lower bits within the data bit time. For a Null in the word gap,
three consecutive Nulls must be found in both the upper and
lower bits of the sampling shift register. In this manner the minimum pulse width is guaranteed.
The receiver parity circuit counts Ones received, including the
parity bit, ARINC bit 32. If the result is odd, then "0" will appear in
the 32nd bit.
RETRIEVING DATA
Once 32 valid bits are recognized, the receiver logic generates an
End of Sequence (EOS). If the receiver decoder is enabled and
the 9th and 10th ARINC bits match the control word program bits
or if the receiver decoder is disabled, then EOS clocks the data
ready flag flip flop to a "1", D/R1 or D/R2 (or both) will go low. The
data flag for a receiver will remain low until after both ARINC
bytes from that receiver are retrieved. This is accomplished by
activating EN with SEL, the byte selector, low to retrieve the first
byte and activating EN with SEL high to retrieve the second byte.
ENI retrieves data from receiver 1 and EN2 retrieves data from
receiver 2.
If another ARINC word is received, and a new EOS occurs before
the two bytes are retrieved, the data is overwritten by the new
word.
TO PINS
SEL
EN
MUX
CONTROL
32 TO 16 DRIVER
LATCH
ENABLE
CONTROL
32 BIT LATCH
CLOCK
OPTION
CONTROL
BIT BD14
D/R
DECODER
CONTROL
BITS
/
CLOCK
BITS 9 & 10
32 BIT SHIFT REGISTER
DATA
PARITY
CHECK
32ND
BIT
BIT
COUNTER
AND
END OF
SEQUENCE
BIT CLOCK
EOS
ONES
CLK
EOS
WORD GAP
WORD GAP
TIMER
SHIFT REGISTER
BIT CLOCK
END
START
NULL
SHIFT REGISTER
ZEROS
SHIFT REGISTER
SEQUENCE
CONTROL
ERROR
ERROR
DETECTION
FIGURE 2.
RECEIVER BLOCK DIAGRAM
HOLT INTEGRATED CIRCUITS
4
CLOCK
HI-8282A
TRANSMITTER
TRANSMITTER PARITY
A block diagram of the transmitter section is shown in Figure 3.
The parity generator counts the ONES in the 31-bit word. If the
BD12 control word bit is set low, the 32nd bit transmitted will make
parity odd. If the control bit is high the parity is even.
FIFO OPERATION
The FIFO is loaded sequentially by first pulsing PL1 to load byte 1
and then PL2 to load byte 2. The control logic automatically loads
the 31 bit word in the next available position of the FIFO. If TX/R,
the transmitter ready flag is high (FIFO empty), then 8 words,
each 31 bits long, may be loaded. If TX/R is low, then only the
available positions may be loaded. If all 8 positions are full, the
FIFO ignores further attempts to load data.
DATA TRANSMISSION
When ENTX goes high, enabling transmission, the FIFO
positions are incremented with the top register loading into the
data transmission shift register. Within 2.5 data clocks the first
data bit appears at either 429DO or 429DO. The 31 bits in the
data transmission shift register are presented sequentially to the
outputs in the ARINC 429 format with the following timing:
ARINC DATA BIT TIME
DATA BIT TIME
NULL BIT TIME
WORD GAP TIME
HIGH SPEED
10 Clocks
5 Clocks
5 Clocks
40 Clocks
LOW SPEED
80 Clocks
40 Clocks
40 Clocks
320 Clocks
The word counter detects when all loaded positions are
transmitted and sets the transmitter ready flag, TX/R, high.
SELF TEST
If the BD05 control word bit is set low, 429DO or 429DO become
inputs to the receiver bypassing the interface circuitry.
SYSTEMOPERATION
The two receivers are independent of the transmitter. Therefore,
control of data exchanges are strictly at the option of the user. The
only restrictions are:
1. The received data may be overwritten if not retrieved
within one ARINC word cycle.
2. The FIFO can store 8 words maximum and ignores
attempts to load addition data if full.
3. Byte 1 of the transmitter data must be loaded first.
4. Either byte of the received data may be retrieved first.
Both bytes must be retrieved to clear the data ready flag.
5. After ENTX, transmission enable, goes high it cannot go
low until TX/R, transmitter readyflag, goes high. Otherwise,
one ARINC word is lost during transmission.
HOLT INTEGRATED CIRCUITS
5
HI-8282A
will also be placed into the transmitter FIFO. SEL is then taken high
and EN is strobed again to place the upper byte of the data word on
the data bus. By strobing PL2 at the same time as EN, the second
byte will also be placed into the FIFO. The data word is now ready to
be transmitted according to the parity programmed into the control
word register.
REPEATER OPERATION
The repeater mode of operation allows a data word that has been
received by the HI-8282A to be placed directly into its FIFO for
transmission. After a 32-bit word has been shifted into the receiver
shift register, the D/R flag will go low. A logic "0" is placed on the SEL
line and EN is strobed. This is the same procedure as for normal
receiver operation and it places the lower byte (16) of the data word
on the data bus. By strobing PL1 at the same time as EN, the byte
In normal operation, either byte of a received data word may be read
from the receiver latches first by use of SEL input. During repeater
operation however, the lower byte of the data word must be read
first. This is necessary because, as the data is being read, it is also
being loaded into the FIFO and the transmitter FIFO is always
loaded with the lower byte of the data word first.
429DO
ARINC BIT
429DO
DATA
NULL
DATA
DATA
NULL
BIT 1
NEXT WORD
WORD GAP
BIT 32
BIT 31
BIT 30
NULL
VALID
DATA BUS
tCWSET
t CWHLD
CWSTR
t CWSTR
t END/R
t D/R
t EN
t SELEN
tSELEN
tENSEL
tENEN
tDATAEN
tD/REN
t DATAEN
BYTE 1 VALID
DATA BUS
tENSEL
tENDATA
HOLT INTEGRATED CIRCUITS
6
BYTE 2 VALID
t ENDATA
HI-8282A
BYTE 1 VALID
DATA BUS
tDWSET
BYTE 2 VALID
tDWSET
tDWHLD
tDWHLD
PL1
tPL12
t PL
PL2
tPL12
t PL
tTX/R
TX/R
PL2
tDTX/R
tPL2EN
TX/R
ENTX
ARINC BIT
tENDAT
429DO
or
429DO
429DI
tENTX/R
DATA
BIT 1
DATA
BIT 32
DATA
BIT 2
BIT 32
tEND/R
D/R
t D/R
t D/REN
t EN
tENEN
t EN
EN
t SELEN
SEL
tENSEL
DON'T CARE
DON'T CARE
tENPL
tSELEN
tPLEN
t ENSEL
PL1
tPLEN
t ENPL
PL2
t TX/R
TX/R
tTX/REN
t ENTX/R
ENTX
t DTX/R
tENDAT
BIT 1
429DO
BIT 32
t NULL
HOLT INTEGRATED CIRCUITS
7
HI-8282A
Supply Voltage Vcc
-0.3V to +7V
Power Dissipation
Voltage at ARINC Inputs
-29V to +29V
Operating Temperature Range: (Industrial)
(Military)
-40°C to +85°C
-55°C to +125°C
Storage Temperature Range:
-65°C to +150°C
Voltage at any other pin
-0.3V to Vcc +0.3V
DC Current Drain per input pin
10mA
500mW
NOTE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only.
Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Vcc = 5V ±5%, GND = 0V, TA = Operating Temperature Range (unless otherwise specified).
PARAMETER
ARINC INPUTS
-
CONDITIONS
SYMBOL
LIMITS
UNIT
MIN
TYP
MAX
6.5
-13.0
-2.5
10.0
-10.0
0
13.0
-6.5
2.5
27
27
429DI1 (A), 429DI1 (B), 429DI2 (A) & 429DI2 (B)
Differential Input Voltage:
ONE
ZERO
NULL
Input Resistance:
Input Current:
VIH
VIL
VNUL
ARINC Input Pins: Common
mode voltage less than ±5V
with respect to GND
Differential
To GND
To Vcc
RI
RG
RH
12
12
12
Input Sink
Input Source
IIH
IIL
-450
Differential
To GND
To Vcc
CI
CG
CH
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
Input Capacitance:
(Guaranteed but not tested)
Pins 2 to 3, 4 to 5
V
V
V
KΩ
KΩ
KΩ
200
µA
µA
20
20
20
pF
pF
pF
0.7
V
V
BI-DIRECTIONAL INPUTS - BD00 through BD15
Input Voltage:
Input Current:
2.1
1.5
-1.5
µA
µA
ALL OTHER INPUTS - SEL, EN1, EN2, PL1, PL2, ENTX, CWSTR, CLK & MR
Input Voltage:
Input Current:
Input Voltage HI
Input Voltage LO
VIH
VIL
Input Sink
Input Source
IIH
IIL
3.5
0.7
10
-20
V
V
µA
µA
OUTPUTS - D/R1, D/R2, BD00 through BD15, TX/R, 429DO, 429DO & TX CLK
Output Voltage:
Logic "1" Output Voltage
Logic "0" Output Voltage
VOH
VOL
IOH = -1.5mA
IOL = 1.1mA
2.7
Output Current:
(Bi-directional Pins)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
3.0
1.1
mA
mA
Output Current:
(All Other Outputs)
Output Sink
Output Source
IOL
IOH
VOUT = 0.4V
VOUT = VCC - 0.4V
2.6
1.1
mA
mA
Output Capacitance:
0.4
V
V
CO
15
pF
Standby Supply Current:
ICC1
20
mA
Operating Supply Current:
ICC2
20
mA
SUPPLY INPUT - VCC
HOLT INTEGRATED CIRCUITS
8
HI-8282A
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
SYMBOL
LIMITS
MIN
TYP
MAX
UNITS
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
tCWSTR
tCWSET
tCWHLD
130
130
0
ns
ns
ns
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
tD/R
tD/R
16
128
µs
µs
200
ns
ns
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
tD/REN
tEND/R
0
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
tSELEN
tENSEL
20
20
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
tENDATA
tDATAEN
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
tEN
tENEN
200
50
ns
ns
tPL
200
ns
tDWSET
tDWHLD
110
0
ns
ns
Spacing - PL1 or PL2
tPL12
0
ns
Delay - PL2 HIGH to TX/R LOW
tTX/R
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
Delay - ENTX HIGH to 429DO or 429D0: High Speed
Delay - ENTX HIGH to 429DO or 429D0: Low Speed
tENDAT
tENDAT
25
200
µs
µs
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
400
ns
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
ns
Delay - EN LOW to PL LOW
tENPL
0
ns
Hold - PL HIGH to EN HIGH
tPLEN
0
ns
tTX/REN
0
ns
tMR
200
ns
ns
ns
200
30
ns
ns
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
840
ns
TRANSMISSION TIMING
0
µs
REPEATER OPERATION TIMING
Delay - TX/R LOW to ENTX HIGH
Master Reset Pulse Width
ARINC Data Rate and Bit Timing
± 1%
HOLT INTEGRATED CIRCUITS
9
HI-8282A
ADDITIONAL HI-8282A PIN CONFIGURATIONS
(See page 1 for the 44-pin Plastic Quad Flat Pack )
44-PIN PLASTIC PLCC
44-PIN J-LEAD CERQUAD
HI-8282APJI
44-PIN CERAMIC LCC
HI-8282ACRI
40-PIN CERAMIC SIDE BRAZED DIP
HI-8282ACLI
HI-8282ACDI
HOLT INTEGRATED CIRCUITS
10
HI-8282A
PART
NUMBER
HI-8282ACDI
HI-8282ACDT
HI-8282ACDM
HI-8282APJI
HI-8282APJT
HI-8282APQI
HI-8282APQT
HI-8282ACLI
HI-8282ACLT
HI-8282ACLM
HI-8282ACRI
HI-8282ACRT
PACKAGE
DESCRIPTION
40 PIN CERAMIC SIDE BRAZED DIP
40 PIN CERAMIC SIDE BRAZED DIP
40 PIN CERAMIC SIDE BRAZED DIP
44 PIN PLASTIC J LEAD
44 PIN PLASTIC J LEAD
44 PIN PLASTIC QUAD FLAT PACK
44 PIN PLASTIC QUAD FLAT PACK
44 PIN CERAMIC LEADLESS CHIP CARRIER
44 PIN CERAMIC LEADLESS CHIP CARRIER
44 PIN CERAMIC LEADLESS CHIP CARRIER
44 PIN CERQUAD
44 PIN CERQUAD
TEMPERATURE
RANGE
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
-55°C TO +125°C
-40°C TO +85°C
-55°C TO +125°C
HOLT INTEGRATED CIRCUITS
11
FLOW BURN
IN
I
NO
T
NO
M
YES
I
NO
T
NO
I
NO
T
NO
I
NO
T
NO
M
YES
I
NO
T
NO
LEAD
FINISH
GOLD
GOLD
SOLDER
SOLDER
SOLDER
SOLDER
SOLDER
GOLD
GOLD
SOLDER
SOLDER
SOLDER
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
40-PIN CERAMIC SIDE-BRAZED DIP
Package Type: 40C
2.020 MAX
(51.308 MAX)
.595 ± .010
(15.113 ± .254)
.610 ± .010
(15.494 ± .254)
.050 TYP
(1.270 TYP)
.225 MAX
(5.715 MAX)
.125 MIN
(3.175 MIN)
.018 TYP
(.457 TYP)
.085 ± .009
(2.159 ± .229)
.100 BSC
(2.540 BSC)
.600 ± .010
(15.240 ± .254)
.010 + .002/−.001
(.254 + .051/−.025)
44-PIN J-LEAD CERQUAD
Package Type: 44U
2 1 44 43
.688 ± .005
(17.475 ± .127)
MAX.
SQ.
.650 ± .010
(16.510 ± .254)
SQ.
.200
(5.080)MAX.
.039 ± .005
(.990 ± .127)
.019 ± .002
(.483 ± .051)
.050
TYP.
(1.270)
.100 ± .007
(2.540 ± .178)
HOLT INTEGRATED CIRCUITS
12
.620 ± .012
(15.748 ± .305)
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN PLASTIC PLCC
Package Type: 44J
PIN NO. 1
PIN NO. 1 IDENT
.045 x 45°
.045 x 45°
.050 ± .005
(1.27 ± .127)
.690 ± .005
(17.526 ± .127)
SQ.
.653 ± .004
(16.586 ± .102)
SQ.
.031± .005
(.787 ± .127)
.017 ± .004
(.432 ± .102)
SEE DETAIL
A
.009
.011
.172 ± .008
(4.369 ± .203)
DETAIL A
.610 ± .020
(15.494± .508)
.015 ± .002
(.381 ± .051)
.020 MIN
(.508 ΜΙΝ)
R .025
.045
44-PIN PLASTIC QUAD FLAT PACK (PQFP)
Package Type: 44PQS
.007 MAX.
(.17)
.0315 BSC
(.80 BSC)
.547 ± .010
(13.90 ± .25)
SQ.
.394 ± .004
(10.0 ± .10)
SQ.
.014 ± ..002
(.35 ± .05)
.035 +.006 / -.004
(.88 +.15 / -.10)
.012
TYP.
(.30 R)
See Detail A
.097
MAX.
(2.45)
.079 +.004 / -.006
(2.00 +.10 / -.15)
0° ≤ Θ ≤ 7°
.008
TYP.
(.20 R)
HOLT INTEGRATED CIRCUITS
13
Detail A
HI-8282A PACKAGE DIMENSIONS
inches (millimeters)
44-PIN CERAMIC LEADLESS CHIP CARRIER
Package Type: 44S
.020 INDEX
(.508 INDEX)
PIN 1
.040 x 45° 3 PLCS
(1.016 x 45° 3 PLCS)
.075 ± .004
(1.905 ± .101)
.050 ± .005
(1.270 ± .127)
.651 ± .011
(16.535 ± .279)
SQ.
.050 BSC
(1.270 BSC)
.025 ± .003
(.635 ± .076)
.009R ± .006
(.229R ± .152)
.092 ± .028
(2.336 ± .711)
HOLT INTEGRATED CIRCUITS
14
.326 ± .006
(8.280 ± .152)
PIN 1