® N HIP5063 nt CT DU ceme O PR epla ETE e d R L SO nd O B o mme ec oR August 1998 File Number Power Control IC Single Chip Power Supply Features The HIP5063 is a complete power control IC, incorporating both the high power DMOS transistor, CMOS logic and low level analog circuitry on the same Intelligent Power IC. • 60V, 10A On-chip DMOS Transistor • Single Chip Current Mode Control IC • Thermal Protection • 1MHz Operation - External Clock This IC allows the user maximum flexibility in implementing high frequency current controlled power supplies and other power sources. • Output Rise and Fall Times ~ 3ns • Simple Implementation of High-Speed Current Mode Controlled Regulators and Power Amplifiers Special power transistor current sensing circuitry is incorporated that minimizes losses due to the monitoring circuitry. Over-temperature detection circuitry is incorporated within the IC to monitor the chip temperature. • Designed for 10V to 45V Operation Applications As a result of the power DMOS transistor’s current and voltage capability (10A and 60V), power supplies with output power capability up to 100 watts are possible. • Single Chip Power Supplies • Current Mode PWM Applications • Distributed Power Supplies Ordering Information PART NUMBER 3209.2 • Multiple Output Converters TEMPERATURE RANGE PACKAGE HIP5063DY 0oC to +85oC 21 Pad Chip HIP5063DW 0oC to +85oC Wafer • Wideband Power Amplifiers for Motor Control (11) DGND (10) AGND (9) IRFI (8) IRFO (7) TMON (6) COOL (5) CLCK (4) FLLN (3) VDDD (2) VDDA (1) VCMP Chip (12) VDDP S (13) D (14) S (15) D (16) S (17) D (18) S (19) D (20) VDDP (21) NOTE: Unused pads are for trim and test. 122 mils x 126 mils (3.1mm x 3.2mm) 1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2002. All Rights Reserved HIP5063 Simplified Block Diagram 4µH VIN = 36V 3µH 0.66µF 0.1µF 12V 3.8µH VDDA FLLN 1MHz CLOCK VDDD CONTROL LOGIC CLCK VDDP 5.1V OUTPUT D 0.88µF 0.1µF GATE DRIVERS 33µF S TMON THERMAL MONITOR HIP5063 + COOL - VCMP AGND DGND IRFI 5.1V REF + IRFO TYPICAL SEPIC APPLICATION CONFIGURATION Functional Block Diagram CLCK VDDD VDDA VDDA VDDP BIAS CIRCUITS DRAIN 50µA S FLIP-FLOP FLLN R Q FAST RESET GATE DRIVERS THERMAL MONITOR TMON 18KΩ CONTROL & BLANKING LOGIC CURRENT MONITORING AMP SOURCE COOL + VCMP - IREF AGND IRFO IRFI EXTERNAL CURRENT SCALING RESISTOR IPEAK(DMOS DRAIN CURRENT) = 4500 x IREF (mA) 2 DGND HIP5063 Absolute Maximum Ratings Thermal Information DMOS Drain Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 60V DMOS Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20A DC Logic Supply. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V Output Voltage, Logic Outputs . . . . . . . . . . . . . . . . . . . -0.3V to 16V Input Voltage, Analog and Logic. . . . . . . . . . . . . . . . . . -0.3V to 16V Operating Junction Temperature Range . . . . . . . . . .0oC to +110oC Storage Temperature Range . . . . . . . . . . . . . . . . . -55oC to +150oC Thermal Resistance θJC (Solder Mounted to . . . . . . . . . . . . . . . . . . . . . . . . . 3oC/W Max 0.050” Thick Copper Heat Sink) Maximum Junction Temperature. . . . . . . . . . . . . . . . . . . . . . +110oC (Controlled By Thermal Shutdown Circuit) CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Electrical Specifications VDDA = VDDD = VDDP = 12V, TJ = 0oC to +110oC; Unless Otherwise Specified SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNITS External Clock Input = 1MHz - 14 - mA DEVICE PARAMETERS I+ Supply Current DMOS TRANSISTORS rDS(on) Drain-Source On-State Resistance I Drain = 5A, TJ = +25oC - - 0.13 Ω IDSS Drain-Source Leakage Current Drain to Source Voltage = 60V - 1 100 µA - - 125 mV CURRENT CONTROLLED PWM |VIO| VCMP Buffer Offset Voltage (VCMP - VIRFO) IRFO = 0mA to -5mA, VCMP = 0.2V to 7.6V IGAIN IPEAK (DMOSDRAIN)/IIRFI ∆I (DMOSDRAIN)/∆t = 1A/ms 3.8 - 4.9 A/mA RIRFI IRFI Resistance to GND IRFI = 2mA 150 - 360 Ω Current Comparator Response Time (Note 1) ∆I (DMOSDRAIN)/∆t > 1A/ms - 30 - ns tRS MCPW Minimum Controllable Pulse Width (Note 1) 25 50 100 ns MCPI Minimum Controllable DMOS Peak Current (Note 1) 200 400 800 mA CLOCK VTH CLCK CLCK Input Threshold Voltage 4 - 8 V VTH FLLN FLLN Input Threshold Voltage 4 - 8 V VFLLN = 0V -70 -50 -30 µA Substrate Temperature for Thermal Monitor to Trip (Note 1) TMON pin open 105 - 135 oC COOL Leakage Current VCOOL = 12V - - 1 µA COOL Low-State Voltage ICOOL = 2mA, TJ > +125oC - - 0.4 V IFLLN FLLN Pull-Up Current THERMAL MONITOR TEMP ILEAK COOL VCOOL NOTE: 1. Determined by design, not a measured parameter. 3 HIP5063 Pin Descriptions PAD NUMBER DESIGNATION DESCRIPTION 1 VCMP This is the input terminal from an external error amplifier. A MOS input voltage follower buffers this terminal. The buffer output is the IRFO terminal. The external error amplifier may be either an operational amplifier or a transconductance amplifier like the CA3080. This node may be used for both gain and frequency compensation of the control loop. 2 VDDA This is the analog supply input. An external 12V supply is required. 3 V DDD Voltage input for the chip’s digital circuits. 4 FLLN One pad of two clocking terminals. This terminal has an external 50µA pull-up current that allows the terminal to be floated or be left open. With FLLN high, (open or tied to VDDD), the ON cycle will start wiith the falling edge of the CLCK input. With FLLN low or grounded, the DMOS ON cycle will start on the rising edge of the CLCK input. 5 CLCK The other clock input pad. An external clock is applied to this terminal. This terminal has no pullup current or resistance. See FLLN above for phasing information. 6 COOL Over-temperature indication is provided at this pad. When the chip temperature is below the thermal threshold, the open drain DMOS transistor is in the high impedance state. When the thermal threshold is exceeded, COOL is held low. 7 TMON This is the thermal shut down pad than can be used to disable the thermal shutdown circuit. By returning this pad to V DDA or 12V the function is disabled. Returning this pad to ground will enable the thermal monitor function. Thermal threshold occurs at a nominal junction temperature of +125oC. 8 IRFO A resistor placed between this pad and IRFI converts the VCMP signal to a reference current for the current sense comparator. The cycle by cycle peak current is set by the value to this resistor according the the equation: IPEAK = 4500 x VCMP/R. Where IPEAK is in amperes and R is the value of the external resistor in ohms. A maximum VCMP of 8V and a resistor of 1800Ω will keep the drain current below the absolute maximum specification of 20A. 9 IRFI See IRFO. 10 AGND Analog ground. 11 DGND Digital ground. 12 & 21 VDDP These pads are used to decouple the high current pulses to the output driver transistors. The capacitor should be at least a 0.1µF chip capacitor placed close to this pad and the DMOS source pads. 13, 15, 17, 19 S Source pads of the DMOS power transistor. 14, 16, 18, 20 D Drain pads of the DMOS power transistor. 4