HM6268 Series Maintenance only 4096-word × 4-bit High-Speed CMOS Static RAM Features Pin Arrangement • Single 5 V supply and high density 20-pin package • High speed: fast access time 25/35/45 ns (max) • Low power — Active: 250 mW (typ) — Standby: 100 µW (typ), 5 µW (typ) (L-version) • Completely static memory: no clock or timing strobe required • Equal access and cycle times • Directly TTL compatible—all inputs and outputs • Battery back-up operation capability (L-version) A4 A5 A6 A7 A8 A9 A10 A11 CS VSS 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 VCC A3 A2 A1 A0 I/O1 I/O2 I/O3 I/O4 WE (Top view) Ordering Information Type No. Access time Package HM6268P-25 25 ns 300-mil 20-pin, plastic DIP (DP-20N) HM6268P-35 35 ns HM6268P-45 45 ns HM6268LP-25 25 ns HM6268LP-35 35 ns HM6268LP-45 45 ns Note: This device is not available for new application. 1 HM6268 Series HM6268 Series Block Diagram A10 A4 Row decoder A5 A6 A7 A8 I/O1 I/O3 VSS Column I/O Input data control I/O2 VCC Memory array 64 × 256 Column decoder I/O4 A0 A1 A2 A3 A11 A9 CS WE Truth Table CS WE Mode VCC current I/O pin Cycle H x Not Selected ISB, ISB1 High-Z — L H Read ICC Dout Read cycle L L Write ICC Din Write cycle Absolute Maximum Ratings Parameter Symbol Rating Unit Voltage on any pin relative to VSS VT –0.5 *1 to +7.0 V Power dissipation PT 1.0 W Operating temperature Topr 0 to + 70 °C Storage temperature Tstg –55 to +125 °C Temperature under bias Tbias –10 to + 85 °C Note: 2 1. –3.5 V for pulse width ≤ 10 ns. HM6268 Series HM6268 Series Recommended DC Operating Conditions (Ta = 0 to + 70°C) Parameter Symbol Min Typ Max Unit Supply voltage VCC 4.5 5.0 5.5 V VSS 0 0 0 V Input high (logic 1) voltage VIH 2.2 — 6.0 V Input low (logic 0) voltage VIL –0.5 *1 — 0.8 V Note: 1. –3.0 V for pulse width ≤ 10 ns. DC Characteristics (VCC = 5 V ± 10%, VSS = 0 V, Ta = 0 to +70°C) Parameter Symbol Min Typ *1 Max Unit Test condition Input leakage current | ILI | — — 2.0 µA VCC = 5.5 V, Vin = VSS to VCC Output leakage current | ILO | — — 2.0 µA CS = VIH, VI/O = VSS to VCC Operating power supply current ICC — 50 *3 90 mA CS = VIL, II/O = 0 mA, min. cycle Standby power supply current ISB — 15 25 mA CS = VIH, min. cycle — 0.02 2.0 mA — 1 *2 50 *2 µA CS ≥ VCC – 0.2 V, 0 V ≤ VIN ≤ 0.2 V or VCC – 0.2 V ≤ VIN Standby power supply current (1) ISB1 Output low voltage VOL — — 0.4 V IOL = 8 mA Output high voltage VOH 2.4 — — V IOH = –4.0 mA Notes: 1. Typical limits are at VCC = 5.0 V, Ta = +25°C and specified loading 2. This characteristic is guaranteed only for L-version. 3. 40 mA typical for 45 ns version. Capacitance (Ta = 25°C, f = 1.0 MHz) *1 Parameter Symbol Test conditions Min Max Unit Input capacitance Cin Vin = 0 V — 6 pF Input/output capacitance CI/O VI/O = 0 V — 9 pF Note: 1. These parameters are sampled and not 100% tested. 3 HM6268 Series HM6268 Series AC Characteristics (VCC = 5 V + 10%, Ta = 0 to +70°C, unless otherwise noted) AC Test Conditions: • • • • Input pulse levels: VSS to 3.0 V Input rise and fall times: 5 ns Input and output timing reference levels: 1.5 V Output load: See figure Output Load 5V 5V 480 Ω Dout 255 Ω 480 Ω Dout 255 Ω 30 pF *1 Output load (A) 5 pF *1 Output load (B) (tHZ , tLZ, tWZ, and tOW) Note: 1. Including scope and jig Read Cycle Parameter HM6268-25 HM6268-35 HM6268-45 —————— —————— —————— Symbol Min Max Min Max Min Max Unit Read cycle time tRC 25 — 35 — 45 — ns Address access time tAA — 25 — 35 — 45 ns Chip select access time tACS — 25 — 35 — 45 ns Output hold from address change tOH 5 — 5 — 5 — ns Chip selection to output in low-Z tLZ *1 10 — 10 — 10 — ns Chip deselection to output in high-Z tHZ *1 0 15 0 20 0 20 ns Chip selection to power up time tPU 0 — 0 — 0 — ns Chip deselection to power down time tPD — 25 — 25 — 30 ns Note: 4 1. Transition is measured +200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. HM6268 Series HM6268 Series Read Timing Waveform (1) tRC Address tAA tOH tOH Valid Data Dout Notes: 1. WE is high for read cycle. 2. Device is continuously selected, CS = VIL Read Timing Waveform (2) tRC CS tLZ Dout VCC Supply current High impedance tPU ICC tHZ tACS 50% Valid Data tPD High impedance 50% ISB Notes: 1. WE is high for read cycle. 2. Address valid prior to or coincident with CS transistion low. 5 HM6268 Series HM6268 Series Write Cycle Parameter HM6268-25 HM6268-35 HM6268-45 —————— —————— —————— Symbol Min Max Min Max Min Max Unit Write cycle time tWC 25 — 35 — 45 — ns Chip selection to end of write tCW 20 — 30 — 40 — ns Address valid to end of write tAW 20 — 30 — 40 — ns Address setup time tAS 0 — 0 — 0 — ns Write pulse width tWP 20 — 30 — 35 — ns Write recovery time tWR 0 — 0 — 0 — ns Data valid to end of write tDW 12 — 20 — 20 — ns Data hold time tDH 0 — 0 — 0 — ns Write enabled to output in high-Z tWZ *1 0 8 0 10 0 15 ns Output active from end of write tOW *1 0 — 0 — 0 — ns Note: 6 1. Transition is measured +200 mV from steady state voltage with load (B). These parameters are sampled and not 100% tested. HM6268 Series HM6268 Series Write Timing Waveform (1) (WE Controlled) tWC Address tCW CS tAW tAS tWR *2 tWP *1 WE tDW Din Dout tDH *4 Valid Data tWZ *4 *3 High impedance tOH *5 tOW Notes: 1. A write cycle occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. During this period, I/O pins are in the output state so input signals of opposite phase to the outputs must not be applied. 4. If CS is low during this period, I/O pins are in the output state, so data input signals of opposite phase to the outputs must not be applied. 5. Dout has the same phase as write data in this write cycle, if tWR is long enough. 7 HM6268 Series HM6268 Series Write Timing Waveform (2) (CS Controlled) tWC Address tAW tAS tWR *2 tCW CS tWP *1 WE tDW Din Dout tDH Valid Data High impedance *3 Notes: 1. A write cycle occurs during the overlap of a low CS and a low WE (tWP). 2. tWR is measured from the earlier of CS or WE going high to the end of the write cycle. 3. If the CS low transition occurs simultaneously with the WE low transition or after the WE transition, the output buffers remain in a high impedance state. 8 HM6268 Series HM6268 Series Low VCC Data Retention Characteristics (0°C ≤ Ta ≤ 70°C) These characteristics are guaranteed only for L-version. Parameter Symbol Min Typ Max Unit Test conditions VCC for data retention VDR 2.0 — — V Data retention current ICCDR — — 30 * 2 20 * 3 µA CS ≥ VCC – 0.2 V, VIN ≥ VCC – 0.2 V, or 0 V ≤ VIN ≤ 0.2 V Chip deselect to data retention time tCDR 2.0 — — ns Operation recovery time tR tRC * 1 — — ns Notes: See retention waveform 1. Read cycle time 2. VCC = 3.0 V 3. VCC = 2.0 V Low VCC Data Retention Waveform Data retention mode VCC 4.5 V 2.2 V VDR tR tCDR VDR CS ≥ VCC – 0.2 V CS 0V 9