HOLTEK HT46C23

HT46R23/HT46C23
A/D Type 8-Bit MCU
Features
· Operating voltage:
· Up to 0.5ms instruction cycle with 8MHz system clock
fSYS=4MHz: 2.2V~5.5V
fSYS=8MHz: 3.3V~5.5V
at VDD=5V
· 8-level subroutine nesting
· 23 bidirectional I/O lines (max.)
· 8 channels 10-bit resolution A/D converter
· 1 interrupt input shared with an I/O line
· 2-channel 8-bit PWM output shared with two I/O lines
· 16-bit programmable timer/event counter with
· Bit manipulation instruction
overflow interrupt and 7-stage prescaler
· 15-bit table read instruction
· On-chip crystal and RC oscillator
· 63 powerful instructions
· Watchdog Timer
· All instructions in one or two machine cycles
· 4096´15 program memory
· Low voltage reset function
· 192´8 data memory RAM
· I2C Bus (slave mode)
· Supports PFD for sound generation
· 24/28-pin SKDIP/SOP packages
· HALT function and wake-up feature reduce power
consumption
General Description
The advantages of low power consumption, I/O flexibility, programmable frequency divider, timer functions,
oscillator options, multi-channel A/D Converter, Pulse
Width Modulation function, I2C interface, HALT and
wake-up functions, enhance the versatility of these devices to suit a wide range of A/D application possibilities
such as sensor signal processing, motor driving, industrial control, consumer products, subsystem controllers,
etc.
The HT46R23/HT46C23 are 8-bit, high performance,
RISC architecture microcontroller devices specifically
designed for A/D applications that interface directly to
analog signals, such as those from sensors. The mask
version HT46C23 is fully pin and functionally compatible
with the OTP version HT46R23 device.
I2C is a trademark of Philips Semiconductors.
Rev. 1.60
1
May 3, 2004
HT46R23/HT46C23
Block Diagram
P A 5 /IN T
In te rru p t
C ir c u it
T M R
S T A C K
P ro g ra m
R O M
M
T M R C
P ro g ra m
C o u n te r
U
P r e s c a le r
IN T C
P A 3 /P F D
M
M P
U
W D T
P r e s c a le r
D A T A
M e m o ry
X
P W
P A 4
M
W D T
U
/4
X
R C
P o rt D
P D 0 /P W
P D
O S C
M 0 ~ P D 1 /P W
M 1
M U X
In s tr u c tio n
D e c o d e r
8 -C h a n n e l
A /D C o n v e rte r
S T A T U S
A L U
P B C
S h ifte r
T im in g
G e n e ra to r
P A 3 , P A 5
S
S
A C C
C 1
P o rt B
P B 0 /A N 0 ~ P B 7 /A N 7
P B
P A C
O S
R E
V D
V S
Y S
M
P D C
O S C 2
Y S
P A 4 /T M R
X
fS
In s tr u c tio n
R e g is te r
fS
P A
P A
P A
P A
P A
P A
P o rt A
P A
L V R
I2 C B u s
S la v e M o d e
D
P C
P o rt C
0 ~
3 /
4 /
5 /
6 /
7 /
P
P F
T M
IN
S D
S C
A 2
D
R
T
A
L
P C 0 ~ P C 4
P C C
Pin Assignment
1
2 8
P B 6 /A N 6
P B 4 /A N 4
2
2 7
P B 7 /A N 7
P B 5 /A N 5
1
2 4
P B 6 /A N 6
P A 3 /P F D
3
2 6
P A 4 /T M R
P B 4 /A N 4
2
2 3
P B 7 /A N 7
P A 2
4
2 5
P A 5 /IN T
P A 3 /P F D
3
2 2
P A 4 /T M R
P A 1
5
2 4
P A 6 /S D A
P A 2
4
2 1
P A 5 /IN T
P A 0
6
2 3
P A 7 /S C L
P A 1
5
2 0
P A 6 /S D A
P B 3 /A N 3
7
2 2
O S C 2
P A 0
6
1 9
P A 7 /S C L
P B 2 /A N 2
8
2 1
O S C 1
P B 3 /A N 3
7
1 8
O S C 2
P B 1 /A N 1
9
2 0
V D D
P B 2 /A N 2
8
1 7
O S C 1
P B 0 /A N 0
1 0
1 9
R E S
P B 1 /A N 1
9
1 6
V D D
V S S
1 1
1 8
P D 1 /P W M 1
P B 0 /A N 0
1 0
1 5
R E S
P C 0
1 2
1 7
P D 0 /P W M 0
V S S
1 1
1 4
P D 0 /P W M 0
P C 1
1 3
1 6
P C 4
P C 0
1 2
1 3
P C 1
P C 2
1 4
1 5
P C 3
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 4 S K D IP -A /S O P -A
Rev. 1.60
P B 5 /A N 5
H T 4 6 R 2 3 /H T 4 6 C 2 3
2 8 S K D IP -A /S O P -A
2
May 3, 2004
HT46R23/HT46C23
Pad Assignment
HT46C23
P A 1
P A 2
P A 3 /P F D
P B 4 /A N 4
P B 5 /A N 5
P B 6 /A N 5
P B 7 /A N 7
P A 4 /T M R
P A 5 /IN T
P A 6 /S D A
P A 0
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
2 5
2 4
1
2
P B 3 /A N 3
P B 1 /A N 1
2 2
O S C 2
2 1
O S C 1
4
P B 0 /A N 0
5
1 9
1 2
1 3
P C 3
P C 4
P D 0 /P W M 0
1 4
1 5
P D 1 /P W M 1
1 1
R E S
1 0
P C 2
9
P C 1
7
8
P C 0
6
V S S
V S S
P A 7 /S C L
(0 , 0 )
3
P B 2 /A N 2
2 3
2 0
V D D
V D D
1 8
1 7
1 6
T E S T 3
T E S T 2
T E S T 1
* The IC substrate should be connected to VSS in the PCB layout artwork.
Pad Description
Pad Name
PA0~PA2
PA3/PFD
PA4/TMR
PA5/INT
PA6/SDA
PA7/SCL
I/O
Option
Description
I/O
Pull-high
Wake-up
PA3 or PFD
I/O or Serial Bus
Bidirectional 8-bit input/output port. Each bit can be configured as wake-up
input by options. Software instructions determine the CMOS output or
Schmitt trigger input with or without pull-high resistor (determined by
pull-high options: bit option). The PFD, TMR and INT are pin-shared with
PA3, PA4 and PA5, respectively. Once the I2C Bus function is used, the internal registers related to PA6 and PA7 can not be used.
PB0/AN0
PB1/AN1
PB2/AN2
PB3/AN3
PB4/AN4
PB5/AN5
PB6/AN6
PB7/AN7
I/O
Pull-high
Bidirectional 8-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determined by pull-high: port option) or A/D input.
Once a PB line is selected as an A/D input (by using software control), the
I/O function and pull-high resistor are disabled automatically.
PC0~PC4
I/O
Pull-high
Bidirectional 5-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without pull-high resistor (determine by pull-high option: port option).
Rev. 1.60
3
May 3, 2004
HT46R23/HT46C23
Pad Name
Option
Description
I/O
Pull-high
I/O or PWM
Bidirectional 2-bit input/output port. Software instructions determine the
CMOS output, Schmitt trigger input with or without a pull-high resistor (determined by pull-high option: port option). The PWM0/PWM1 output function are pin-shared with PD0/PD1 (dependent on PWM options).
RES
I
¾
Schmitt trigger reset input. Active low.
VDD
¾
¾
Positive power supply
VSS
¾
¾
Negative power supply, ground.
OSC1
OSC2
I
O
Crystal
or RC
TEST1
TEST2
TEST3
I
¾
PD0/PWM0
PD1/PWM1
I/O
OSC1, OSC2 are connected to an RC network or a Crystal (determined by
options) for the internal system clock. In the case of RC operation, OSC2 is
the output terminal for 1/4 system clock.
TEST mode input pin.
It disconnects in normal operation.
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
VDD
VDD
IDD1
Operating Voltage
Operating Current
(Crystal OSC)
Typ.
Max.
Unit
¾
fSYS=4MHz
2.2
¾
5.5
V
¾
fSYS=8MHz
3.3
¾
5.5
V
3V
No load, fSYS=4MHz
ADC disable
¾
0.6
1.5
mA
¾
2
4
mA
¾
0.8
1.5
mA
¾
2.5
4
mA
¾
3
5
mA
¾
¾
5
mA
¾
¾
10
mA
¾
¾
1
mA
¾
¾
2
mA
5V
3V
Operating Current
(RC OSC)
5V
IDD3
Operating Current
5V
ISTB1
Standby Current
(WDT Enabled)
3V
IDD2
Min.
Conditions
No load, fSYS=4MHz
ADC disable
No load, fSYS=8MHz
ADC disable
No load, system HALT
5V
3V
Standby Current
(WDT Disabled)
5V
VIL1
Input Low Voltage for I/O Ports,
TMR and INT
¾
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports,
TMR and INT
¾
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RES)
¾
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RES)
¾
¾
0.9VDD
¾
VDD
V
ISTB2
Rev. 1.60
No load, system HALT
4
May 3, 2004
HT46R23/HT46C23
Test Conditions
Symbol
Parameter
VLVR
Low Voltage Reset
IOL
I/O Port Sink Current
IOH
RPH
VDD
Conditions
¾
¾
Min.
Typ.
Max.
Unit
2.7
3
3.3
V
3V
VOL=0.1VDD
4
8
¾
mA
5V
VOL=0.1VDD
10
20
¾
mA
3V
VOH=0.9VDD
-2
-4
¾
mA
5V
VOH=0.9VDD
-5
-10
¾
mA
3V
¾
20
60
100
kW
5V
¾
10
30
50
kW
I/O Port Source Current
Pull-high Resistance
VAD
A/D Input Voltage
¾
¾
0
¾
VDD
V
EAD
A/D Conversion Error
¾
¾
¾
±0.5
±1
LSB
IADC
Additional Power Consumption
if A/D Converter is Used
3V
¾
0.5
1
mA
¾
1.5
3
mA
¾
5V
A.C. Characteristics
Ta=25°C
Test Conditions
Symbol
Parameter
fSYS
fTIMER
tWDTOSC
System Clock
Timer I/P Frequency
(TMR)
Min.
Typ.
Max.
Unit
Conditions
VDD
¾
2.2V~5.5V
400
¾
4000
kHz
¾
3.3V~5.5V
400
¾
8000
kHz
¾
2.2V~5.5V
0
¾
4000
kHz
¾
3.3V~5.5V
0
¾
8000
kHz
3V
¾
45
90
180
ms
5V
¾
32
65
130
ms
¾
1
¾
¾
ms
¾
1024
¾
*tSYS
Watchdog Oscillator Period
tRES
External Reset Low Pulse Width
¾
tSST
System Start-up Timer Period
¾
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
tAD
A/D Clock Period
¾
¾
1
¾
¾
ms
tADC
A/D Conversion Time
¾
¾
¾
76
¾
tAD
tADCS
A/D Sampling Time
¾
¾
¾
32
¾
tAD
tIIC
I2C Bus Clock Period
¾
64
¾
¾
*tSYS
Wake-up from HALT
Connect to external
pull-high resistor 2kW
Note: *tSYS=1/fSYS
Rev. 1.60
5
May 3, 2004
HT46R23/HT46C23
Functional Description
Execution Flow
When executing a jump instruction, conditional skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from
subroutine, the PC manipulates the program transfer by
loading the address corresponding to each instruction.
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of four system clock cycles.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed with the next instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each instruction to effectively execute in a cycle. If an instruction
changes the program counter, two cycles are required to
complete the instruction.
The lower byte of the program counter (PCL) is a readable and writeable register (06H). Moving data into the
PCL performs a short jump. The destination will be
within 256 locations.
Program Counter - PC
The program counter (PC) controls the sequence in
which the instructions stored in program PROM are executed and its contents specify full range of program
memory.
When a control transfer takes place, an additional
dummy cycle is required.
After accessing a program memory word to fetch an instruction code, the contents of the program counter are incremented by one. The program counter then points to the
memory word containing the next instruction code.
The program memory is used to store the program instructions which are to be executed. It also contains
data, table, and interrupt entries, and is organized into
4096´15 bits, addressed by the program counter and table pointer.
S y s te m
O S C 2 (R C
C lo c k
T 1
T 2
T 3
T 4
Program Memory - ROM
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
External Interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter Overflow
0
0
0
0
0
0
0
0
1
0
0
0
A/D Converter Interrupt
0
0
0
0
0
0
0
0
1
1
0
0
I2C Bus Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
PC+2
Program Counter
Note:
*11~*0: Program counter bits
#11~#0: Instruction code bits
Rev. 1.60
S11~S0: Stack register bits
@7~@0: PCL bits
6
May 3, 2004
HT46R23/HT46C23
0 0 0 H
0 0 4 H
0 0 8 H
address is match or completed one byte of data transfer, and if the interrupt is enable and the stack is not
full, the program begins execution at location 010H.
D e v ic e In itia liz a tio n P r o g r a m
E x te r n a l In te r r u p t S u b r o u tin e
· Table location
Any location in the PROM space can be used as
look-up tables. The instructions ²TABRDC [m]² (the
current page, 1 page=256 words) and ²TABRDL [m]²
(the last page) transfer the contents of the lower-order
byte to the specified data memory, and the
higher-order byte to TBLH (08H). Only the destination
of the lower-order byte in the table is well-defined, the
other bits of the table word are transferred to the lower
portion of TBLH, and the remaining 1 bit is read as ²0².
The Table Higher-order byte register (TBLH) is read
only. The table pointer (TBLP) is a read/write register
(07H), which indicates the table location. Before accessing the table, the location must be placed in
TBLP. The TBLH is read only and cannot be restored.
If the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of the TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
Errors can occur. In other words, using the table read
instruction in the main routine and the ISR simultaneously should be avoided. However, if the table read
instruction has to be applied in both the main routine
and the ISR, the interrupt is supposed to be disabled
prior to the table read instruction. It will not be enabled
until the TBLH has been backed up. All table related
instructions require two cycles to complete the operation. These areas may function as normal program
memory depending upon the requirements.
T im e r /E v e n t C o u n te r In te r r u p t S u b r o u tin e
0 0 C H
A /D
0 1 0 H
C o n v e r te r In te r r u p t S u b r o u tin e
I2C
n 0 0 H
P ro g ra m
M e m o ry
B U S In te r r u p t S u b r o u tin e
L o o k - u p T a b le ( 2 5 6 w o r d s )
n F F H
F 0 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program Memory
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialization. After
chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the external interrupt service
program. If the INT input pin is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter (PC) only. The
stack is organized into 8 levels and is neither part of the
data nor part of the program space, and is neither readable nor writeable. The activated level is indexed by the
stack pointer (SP) and is neither readable nor writeable.
At a subroutine call or interrupt acknowledgment, the
contents of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt routine,
signaled by a return instruction (RET or RETI), the program counter is restored to its previous value from the
stack. After a chip reset, the SP will point to the top of the
stack.
· Location 008H
This area is reserved for the timer/event counter interrupt service program. If a timer interrupt results from a
timer/event counter overflow, and if the interrupt is enabled and the stack is not full, the program begins execution at location 008H.
· Location 00CH
This area is reserved for the A/D converter interrupt
service program. If an A/D converter interrupt results
from an end of A/D conversion, and if the interrupt is
enabled and the stack is not full, the program begins
execution at location 00CH.
· Location 010H
This area is reserved for the I2C Bus interrupt service
program. If the I2C Bus interrupt resulting from a slave
Table Location
Instruction
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note:
*11~*0: Table location bits
@7~@0: Table pointer bits
Rev. 1.60
P11~P8: Current program counter bits
7
May 3, 2004
HT46R23/HT46C23
The memory pointer registers (MP0 and MP1 are 8-bit
registers).
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledgment will be inhibited. When the stack
pointer is decremented (by RET or RETI), the interrupt
will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily.
In a similar case, if the stack is full and a ²CALL² is subsequently executed, stack overflow occurs and the first
entry will be lost (only the most recent 8 return addresses are stored).
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
0 0 H
Data Memory - RAM
The data memory is designed with 224´8 bits. The
data memory is divided into two functional groups: special function registers and general purpose data memory (192´8). Most are read/write, but some are read
only.
M P 0
0 2 H
In d ir e c t A d d r e s s in g R e g is te r 1
0 3 H
M P 1
0 4 H
0 5 H
The special function registers include the indirect addressing registers (00H;02H), timer/event counter
higher-order byte register (TMRH;0CH), timer/event
counter low-order byte register (TMRL;0DH),
timer/event counter control register (TMRC;0EH), program counter lower-order byte register (PCL;06H),
memory pointer registers (MP0;01H, MP1;03H), accumulator (ACC;05H), table pointer (TBLP;07H), table
higher-order byte register (TBLH;08H), status register
(STATUS;0AH), interrupt control register 0 (INTC0;
0BH), PWM data register (PWM0;1AH, PWM1;1BH),
the I2C Bus slave address register (HADR;20H), the I2C
Bus control register (HCR;21H), the I2C Bus status register (HSR;22H), the I2C Bus data register (HDR;23H),
the A/D result lower-order byte register (ADRL;24H), the
A/D result higher-order byte register (ADRH;25H), the
A/D control register (ADCR;26H), the A/D clock setting
register (ACSR;27H), I/O registers (PA;12H, PB;14H,
PC;16H, PD;18H) and I/O control registers (PAC;13H,
PBC;15H, PCC;17H, PDC;19H). The remaining space
before the 40H is reserved for future expanded usage
and reading these locations will get ²00H². The general
purpose data memory, addressed from 40H to FFH, is
used for data and control information under instruction
commands.
A C C
0 6 H
P C L
0 7 H
T B L P
0 8 H
T B L H
0 9 H
0 A H
S T A T U S
0 B H
IN T C 0
0 C H
T M R H
0 D H
T M R L
0 E H
T M R C
0 F H
1 0 H
1 1 H
1 2 H
P A
1 3 H
P A C
1 4 H
P B
1 5 H
P B C
1 6 H
P C
1 7 H
P C C
1 8 H
P D
1 9 H
P D C
1 A H
P W M 0
1 B H
P W M 1
S p e c ia l P u r p o s e
D A T A M E M O R Y
1 C H
1 D H
1 E H
IN T C 1
1 F H
All of the data memory areas can handle arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits, each bit in the
data memory can be set and reset by ²SET [m].i² and
²CLR [m].i². They are also indirectly accessible through
memory pointer registers (MP0;01H/MP1;03H).
2 0 H
H A D R
2 1 H
H C R
2 2 H
H S R
2 3 H
H D R
2 4 H
A D R L
2 5 H
A D R H
2 6 H
A D C R
2 7 H
A C S R
2 8 H
3 F H
4 0 H
Indirect Addressing Register
Location 00H and 02H are indirect addressing registers
that are not physically implemented. Any read/write operation of [00H] or [02H] will access data memory
pointed to by MP0[01H] or MP1[03H] respectively.
Reading location 00H or 02H itself indirectly will return
the result 00H. Writing indirectly result in no operation.
Rev. 1.60
In d ir e c t A d d r e s s in g R e g is te r 0
0 1 H
F F H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(1 9 2 B y te s )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
8
May 3, 2004
HT46R23/HT46C23
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic operations.
The ALU provides the following functions:
The device provides an external interrupt, an internal
timer/event counter interrupt, the A/D converter interrupt
and the I2C Bus interrupts. The interrupt control register
0 (INTC0;0BH) and interrupt control register 1
(INTC1;1EH) contains the interrupt control bits to set the
enable or disable and the interrupt request flags.
· Arithmetic operations (ADD, ADC, SUB, SBC, DAA)
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
· Increment and Decrement (INC, DEC)
Once an interrupt subroutine is serviced, all the other interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
interrupt requests may happen during this interval but
only the interrupt request flag is recorded. If a certain interrupt requires servicing within the service routine, the
EMI bit and the corresponding bit of INTC0 and INTC1
may be set to allow interrupt nesting. If the stack is full,
the interrupt request will not be acknowledged, even if the
related interrupt is enabled, until the SP is decremented.
If immediate service is desired, the stack must be prevented from becoming full.
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
The ALU not only saves the results of a data operation but
also changes the status register.
Status Register - STATUS
This 8-bit register (0AH) contains the zero flag (Z), carry
flag (C), auxiliary carry flag (AC), overflow flag (OV),
power down flag (PDF), and watchdog time-out flag
(TO). It also records the status information and controls
the operation sequence.
With the exception of the TO and PDF flags, bits in
the status register can be altered by instructions like
most other registers. Any data written into the status
register will not change the TO or PDF flag. In addition operations related to the status register may give
different results from those intended. The TO flag
can be affected only by system power-up, a WDT
time-out or executing the ²CLR WDT² or ²HALT² instruction. The PDF flag can be affected only by executing the ²HALT² or ²CLR WDT² instruction or a
system power-up.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the program memory. Only the program counter is pushed onto
the stack. If the contents of the register or status register
(STATUS) are altered by the interrupt service program
which corrupts the desired control sequence, the contents should be saved in advance.
External interrupts are triggered by a high to low transition of INT and the related interrupt request flag (EIF; bit
4 of INTC0) will be set. When the interrupt is enabled,
the stack is not full and the external interrupt is active, a
subroutine call to location 04H will occur. The interrupt
request flag (EIF) and EMI bits will be cleared to disable
other interrupts.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
In addition, on entering the interrupt sequence or executing the subroutine call, the status register will not be
pushed onto the stack automatically. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take
place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate through
carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or no borrow from the
high nibble into the low nibble in subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PDF
4
PDF is cleared by system power-up or executing the ²CLR WDT² instruction. PDF is set by executing the ²HALT² instruction.
TO
5
TO is cleared by system power-up or executing the ²CLR WDT² or ²HALT² instruction. TO is set
by a WDT time-out.
¾
6, 7
Unused bit, read as ²0²
Status Register
Rev. 1.60
9
May 3, 2004
HT46R23/HT46C23
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding interrupts are enabled. In the case of simultaneous requests
the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The internal timer/event counter interrupt is initialized by
setting the timer/event counter interrupt request flag
(TF; bit 5 of INTC0), caused by a timer overflow. When
the interrupt is enabled, the stack is not full and the TF
bit is set, a subroutine call to location 08H will occur. The
related interrupt request flag (TF) will be reset and the
EMI bit cleared to disable further interrupts.
Interrupt Source
The A/D converter interrupt is initialized by setting the
A/D converter request flag (ADF; bit 6 of INTC0),
caused by an end of A/D conversion. When the interrupt
is enabled, the stack is not full and the ADF is set, a subroutine call to location 0CH will occur. The related interrupt request flag (ADF) will be reset and the EMI bit
cleared to disable further interrupts.
Register Bit No. Label
INTC0
(0BH)
Controls the master (global)
EMI interrupt
(1=enabled; 0=disabled)
1
EEI
Controls the external interrupt
(1=enabled; 0=disabled)
2
ETI
Controls the timer/event
counter interrupt
(1=enabled; 0=disabled)
3
Controls the A/D converter
EADI interrupt
(1=enabled; 0=disabled)
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
TF
Internal timer/event counter
request flag
(1=active; 0=inactive)
6
ADF
7
¾
Vector
External Interrupt
1
04H
Timer/Event Counter Overflow
2
08H
A/D Converter Interrupt
3
0CH
Serial bus interrupt
4
10H
The timer/event counter interrupt request flag (TF), external interrupt request flag (EIF), A/D converter request
flag (ADF), the I2C Bus interrupt request flag (HIF), enable timer/event counter bit (ETI), enable external interrupt bit (EEI), enable A/D converter interrupt bit (EADI),
enable I2C Bus interrupt bit (EHI) and enable master interrupt bit (EMI) constitute an interrupt control register 0
(INTC0) and an interrupt control register 1 (INTC1)
which are located at 0BH and 1EH in the data memory.
EMI, EEI, ETI, EADI, EHI are used to control the enabling/disabling of interrupts. These bits prevent the requested interrupt from being serviced. Once the
interrupt request flags (TF, EIF, ADF, HIF) are set, they
will remain in the INTC0 and INTC1 register until the interrupts are serviced or cleared by a software instruction.
Function
0
Priority
Register Bit No. Label
A/D converter request flag
(1=active; 0=inactive)
INTC1
(1EH)
Unused bit, read as ²0²
INTC0 Register
The I C Bus interrupt is initialized by setting the I2C Bus
interrupt request flag (HIF; bit 4 of INTC1), caused by a
slave address match (HAAS=²1²) or one byte of data transfer is completed. When the interrupt is enabled, the stack
is not full and the HIF bit is set, a subroutine call to location
10H will occur. The related interrupt request flag (HIF) will
be reset and the EMI bit cleared to disable further interrupts.
0
EHI
1~3
¾
4
HIF
5~7
¾
Function
Controls the I2C Bus interrupt
(1= enabled; 0= disabled)
Unused bit, read as ²0²
I2C Bus interrupt request flag
(1= active; 0= inactive)
Unused bit, read as ²0²
2
INTC1 Register
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine. Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications.
If only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be damaged once the ²CALL² operates in the interrupt subroutine.
During the execution of an interrupt subroutine, other interrupt acknowledgments are held until the ²RETI² instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (of course, if the stack is
not full). To return from the interrupt subroutine, ²RET² or
²RETI² may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
Rev. 1.60
10
May 3, 2004
HT46R23/HT46C23
(system clock divided by 4) decided by options. This
timer is designed to prevent a software malfunction or
sequence jumping to an unknown location with unpredictable results. The watchdog timer can be disabled by
an option. If the watchdog timer is disabled, all the executions related to the WDT result in no operation.
Oscillator Configuration
There are two oscillator circuits in the microcontroller.
V
D D
O S C 1
O S C 1
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
N M O S O p e n D r a in
Once an internal WDT oscillator (RC oscillator with period 65ms/@5V normally) is selected, it is divided by
212~215 (by options to get the WDT time-out period).
The minimum period of WDT time-out period is about
300ms~600ms. This time-out period may vary with temperature, VDD and process variations. By selection the
WDT options, longer time-out periods can be realized. If
the WDT time-out is selected 215, the maximum time-out
period is divided by 215~216 about 2.1s~4.3s.
O S C 2
R C
O s c illa to r
System Oscillator
Both are designed for system clocks, namely the RC oscillator and the Crystal oscillator, which are determined
by options. No matter what oscillator type is selected,
the signal provides the system clock. The HALT mode
stops the system oscillator and ignores an external signal to conserve power.
If the WDT oscillator is disabled, the WDT clock may still
come from the instruction clock and operate in the same
manner except that in the halt state the WDT may stop
counting and lose its protecting purpose. In this situation
the logic can only be restarted by external logic. If the
device operates in a noisy environment, using the
on-chip RC oscillator (WDT OSC) is strongly recommended, since the HALT will stop the system clock.
If an RC oscillator is used, an external resistor between
OSC1 and VSS is required and the resistance must
range from 30kW to 750kW. The system clock, divided
by 4, is available on OSC2, which can be used to synchronize external logic. The RC oscillator provides the
most cost effective solution. However, the frequency of
oscillation may vary with VDD, temperatures and the
chip itself due to process variations. It is, therefore, not
suitable for timing sensitive operations where an accurate oscillator frequency is desired.
The WDT overflow under normal operation will initialize
²chip reset² and set the status bit TO. Whereas in the halt
mode, the overflow will initialize a ²warm reset² only the
PC and SP are reset to zero. To clear the contents of WDT,
three methods are adopted; external reset (a low level to
RES), software instructions, or a HALT instruction. The
software instructions include CLR WDT and the other set CLR WDT1 and CLR WDT2. Of these two types of instruction, only one can be active depending on the options ²CLR WDT times selection option². If the ²CLR WDT² is
selected (i.e. CLRWDT times equal one), any execution of
the CLR WDT instruction will clear the WDT. In case ²CLR
WDT1² and ²CLR WDT2² are chosen (i.e. CLRWDT times
equal two), these two instructions must be executed to
clear the WDT; otherwise, the WDT may reset the chip because of time-out.
If the Crystal oscillator is used, a crystal across OSC1
and OSC2 is needed to provide the feedback and phase
shift required for the oscillator, and no other external
components are required. Instead of a crystal, a resonator can also be connected between OSC1 and OSC2 to
get a frequency reference, but two external capacitors in
OSC1 and OSC2 are required (If the oscillating frequency is less than 1MHz).
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock is stopped, but the WDT oscillator still works with a
period of approximately 65ms@5V. The WDT oscillator
can be disabled by options to conserve power.
If the WDT time-out period is selected fs/212 (by options),
the WDT time-out period ranges from fs/212~fs/213, since
the ²CLR WDT² or ²CLR WDT1² and ²CLR WDT2² instructions only clear the last two stages of the WDT.
Watchdog Timer - WDT
The clock source of the WDT is implemented by an dedicated RC oscillator (WDT oscillator) or instruction clock
S y s te m
C lo c k /4
M a s k
o p tio n
s e le c t
W D T
O S C
fs
D iv id e r
fs/2
8
W D T P r e s c a le r
M a s k O p tio n
W D T C le a r
C K
R
T
C K
R
T
T im e - o
fs /2 1 5 ~
fs /2 1 4 ~
fs /2 1 3 ~
fs /2 1 2 ~
u t R e s e t
fs /2 1 6
fs /2 1 5
fs /2 1 4
fs /2 1 3
Watchdog Timer
Rev. 1.60
11
May 3, 2004
HT46R23/HT46C23
Power Down Operation - HALT
V D D
The HALT mode is initialized by the ²HALT² instruction
and results in the following...
R E S
tS
S T
S S T T im e - o u t
· The system oscillator will be turned off but the WDT
oscillator keeps running (if the WDT oscillator is selected).
C h ip
R e s e t
Reset Timing Chart
· The contents of the on chip RAM and registers remain
unchanged.
V
· WDT will be cleared and recounted again (if the WDT
D D
0 .0 1 m F *
clock is from the WDT oscillator).
· All of the I/O ports maintain their original status.
1 0 0 k W
· The PDF flag is set and the TO flag is cleared.
R E S
1 0 k W
The system can leave the HALT mode by means of an
external reset, an interrupt, an external falling edge signal on port A or a WDT overflow. An external reset
causes a device initialization and the WDT overflow performs a ²warm reset². After the TO and PDF flags are
examined, the reason for chip reset can be determined.
The PDF flag is cleared by system power-up or executing the ²CLR WDT² instruction and is set when executing the ²HALT² instruction. The TO flag is set if the WDT
time-out occurs, and causes a wake-up that only resets
the PC and SP; the others keep their original status.
0 .1 m F *
Reset Circuit
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to
avoid noise interference.
Note:
H A L T
W a rm
R e s e t
W D T
The port A wake-up and interrupt methods can be considered as a continuation of normal execution. Each bit
in port A can be independently selected to wake up the
device by the options. Awakening from an I/O port stimulus, the program will resume execution of the next instruction. If it is awakening from an interrupt, two
sequences may happen. If the related interrupt is disabled or the interrupt is enabled but the stack is full, the
program will resume execution at the next instruction. If
the interrupt is enabled and the stack is not full, the regular interrupt response takes place. If an interrupt request
flag is set to ²1² before entering the HALT mode, the
wake-up function of the related interrupt will be disabled.
Once a wake-up event occurs, it takes 1024 tSYS (system clock period) to resume normal operation. In other
words, a dummy period will be inserted after wake-up. If
the wake-up results from an interrupt acknowledgment,
the actual interrupt subroutine execution will be delayed
by one or more cycles. If the wake-up results in the next
instruction execution, this will be executed immediately
after the dummy period is finished.
R E S
C o ld
R e s e t
S S T
1 0 - b it R ip p le
C o u n te r
O S C 1
S y s te m
R e s e t
Reset Configuration
set² that resets only the PC and SP, leaving the other
circuits in their original state. Some registers remain unchanged during other reset conditions. Most registers
are reset to the ²initial condition² when the reset conditions are met. By examining the PDF and TO flags, the
program can distinguish between different ²chip resets².
TO
PDF
RESET Conditions
0
0
RES reset during power-up
u
u
RES reset during normal operation
To minimize power consumption, all the I/O pins should
be carefully managed before entering the HALT status.
0
1
RES wake-up HALT
1
u
WDT time-out during normal operation
Reset
1
1
WDT wake-up HALT
There are three ways in which a reset can occur:
Note: ²u² means ²unchanged²
· RES reset during normal operation
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra-delay of 1024 system clock pulses when the system reset (power-up, WDT time-out or RES reset) or the
system awakes from the HALT state.
· RES reset during HALT
· WDT time-out reset during normal operation
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re Rev. 1.60
12
May 3, 2004
HT46R23/HT46C23
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay. The functional unit chip reset status
are shown below.
An extra option load time delay is added during system
reset (power-up, WDT time-out at normal mode or RES
reset).
PC
000H
Interrupt
Disable
WDT
Clear. After master reset, WDT
begins counting
Timer/Event Counter Off
Input/Output Ports
Input mode
SP
Points to the top of the stack
The registers states are summarized in the following table.
Register
TMRL
Reset
(Power On)
WDT Time-out
RES Reset
(Normal Operation) (Normal Operation)
xxxx xxxx
xxxx xxxx
xxxx xxxx
RES Reset
(HALT)
WDT Time-out
(HALT)*
xxxx xxxx
uuuu uuuu
TMRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
TMRC
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
Program
Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
INTC1
---0 ---0
---0 ---0
---0 ---0
---0 ---0
---u ---u
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
PCC
---1 1111
---1 1111
---1 1111
---1 1111
---u uuuu
---- --11
---- --11
---- --11
---- --11
---- --uu
PD
PDC
---- --11
---- --11
---- --11
---- --11
---- --uu
PWM0
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
PWM1
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
HADR
xxxx xxx-
xxxx xxx-
xxxx xxx-
xxxx xxx-
uuuu uuu-
HCR
0--0 0---
0--0 0---
0--0 0---
0--0 0---
u--u u---
HSR
100- -0-1
100- -0-1
100- -0-1
100- -0-1
uuu- -u-u
HDR
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADRL
xx-- ----
xx-- ----
xx-- ----
xx-- ----
uuuu ----
ADRH
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
uuuu uuuu
ADCR
0100 0000
0100 0000
0100 0000
0100 0000
uuuu uuuu
ACSR
1--- --00
1--- --00
1--- --00
1--- --00
u--- --uu
Note:
²*² stands for warm reset
²u² stands for unchanged
²x² stands for unknown
Rev. 1.60
13
May 3, 2004
HT46R23/HT46C23
In the pulse width measurement mode with the TON and
TE bits equal to one, once the TMR has received a transient from low to high (or high to low if the TE bits is ²0²)
it will start counting until the TMR returns to the original
level and resets the TON. The measured result will remain in the timer/event counter even if the activated
transient occurs again. In other words, only one cycle
measurement can be done. Until setting the TON, the
cycle measurement will function again as long as it receives further transient pulse. Note that, in this operating mode, the timer/event counter starts counting not
according to the logic level but according to the transient
edges. In the case of counter overflows, the counter is
reloaded from the timer/event counter preload register
and issues the interrupt request just like the other two
modes. To enable the counting operation, the timer ON
bit (TON; bit 4 of TMRC) should be set to 1. In the pulse
width measurement mode, the TON will be cleared automatically after the measurement cycle is completed.
But in the other two modes the TON can only be reset by
instructions. The overflow of the timer/event counter is
one of the wake-up sources. No matter what the operation mode is, writing a 0 to ETI can disable the interrupt
service.
Timer/Event Counter
A timer/event counter (TMR) is implemented in the
microcontroller. The timer/event counter contains an
16-bit programmable count-up counter and the clock
may come from an external source or the system clock.
Using the internal system clock, there is only one reference time-base. The internal clock source comes from
fSYS. The external clock input allows the user to count
external events, measure time intervals or pulse widths,
or to generate an accurate time base.
There are three registers related to the timer/event
counter; TMRH (0CH), TMRL (0DH), TMRC (0EH).
Writing TMRL will only put the written data to an internal
lower-order byte buffer (8 bits) and writing TMRH will
transfer the specified data and the contents of the
lower-order byte buffer to TMRH and TMRL preload registers, respectively. The timer/event counter preload
register is changed by each writing TMRH operations.
Reading TMRH will latch the contents of TMRH and
TMRL counters to the destination and the lower-order
byte buffer, respectively. Reading the TMRL will read the
contents of the lower-order byte buffer. The TMRC is the
timer/event counter control register, which defines the
operating mode, counting enable or disable and active
edge.
In the case of timer/event counter OFF condition, writing
data to the timer/event counter preload register will also
reload that data to the timer/event counter. But if the
timer/event counter is turned on, data written to it will
only be kept in the timer/event counter preload register.
The timer/event counter will still operate until overflow
occurs. When the timer/event counter (reading TMRH)
is read, the clock will be blocked to avoid errors. As
clock blocking may results in a counting error, this must
be taken into consideration by the programmer.
The TM0, TM1 bits define the operating mode. The
event count mode is used to count external events,
which means the clock source comes from an external
(TMR) pin. The timer mode functions as a normal timer
with the clock source coming from the fINT clock. The
pulse width measurement mode can be used to count the
high or low level duration of the external signal (TMR).
The counting is based on the fINT.
In the event count or timer mode, once the timer/event
counter starts counting, it will count from the current contents in the timer/event counter to FFFFH. Once overflow
occurs, the counter is reloaded from the timer/event counter preload register and generates the interrupt request
flag (TF; bit 5 of INTC0) at the same time.
The bit0~bit2 of the TMRC can be used to define the
pre-scaling stages of the internal clock sources of the
timer/event counter. The definitions are as shown. The
overflow signal of the timer/event counter can be used
to generate the PFD signal.
P W M
(6 + 2 ) o r (7 + 1 )
C o m p a re
fS
Y S
T o P D 0 /P D 1 C ir c u it
D a ta B u s
8 - s ta g e p r e s c a le r
f IN
8 -1 M U X
P S C 2 ~ P S C 0
L o w B y te
B u ffe r
T
T M 1
T M 0
T M R
1 6 - B it
P r e lo a d R e g is te r
T E
T M 1
T M 0
T O N
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
H ig h B y te
R e lo a d
O v e r flo w
L o w B y te
to In te rru p t
1 6 - B it T im e r /E v e n t C o u n te r
1 /2
P F D
Timer/Event Counter
Rev. 1.60
14
May 3, 2004
HT46R23/HT46C23
Label
Bits
(TMRC)
must be ready at the T2 rising edge of instruction ²MOV
A,[m]² (m=12H, 14H, 16H or 18H). For output operation,
all the data is latched and remains unchanged until the
output latch is rewritten.
Function
To define the prescaler stages, PSC2,
PSC1, PSC0=
000: fINT=fSYS
001: fINT=fSYS/2
PSC0~
010: fINT=fSYS/4
0~2
PSC2
011: fINT=fSYS/8
100: fINT=fSYS/16
101: fINT=fSYS/32
110: fINT=fSYS/64
111: fINT=fSYS/128
TE
3
To define the TMR active edge of timer/
event counter
(0=active on low to high;
1=active on high to low)
TON
4
To enable or disable timer counting
(0=disabled; 1=enabled)
¾
5
Unused bits, read as ²0²
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TM0
TM1
Each I/O line has its own control register (PAC, PBC,
PCC, PDC) to control the input/output configuration.
With this control register, CMOS output or schmitt trigger input with or without pull-high resistor structures can
be reconfigured dynamically (i.e. on-the-fly) under software control. To function as an input, the corresponding
latch of the control register must write ²1². The input
source also depends on the control register. If the control register bit is ²1², the input will read the pad state. If
the control register bit is ²0², the contents of the latches
will move to the internal bus. The latter is possible in the
²read-modify-write² instruction.
For output function, CMOS is the only configuration.
These control registers are mapped to locations 13H,
15H, 17H and 19H.
After a chip reset, these input/output lines remain at high
levels or floating state (dependent on pull-high options).
Each bit of these input/output latches can be set or
cleared by ²SET [m].i² and ²CLR [m].i² (m=12H, 14H,
16H or 18H) instructions.
TMRC Register
Input/Output Ports
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
There are 23 bidirectional input/output lines in the
microcontroller, labeled as PA, PB, PC and PD, which
are mapped to the data memory of [12H], [14H], [16H]
and [18H] respectively. All of these I/O ports can be
used for input and output operations. For input operation, these ports are non-latching, that is, the inputs
V
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
P U
P A
P A
P A
P A
P A
P A
P B
P C
P D
P D
Q
S
C h ip R e s e t
D a ta B it
Q
D
Q
C K
D D
0 ~ P A 2
3 /P F D
4 /T M R
5 /IN T
6 /S D A
7 /S C L
0 /A N 0 ~ P B 7 /A N 7
0 ~ P C 4
0 /P W M 0
1 /P W M 1
S
M
(P D 0 o r P W M 0 ) P A 3
(P D 1 o r P W M 1 ) P F D
M
R e a d D a ta R e g is te r
S y s te m W a k e -u p
( P A o n ly )
U
U
X
P F D E N
(P A 3 )
X
O P 0 ~ O P 7
IN T fo r P A 5 O n ly
T M R
fo r P A 4 O n ly
Input/Output Ports
Rev. 1.60
15
May 3, 2004
HT46R23/HT46C23
denoted as PWM0 (1AH) and PWM1 (1BH). The frequency source of the PWM counter comes from fSYS.
The PWM registers are two 8-bit registers. The waveforms of PWM outputs are as shown. Once the
PD0/PD1 are selected as the PWM outputs and the output function of PD0/PD1 are enabled (PDC.0/PDC.1
=²0²), writing ²1² to PD0/PD1 data register will enable
the PWM output function and writing ²0² will force the
PD0/PD1 to stay at ²0².
Each line of port A has the capability of waking-up the
device. The highest 3-bit of port C and 6-bit of port D are
not physically implemented; on reading them a ²0² is returned whereas writing then results in a no-operation.
See Application note.
Each I/O port has a pull-high option. Once the pull-high
option is selected, the I/O port has a pull-high resistor,
otherwise, there¢s none. Take note that a non-pull-high
I/O port operating in input mode will cause a floating
state.
A (6+2) bits mode PWM cycle is divided into four modulation cycles (modulation cycle 0~modulation cycle 3).
Each modulation cycle has 64 PWM input clock period.
In a (6+2) bit PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.2.
The PA3 is pin-shared with the PFD signal. If the PFD
option is selected, the output signal in output mode of
PA3 will be the PFD signal generated by the timer/event
counter overflow signal. The input mode always remaining its original functions. Once the PFD option is selected, the PFD output signal is controlled by PA3 data
register only. Writing ²1² to PA3 data register will enable
the PFD output function and writing ²0² will force the
PA3 to remain at ²0². The I/O functions of PA3 are
shown below.
I/O
I/P
Mode (Normal)
Logical
Input
PA3
Note:
O/P
(Normal)
I/P
(PFD)
O/P
(PFD)
Logical
Output
Logical
Input
PFD
(Timer on)
The group 2 is denoted by AC which is the value of
PWM.1~PWM.0.
In a (6+2) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
AC (0~3)
Duty Cycle
i<AC
DC+1
64
i³AC
DC
64
Modulation cycle i
(i=0~3)
The PFD frequency is the timer/event counter
overflow frequency divided by 2.
A (7+1) bits mode PWM cycle is divided into two modulation cycles (modulation cycle 0 ~ modulation cycle 1).
Each modulation cycle has 128 PWM input clock period.
The PA4, PA5, PA6 and PA7 are pin-shared with TMR,
INT, SDA and SCL pins respectively.
The PB can also be used as A/D converter inputs. The
A/D function will be described later. There is a PWM
function shared with PD0/PD1. If the PWM function is
enabled, the PWM0/PWM1 signal will appear on
PD0/PD1 (if PD0/PD1 is operating in output mode).
Writing ²1² to PD0/PD1 data register will enable the
PWM0/PWM1 output function and writing ²0² will force
the PD0/PD1 to remain at ²0². The I/O functions of
PD0/PD1 are as shown.
I/O
I/P
Mode (Normal)
PD0
PD1
Logical
Input
O/P
(Normal)
I/P
(PWM)
O/P
(PWM)
Logical
Output
Logical
Input
PWM0
PWM1
In a (7+1) bits PWM function, the contents of the PWM
register is divided into two groups. Group 1 of the PWM
register is denoted by DC which is the value of
PWM.7~PWM.1.
The group 2 is denoted by AC which is the value of
PWM.0.
In a (7+1) bits mode PWM cycle, the duty cycle of each
modulation cycle is shown in the table.
Parameter
Duty Cycle
i<AC
DC+1
128
i³AC
DC
128
Modulation cycle i
(i=0~1)
It is recommended that unused or not bonded out I/O
lines should be set as output pins by software instruction
to avoid consuming power under input floating state.
The modulation frequency, cycle frequency and cycle
duty of the PWM output signal are summarized in the
following table.
PWM
PWM
Modulation Frequency
The microcontroller provides 2 channels (6+2)/(7+1)
(dependent on options) bits PWM output shared with
PD0/PD1. The PWM channels have their data registers
Rev. 1.60
AC (0~1)
fSYS/64 for (6+2) bits mode
fSYS/128 for (7+1) bits mode
16
PWM Cycle PWM Cycle
Frequency
Duty
fSYS/256
[PWM]/256
May 3, 2004
HT46R23/HT46C23
fS
/2
Y S
[P W M ] = 1 0 0
P W M
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 5 /6 4
2 6 /6 4
2 6 /6 4
2 6 /6 4
2 5 /6 4
2 6 /6 4
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
2 6 /6 4
P W M
m o d u la tio n p e r io d : 6 4 /fS
M o d u la tio n c y c le 0
Y S
M o d u la tio n c y c le 1
P W M
M o d u la tio n c y c le 2
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 3
M o d u la tio n c y c le 0
Y S
(6+2) PWM Mode
fS
Y S
/2
[P W M ] = 1 0 0
P W M
5 0 /1 2 8
5 0 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 0 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 1 /1 2 8
5 2 /1 2 8
[P W M ] = 1 0 1
P W M
[P W M ] = 1 0 2
P W M
[P W M ] = 1 0 3
P W M
5 2 /1 2 8
P W M
m o d u la tio n p e r io d : 1 2 8 /fS
Y S
M o d u la tio n c y c le 0
M o d u la tio n c y c le 1
P W M
c y c le : 2 5 6 /fS
M o d u la tio n c y c le 0
Y S
(7+1) PWM Mode
The A/D converter control register is used to control the
A/D converter. The bit2~bit0 of the ADCR are used to
select an analog input channel. There are a total of eight
channels to select. The bit5~bit3 of the ADCR are used
to set PB configurations. PB can be an analog input or
as digital I/O line decided by these 3 bits. Once a PB line
is selected as an analog input, the I/O functions and
pull-high resistor of this I/O line are disabled and the A/D
converter circuit is power on. The EOCB bit (bit6 of the
ADCR) is end of A/D conversion flag. Check this bit to
know when A/D conversion is completed. The START
bit of the ADCR is used to begin the conversion of the
A/D converter. Giving START bit a rising edge and falling edge means that the A/D conversion has started. In
order to ensure the A/D conversion is completed, the
START should remain at ²0² until the EOCB is cleared to
²0² (end of A/D conversion).
A/D Converter
The 8 channels and 10-bit resolution A/D (9-bit accuracy) converter are implemented in this microcontroller.
The reference voltage is VDD. The A/D converter contains 4 special registers which are; ADRL (24H), ADRH
(25H), ADCR (26H) and ACSR (27H). The ADRH and
ADRL are A/D result register higher-order byte and
lower-order byte and are read-only. After the A/D conversion is completed, the ADRH and ADRL should be
read to get the conversion result data. The ADCR is an
A/D converter control register, which defines the A/D
channel number, analog channel select, start A/D conversion control bit and the end of A/D conversion flag. If
the users want to start an A/D conversion. Define PB
configuration, select the converted analog channel, and
give START bit a raising edge and falling edge
(0®1®0). At the end of A/D conversion, the EOCB bit is
cleared and an A/D converter interrupt occurs (if the A/D
converter interrupt is enabled). The ACSR is A/D clock
setting register, which is used to select the A/D clock
source.
Rev. 1.60
The bit 7 of the ACSR is used for testing purposes only.
It can not be used by the users. The bit1 and bit0 of the
ACSR are used to select A/D clock sources.
17
May 3, 2004
HT46R23/HT46C23
Label
Bits
(ACSR)
ADCS0
ADCS1
¾
TEST
Function
Selects the A/D converter clock source
00= system clock/2
01= system clock/8
10= system clock/32
11= undefined
0
1
2~6 Unused bit, read as ²0²
7
For test mode used only
ACSR Register
ACS2
ACS1
ACS0
Analog Channel
0
0
0
A0
0
0
1
A1
0
1
0
A2
0
1
1
A3
1
0
0
A4
1
0
1
A5
1
1
0
A6
1
1
1
A7
Analog Input Channel Selection
Label
Bits
(ADCR)
Function
ACS0
ACS1
ACS2
0
1
2
Defines the analog channel select.
PCR0
PCR1
PCR2
3
4
5
Defines the port B configuration select.
If PCR0, PCR1 and PCR2 are all zero,
the ADC circuit is power off to reduce
power consumption
EOCB
6
Provides response at the end of the
A/D conversion.
(0= end of A/D conversion)
START
7
Starts the A/D conversion. (0®1®0=
start; 0®1= reset A/D converter)
When the A/D conversion is completed, the A/D interrupt request flag is set. The EOCB bit is set to ²1² when
the START bit is set from ²0² to ²1².
Register
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
ADRL
D1
D0
¾
¾
¾
¾
¾
¾
ADRH
D9
D8 D7
D6
D5
D4
D3
D2
Note:
D0~D9 is A/D conversion result data bit
LSB~MSB.
ADCR Register
PCR2
PCR1
PCR0
7
6
5
4
3
2
1
0
0
0
0
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
0
0
1
PB7
PB6
PB5
PB4
PB3
PB2
PB1
A0
0
1
0
PB7
PB6
PB5
PB4
PB3
PB2
A1
A0
0
1
1
PB7
PB6
PB5
PB4
PB3
A2
A1
A0
1
0
0
PB7
PB6
PB5
PB4
A3
A2
A1
A0
1
0
1
PB7
PB6
PB5
A4
A3
A2
A1
A0
1
1
0
PB7
PB6
A5
A4
A3
A2
A1
A0
1
1
1
A7
A6
A5
A4
A3
A2
A1
A0
Port B Configuration
Rev. 1.60
18
May 3, 2004
HT46R23/HT46C23
The following two programming examples illustrate how to setup and implement an A/D conversion. In the first example, the method of polling the EOCB bit in the ADCR register is used to detect when the conversion cycle is complete,
whereas in the second example, the A/D interrupt is used to determine when the conversion is complete.
Example: using EOCB Polling Method to detect end of conversion
clr INTC0.3
mov a,00100000B
mov ADCR,a
mov a,00000001B
mov ACSR,a
Start_conversion:
clr ADCR.7
set ADCR.7
clr ADCR.7
Polling_EOC:
sz ADCR.6
jmp polling_EOC
mov a,ADRH
mov adrh_buffer,a
mov a,ADRL
mov adrl_buffer,a
:
:
jmp start_conversion
; disable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; poll the ADCR register EOCB bit to detect end of A/D conversion
; continue polling
; read conversion result from the high byte ADRH register
; save result to user defined register
; read conversion result from the low byte ADRL register
; save result to user defined register
; start next A/D conversion
Example: using Interrupt method to detect end of conversion
set INTC0.0
set INTC0.3
mov a,00100000B
mov ADCR,a
mov a,00000001B
mov ACSR,a
start_conversion:
clr ADCR.7
set ADCR.7
clr ADCR.7
:
:
; interrupt service routine
EOC_service routine:
mov a_buffer,a
mov a,ADRH
mov adrh_buffer,a
mov a,ADRL
mov adrl_buffer,a
clr ADCR.7
set ADCR.7
clr ADCR.7
mov a,a_buffer
reti
Rev. 1.60
; interrupt global enable
; enable A/D interrupt in interrupt control register
; setup ADCR register to configure Port PB0~PB3 as A/D inputs and select
; AN0 to be connected to the A/D converter
; setup the ACSR register to select fSYS/8 as the A/D clock
; reset A/D
; start A/D
; save ACC to user defined register
; read conversion result from the high byte ADRH register
; save result to user defined register
; read conversion result from the low byte ADRL register
; save result to user defined register
; reset A/D
; start A/D
; restore ACC from temporary storage
19
May 3, 2004
HT46R23/HT46C23
M in im u m
o n e in s tr u c tio n c y c le n e e d e d
S T A R T
E O C B
A /D s a m p lin g tim e
3 2 tA D
P C R 2 ~ P C R 0
0 0 0 B
A /D s a m p lin g tim e
3 2 tA D
1 0 0 B
1 0 0 B
0 0 0 B
1 . P B p o rt s e tu p a s I/O s
2 . A /D c o n v e r te r is p o w e r e d o ff
to r e d u c e p o w e r c o n s u m p tio n
A C S 2 ~ A C S 0
0 0 0 B
P o w e r-o n
R e s e t
0 1 0 B
0 0 0 B
S ta rt o f A /D
c o n v e r s io n
S ta rt o f A /D
c o n v e r s io n
R e s e t A /D
c o n v e rte r
R e s e t A /D
c o n v e rte r
E n d o f A /D
c o n v e r s io n
1 : D e fin e P B c o n fig u r a tio n
2 : S e le c t a n a lo g c h a n n e l
A /D
A /D
N o te :
c lo c k m u s t b e fS
Y S
/2 , fS
7 6 tA D
c o n v e r s io n tim e
Y S
/8 o r fS
Y S
d o n 't c a r e
E n d o f A /D
c o n v e r s io n
A /D
7 6 tA D
c o n v e r s io n tim e
/3 2
A/D Conversion Timing
Low Voltage Reset - LVR
SCL are NMOS open drain output pin. They must connect a pull-high resistor respectively.
The microcontroller provides low voltage reset circuit in
order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~3.3V, such as changing a battery, the LVR will automatically reset the device internally.
Using the I2C Bus, the device has two ways to transfer
data. One is in slave transmit mode, the other is in slave
receive mode. There are four registers related to I2C
Bus; HADR([20H]), HCR([21H]), HSR([22H]),
HDR([23H]). The HADR register is the slave address
setting of the device, if the master sends the calling address which match, it means that this device is selected.
The HCR is I2C Bus control register which defines the
device enable or disable the I2C Bus as a transmitter or
as a receiver. The HSR is I2C Bus status register, it responds with the I2C Bus status. The HDR is input/output
data register, data to transmit or receive must be via the
HDR register.
The LVR includes the following specifications:
· The low voltage (0.9V~VLVR) has to remain in their
original state to exceed 1ms. If the low voltage state
does not exceed 1ms, the LVR will ignore it and do not
perform a reset function.
· The LVR uses the ²OR² function with the external RES
signal to perform chip reset.
The relationship between VDD and VLVR is shown below.
V
D D
5 .5 V
V
The I2C Bus control register contains three bits. The
HEN bit define the enable or disable the I2C Bus. If the
data wants transfer via I2C Bus, this bit must be set. The
HTX bit defines whether the I2C Bus is in transmit or receive mode. If the device is as a transmitter, this bit must
be set to ²1². The TXAK defines the transmit acknowledge signal, when the device received 8-bit data, the
device sends this bit to I2C Bus at the 9th clock. If the receiver wants to continue to receive the next data, this bit
must be reset to ²0² before receiving data.
O P R
5 .5 V
V
L V R
3 .0 V
2 .2 V
0 .9 V
The I2C Bus status register contains 5 bits. The HCF bit
is reset to ²0² when one data byte is being transferred. If
one data transfer is completed, this bit is set to ²1². The
HASS bit is set ²1² when the address is match, and the
I2C Bus interrupt request flag is set to ²1². If the interrupt
is enabled and the stack is not full, a subroutine call to
location 10H will occur. Writing data to the I2C Bus con-
Note: VOPR is the voltage range for proper chip
operation at 4MHz system clock.
I2C Bus Serial Interface
I2C Bus is implemented in the device. The I2C Bus is a
bidirectional two-wire lines. The data line and clock line
are implement in SDA pin and SCL pin. The SDA and
Rev. 1.60
20
May 3, 2004
HT46R23/HT46C23
V
D D
5 .5 V
V
L V R
L V R
D e te c t V o lta g e
0 .9 V
0 V
R e s e t S ig n a l
N o r m a l O p e r a tio n
R e s e t
R e s e t
*1
*2
Low Voltage Reset
Note:
*1: To make sure that the system oscillator has stabilized, the SST provides an extra delay of 1024 system
clock pulses before entering the normal operation.
*2: Since low voltage state has to be maintained in its original state for over 1ms, therefore after 1ms delay,
the device enters the reset mode.
start signal, all slave device notice the continuity of the
8-bit data. The front of 7 bits is slave address and the
first bit is MSB. If the address is match, the HAAS status
bit is set and generate an I2C Bus interrupt. In the ISR,
the slave device must check the HAAS bit to know the
I2C Bus interrupt comes from the slave address that has
match or completed one 8-bit data transfer. The last bit
of the 8-bit data is read/write command bit, it responds in
SRW bit. The slave will check the SRW bit to know if the
master wants to transmit or receive data. The device
check SRW bit to know it is as a transmitter or receiver.
trol register clears HAAS bit. If the address is not match,
this bit is reset to ²0². The HBB bit is set to respond the
I2C Bus is busy. It mean that a START signal is detected. This bit is reset to ²0² when the I2C Bus is not
busy. It means that a STOP signal is detected and the
I2C Bus is free. The SRW bit defines the read/write command bit, if the calling address is match. When HAAS is
set to ²1², the device check SRW bit to determine
whether the device is working in transmit or receive
mode. When SRW bit is set ²1², it means that the master
wants to read data from I2C Bus, the slave device must
write data to I2C Bus, so the slave device is working in
transmit mode. When SRW is reset to ²0², it means that
the master wants to write data to I2C Bus, the slave device must read data from the bus, so the slave device is
working in receive mode. The RXAK bit is reset ²0² indicates an acknowledges signal has been received. In the
transmit mode, the transmitter checks RXAK bit to know
the receiver which wants to receive the next data byte,
so the transmitter continue to write data to the I2C Bus
until the RXAK bit is set to ²1² and the transmitter releases the SDA line, so that the master can send the
STOP signal to release the bus.
Bit7~Bit1
Slave Address
¾
Note: ²¾² means undefined
HADR Register
The HDR register is the I2C Bus input/output data register. Before transmitting data, the HDR must write the
data which we want to transmit. Before receiving data,
the device must dummy read data from HDR. Transmit
or Receive data from I2C Bus must be via the HDR register. At the beginning of the transfer of the I2C Bus, the
device must initial the bus, the following are the notes for
initialing the I2C Bus.
The HADR bit7-bit1 define the device slave address. At
the beginning of transfer, the master must select a device by sending the address of the slave device. The bit
0 is unused and is not defined. If the I2C Bus receives a
Rev. 1.60
Bit0
21
May 3, 2004
HT46R23/HT46C23
Note:
3. Set EHI bit of the interrupt control register 1 (INTC1)
bit 0 to enable the I2C Bus interrupt.
2
1. Write the I C Bus address register (HADR) to define
its own slave address.
Label
Bits
(HSR)
2
2. Set HEN bit of I C Bus control register (HCR) bit 0 to
enable the I2C Bus.
Label
Bits
(HCR)
HEN
¾
7
Function
To enable or disable I2C Bus function
(0= disable; 1= enable)
4
To define the transmit/receive mode
(0= receive mode; 1= transmit)
TXAK
3
To enable or disable transmit acknowledge
(0=acknowledge; 1=don¢t acknowledge)
¾
HCF
7
HCF is clear to ²0² when one data byte is
being transferred, HCF is set to ²1² indicating 8-bit data communication has
been finished.
HAAS
6
HAAS is set to ²1² when the calling address has matched, and I2C Bus interrupt will occur and HIF is set.
HBB
5
HBB is set to ²1² when I2C Bus is busy
and HBB is cleared to ²0² means that the
I2C Bus is not busy.
6~5 Unused bit, read as ²0²
HTX
¾
4~3 Unused bit, read as ²0²
SRW
2
SRW is set to ²1² when the master wants
to read data from the I2C Bus, so the
slave must transmit data to the master.
SRW is cleared to ²0² when the master
wants to write data to the I2C Bus, so the
slave must receive data from the master.
¾
1
Unused bit, read as ²0²
RXAK
0
RXAK is cleared to ²0² when the master
receives an 8-bit data and acknowledgment at the 9th clock, RXAK is set to ²1²
means not acknowledged.
2~0 Unused bit, read as ²0²
HCR Register
Function
HSR Register
S ta rt
W r ite S la v e
A d d re s s to H A D R
S E T H E N
D is a b le
Rev. 1.60
I2C B u s
In te rru p t= ?
E n a b le
C L R E H I
P o ll H IF to d e c id e
w h e n to g o to I2C B u s IS R
S E T E H I
W a it fo r In te r r u p t
G o to M a in P r o g r a m
G o to M a in P r o g r a m
22
May 3, 2004
HT46R23/HT46C23
S ta rt
N o
N o
R e a d fro m
Y e s
H A A S = 1
?
Y e s
Y e s
H T X = 1
?
H D R
R E T I
Y e s
C L R H T X
C L R T X A K
W r ite to H D R
D u m m y R e a d
F ro m H D R
R E T I
R E T I
N o
W r ite to H D R
D u m m y R e a d
fro m H D R
R E T I
N o
S E T H T X
R X A K = 1
?
C L R H T X
C L R T X A K
S R W = 1
?
R E T I
Start Signal
In interrupt subroutine, check HAAS bit to know whether
the I2C Bus interrupt comes from a slave address that is
matched or a data byte transfer is completed. When the
slave address is matched, the device must be in transmit mode or receive mode and write data to HDR or
dummy read from HDR to release the SCL line.
The START signal is generated only by the master device. The other device in the bus must detect the START
signal to set the I2C Bus busy bit (HBB). The START signal is SDA line from high to low, when SCL is high.
S C L
SRW Bit
The SRW bit means that the master device wants to
read from or write to the I2C Bus. The slave device
check this bit to understand itself if it is a transmitter or a
receiver. The SRW bit is set to ²1² means that the master wants to read data from the I2C Bus, so the slave device must write data to a bus as a transmitter. The SRW
is cleared to ²0² means that the master wants to write
data to the I2C Bus, so the slave device must read data
from the I2C Bus as a receiver.
S D A
Start Bit
Slave Address
The master must select a device for transferring the
data by sending the slave device address after the
START signal. All device in the I2C Bus will receive the
I2C Bus slave address (7 bits) to compare with its own
slave address (7 bits). If the slave address is matched,
the slave device will generate an interrupt and save the
following bit (8th bit) to SRW bit and sends an acknowledge bit (low level) to the 9th bit. The slave device also
sets the status flag (HAAS), when the slave address is
matched.
Rev. 1.60
23
May 3, 2004
HT46R23/HT46C23
S C L
S ta rt
S R W
S la v e A d d r e s s
0
1
S D A
1
1
0
1
0
1
D a ta
S C L
1
0
0
1
A C K
0
A C K
0
1
0
S to p
0
S D A
S = S
S A =
S R =
M = S
D = D
A = A
P = S
S
ta rt (1
S la v e
S R W
la v e d
a ta (8
C K (R
to p (1
S A
b it)
A d d r e s s ( 7 b its )
b it ( 1 b it)
e v ic e s e n d a c k n o w le d g e b it ( 1 b it)
b its )
X A K b it fo r tr a n s m itte r , T X A K b it fo r r e c e iv e r 1 b it)
b it)
S R
M
D
A
D
A
S
S A
S R
M
D
A
D
A
P
I2C Communication Timing Diagram
Acknowledge Bit
Data Byte
One of the slave device generates an acknowledge signal,
when the slave address is matched. The master device
can check this acknowledge bit to know if the slave device
accepts the calling address. If no acknowledge bit, the
master must send a STOP bit and end the communication.
When the I2C Bus status register bit 6 HAAS is high, it
means the address is matched, so the slave must check
SRW as a transmitter (set HTX) to ²1² or as a receiver
(clear HTX) to ²0².
The data is 8 bits and is sent after the slave device has
acknowledges the slave address. The first bit is MSB
and the 8th bit is LSB. The receiver sends the acknowledge signal (²0²) and continues to receive the next one
byte data. If the transmitter checks and there¢s no acknowledge signal, then it release the SDA line, and the
master sends a STOP signal to release the I2C Bus. The
data is stored in the HDR register. The transmitter must
write data to the HDR before transmit data and the receiver must read data from the HDR after receiving
data.
S C L
S C L
S D A
S D A
Stop Bit
S ta r t b it
S to p b it
D a ta
s ta b le
D a ta
a llo w
c h a n g e
Data Timing Diagram
Rev. 1.60
24
May 3, 2004
HT46R23/HT46C23
Receive Acknowledge Bit
When the receiver wants to continue to receive the next data byte, it generates an acknowledge bit (TXAK) at the 9th
clock. The transmitter checks the acknowledge bit (RXAK) to continue to write data to the I2C Bus or change to receive
mode and dummy read the HDR register to release the SDA line and the master sends the STOP signal.
Options
The following table shows all kinds of options in the microcontroller. All of the options must be defined to ensure proper
system function.
No.
Options
1
OSC type selection.
This option is to decide if an RC or crystal oscillator is chosen as system clock.
2
WDT source selection.
There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
3
CLRWDT times selection.
This option defines how to clear the WDT by instruction. ²One time² means that the CLR WDT instruction can
clear the WDT. ²Two times² means only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then WDT can be cleared.
4
Wake-up selection.
This option defines the wake-up function activity. External I/O pins (PA only) all have the capability to wake-up
the chip from a HALT.
5
Pull-high selection.
This option is to decide whether a pull-high resistance is visible or not in the input mode of the I/O ports.
PA0~PA7, can be independently selected.
6
PFD selection:
PA3: level output or PFD output
7
PWM selection: (7+1) or (6+2) mode
PD0: level output or PWM0 output
PD1: level output or PWM1 output
8
WDT time-out period selection.
There are four types of selection: WDT clock source divided by 212, 213, 214 and 215
9
Low voltage reset selection: Enable or disable LVR function.
10
I2C Bus selection:
PA6 and PA7: I/O or I2C Bus function
Rev. 1.60
25
May 3, 2004
HT46R23/HT46C23
Application Circuits
V
D D
0 .0 1 m F *
P A 0 ~ P A 2
V D D
P A 3 /P F D
1 0 0 k W
V
P A 4 /T M R
0 .1 m F
R E S
4 7 0 p F
P A 5 /IN T
1 0 k W
P A 6 /S D A
R
P A 7 /S C L
0 .1 m F *
V S S
P B 0 /A N 0
P B 7 /A N 7
O S C 1
O S C 2
S e e R ig h t S id e
O S C
O S C 1
fS
Y S
/4
C 1
~
O S C
C ir c u it
D D
P C 0 ~ P C 4
C ry s ta l S y s te m
F o r th e v a lu e s ,
s e e ta b le b e lo w
O s c illa to r
O S C 2
R 1
P D 1 /P W M 1
O S C 2
O S C 1
C 2
P D 0 /P W M 0
R C S y s te m O s c illa to r
3 0 k W < R O S C < 7 5 0 k W
H T 4 6 R 2 3 /H T 4 6 C 2 3
O S C
C ir c u it
The following table shows the C1, C2 and R1 value according different crystal values.
C1, C2
R1
4MHz Crystal
Crystal or Resonator
0pF
10kW
4MHz Resonator (3 pin)
0pF
12kW
4MHz Resonator (2 pin)
10pF
12kW
3.58MHz Crystal
0pF
10kW
3.58MHz Resonator (2 pin)
25pF
10kW
2MHz Crystal & Resonator (2 pin)
25pF
10kW
1MHz Crystal
35pF
27kW
480kHz Resonator
300pF
9.1kW
455kHz Resonator
300pF
10kW
429kHz Resonator
300pF
10kW
Note:
The resistance and capacitance for reset circuit should be designed in such a way as to ensure that the VDD is
stable and remains within a valid operating voltage range before bringing RES to high.
²*² Make the length of the wiring, which is connected to the RES pin as short as possible, to avoid noise
interference.
Rev. 1.60
26
May 3, 2004
HT46R23/HT46C23
Instruction Set Summary
Description
Instruction
Cycle
Flag
Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to data memory with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry and result in data memory
Decimal adjust ACC for addition with result in data memory
1
1(1)
1
1
1(1)
1
1
1(1)
1
1(1)
1(1)
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
C
1
1
1
1(1)
1(1)
1(1)
1
1
1
1(1)
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
1
1(1)
1
1(1)
Z
Z
Z
Z
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
1
1(1)
1
1(1)
1
1(1)
1
1(1)
None
None
C
C
None
None
C
C
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
1
1(1)
1
None
None
None
Clear bit of data memory
Set bit of data memory
1(1)
1(1)
None
None
Mnemonic
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Rev. 1.60
27
May 3, 2004
HT46R23/HT46C23
Instruction
Cycle
Flag
Affected
Jump unconditionally
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1(2)
1(2)
1(2)
1(2)
1(3)
1(3)
1(2)
1(2)
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
2(1)
2(1)
None
None
No operation
Clear data memory
Set data memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
1
1(1)
1(1)
1
1
1
1(1)
1
1
None
None
None
TO,PDF
TO(4),PDF(4)
TO(4),PDF(4)
None
None
TO,PDF
Mnemonic
Description
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note:
x: Immediate data
m: Data memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Ö: Flag is affected
-: Flag is not affected
(1)
: If a loading to the PCL register occurs, the execution cycle of instructions will be delayed for one more cycle
(four system clocks).
(2)
: If a skipping to the next instruction occurs, the execution cycle of instructions will be delayed for one more
cycle (four system clocks). Otherwise the original instruction cycle is unchanged.
(3) (1)
:
(4)
Rev. 1.60
and (2)
: The flags may be affected by the execution status. If the Watchdog Timer is cleared by executing the
CLR WDT1 or CLR WDT2 instruction, the TO and PDF are cleared.
Otherwise the TO and PDF flags remain unchanged.
28
May 3, 2004
HT46R23/HT46C23
Instruction Definition
ADC A,[m]
Add data memory and carry to the accumulator
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add the accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to the accumulator
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to the accumulator
Description
The contents of the accumulator and the specified data are added, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
ADDM A,[m]
Add the accumulator to the data memory
Description
The contents of the specified data memory and the accumulator are added. The result is
stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
29
May 3, 2004
HT46R23/HT46C23
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory perform a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_AND operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with the accumulator
Description
Data in the specified data memory and the accumulator perform a bitwise logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated address. The
program counter increments once to obtain the address of the next instruction, and pushes
this onto the stack. The indicated address is then loaded. Program execution continues
with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR [m]
Clear data memory
Description
The contents of the specified data memory are cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
30
May 3, 2004
HT46R23/HT46C23
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
CLR WDT
Clear Watchdog Timer
Description
The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are
cleared.
Operation
WDT ¬ 00H
PDF and TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
0
¾
¾
¾
¾
CLR WDT1
Preclear Watchdog Timer
Description
Together with CLR WDT2, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction just sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear Watchdog Timer
Description
Together with CLR WDT1, clears the WDT. PDF and TO are also cleared. Only execution
of this instruction without the other preclear instruction, sets the indicated flag which implies this instruction has been executed and the TO and PDF flags remain unchanged.
Operation
WDT ¬ 00H*
PDF and TO ¬ 0*
Affected flag(s)
TO
PDF
OV
Z
AC
C
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
31
May 3, 2004
HT46R23/HT46C23
CPLA [m]
Complement data memory and place result in the accumulator
Description
Each bit of the specified data memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice-versa. The complemented result
is stored in the accumulator and the contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Coded Decimal) code. The accumulator is divided into two nibbles. Each nibble is adjusted to the BCD code and an internal
carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the original value if the original value is greater than 9 or a
carry (AC or C) is set; otherwise the original value remains unchanged. The result is stored
in the data memory and only the carry flag (C) may be affected.
Operation
If ACC.3~ACC.0 >9 or AC=1
then [m].3~[m].0 ¬ (ACC.3~ACC.0)+6, AC1=AC
else [m].3~[m].0 ¬ (ACC.3~ACC.0), AC1=0
and
If ACC.7~ACC.4+AC1 >9 or C=1
then [m].7~[m].4 ¬ ACC.7~ACC.4+6+AC1,C=1
else [m].7~[m].4 ¬ ACC.7~ACC.4+AC1,C=C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
DEC [m]
Decrement data memory
Description
Data in the specified data memory is decremented by 1.
Operation
[m] ¬ [m]-1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
DECA [m]
Decrement data memory and place result in the accumulator
Description
Data in the specified data memory is decremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]-1
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
32
May 3, 2004
HT46R23/HT46C23
HALT
Enter power down mode
Description
This instruction stops program execution and turns off the system clock. The contents of
the RAM and registers are retained. The WDT and prescaler are cleared. The power down
bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Operation
PC ¬ PC+1
PDF ¬ 1
TO ¬ 0
Affected flag(s)
TO
PDF
OV
Z
AC
C
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by 1
Operation
[m] ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in the accumulator
Description
Data in the specified data memory is incremented by 1, leaving the result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
JMP addr
Directly jump
Description
The program counter are replaced with the directly-specified address unconditionally, and
control is passed to this destination.
Operation
PC ¬addr
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV A,[m]
Move data memory to the accumulator
Description
The contents of the specified data memory are copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
33
May 3, 2004
HT46R23/HT46C23
MOV A,x
Move immediate data to the accumulator
Description
The 8-bit data specified by the code is loaded into the accumulator.
Operation
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
MOV [m],A
Move the accumulator to data memory
Description
The contents of the accumulator are copied to the specified data memory (one of the data
memories).
Operation
[m] ¬ACC
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data memories) perform a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical_OR operation.
The result is stored in the accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with the accumulator
Description
Data in the data memory (one of the data memories) and the accumulator perform a
bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ACC ²OR² [m]
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
34
May 3, 2004
HT46R23/HT46C23
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a 2-cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RET A,x
Return and place immediate data in the accumulator
Description
The program counter is restored from the stack and the accumulator loaded with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and interrupts are enabled by setting the
EMI bit. EMI is the enable master (global) interrupt bit.
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory are rotated 1 bit left with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit left with bit 7 rotated into bit 0, leaving the
rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
35
May 3, 2004
HT46R23/HT46C23
RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the carry bit; the original carry flag is rotated into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in the accumulator
Description
Data in the specified data memory and the carry flag are rotated 1 bit left. Bit 7 replaces the
carry bit and the original carry flag is rotated into bit 0 position. The rotated result is stored
in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated 1 bit right with bit 0 rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRA [m]
Rotate right and place result in the accumulator
Description
Data in the specified data memory is rotated 1 bit right with bit 0 rotated into bit 7, leaving
the rotated result in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated 1 bit
right. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
36
May 3, 2004
HT46R23/HT46C23
RRCA [m]
Rotate right through carry and place result in the accumulator
Description
Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces
the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is
stored in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
SBC A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from the accumulator
Description
The contents of the specified data memory and the complement of the carry flag are subtracted from the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. If the result is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, [m] ¬ ([m]-1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SDZA [m]
Decrement data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are decremented by 1. If the result is 0, the next
instruction is skipped. The result is stored in the accumulator but the data memory remains
unchanged. If the result is 0, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]-1)=0, ACC ¬ ([m]-1)
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
37
May 3, 2004
HT46R23/HT46C23
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SET [m]. i
Set bit of data memory
Description
Bit i of the specified data memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a
dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with
the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SIZA [m]
Increment data memory and place result in ACC, skip if 0
Description
The contents of the specified data memory are incremented by 1. If the result is 0, the next
instruction is skipped and the result is stored in the accumulator. The data memory remains unchanged. If the result is 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper
instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not 0
Description
If bit i of the specified data memory is not 0, the next instruction is skipped. If bit i of the data
memory is not 0, the following instruction, fetched during the current instruction execution,
is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i¹0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
38
May 3, 2004
HT46R23/HT46C23
SUB A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from the accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the
result in the data memory.
Operation
[m] ¬ ACC+[m]+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SUB A,x
Subtract immediate data from the accumulator
Description
The immediate data specified by the code is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (1 of the data memories) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in the accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
39
May 3, 2004
HT46R23/HT46C23
SZ [m]
Skip if data memory is 0
Description
If the contents of the specified data memory are 0, the following instruction, fetched during
the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZA [m]
Move data memory to ACC, skip if 0
Description
The contents of the specified data memory are copied to the accumulator. If the contents is
0, the following instruction, fetched during the current instruction execution, is discarded
and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed
with the next instruction (1 cycle).
Operation
Skip if [m]=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is 0
Description
If bit i of the specified data memory is 0, the following instruction, fetched during the current
instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles). Otherwise proceed with the next instruction (1 cycle).
Operation
Skip if [m].i=0
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move the ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer (TBLP) is moved
to the specified data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move the ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP) is moved to
the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
40
May 3, 2004
HT46R23/HT46C23
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory perform a bitwise logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with the accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise logical Exclusive_OR operation. The result is stored in the data memory. The 0 flag is affected.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to the accumulator
Description
Data in the accumulator and the specified data perform a bitwise logical Exclusive_OR operation. The result is stored in the accumulator. The 0 flag is affected.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Rev. 1.60
TO
PDF
OV
Z
AC
C
¾
¾
¾
Ö
¾
¾
41
May 3, 2004
HT46R23/HT46C23
Package Information
24-pin SKDIP (300mil) Outline Dimensions
A
B
2 4
1 3
1
1 2
H
C
D
E
Symbol
A
Rev. 1.60
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
1235
¾
1265
B
255
¾
265
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
345
¾
360
a
0°
¾
15°
42
May 3, 2004
HT46R23/HT46C23
28-pin SKDIP (300mil) Outline Dimensions
A
B
2 8
1 5
1
1 4
H
C
D
E
Symbol
Rev. 1.60
F
a
G
I
Dimensions in mil
Min.
Nom.
Max.
A
1375
¾
1395
B
278
¾
298
C
125
¾
135
D
125
¾
145
E
16
¾
20
F
50
¾
70
G
¾
100
¾
H
295
¾
315
I
330
¾
375
a
0°
¾
15°
43
May 3, 2004
HT46R23/HT46C23
24-pin SOP (300mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Rev. 1.60
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
590
¾
614
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
44
May 3, 2004
HT46R23/HT46C23
28-pin SOP (300mil) Outline Dimensions
2 8
1 5
A
B
1
1 4
C
C '
G
H
D
E
Symbol
Rev. 1.60
a
F
Dimensions in mil
Min.
Nom.
Max.
A
394
¾
419
B
290
¾
300
C
14
¾
20
C¢
697
¾
713
D
92
¾
104
E
¾
50
¾
F
4
¾
¾
G
32
¾
38
H
4
¾
12
a
0°
¾
10°
45
May 3, 2004
HT46R23/HT46C23
Product Tape and Reel Specifications
Reel Dimensions
D
T 2
A
C
B
T 1
SOP 24W
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
SOP 28W (300mil)
Symbol
Description
Dimensions in mm
A
Reel Outer Diameter
330±1.0
B
Reel Inner Diameter
62±1.5
C
Spindle Hole Diameter
13.0+0.5
-0.2
D
Key Slit Width
2.0±0.5
T1
Space Between Flange
24.8+0.3
-0.2
T2
Reel Thickness
30.2±0.2
Rev. 1.60
46
May 3, 2004
HT46R23/HT46C23
Carrier Tape Dimensions
P 0
D
P 1
t
E
F
W
C
D 1
B 0
P
K 0
A 0
SOP 24W
Symbol
W
Description
Dimensions in mm
Carrier Tape Width
24.0±0.3
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
D
Perforation Diameter
1.55+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.9±0.1
B0
Cavity Width
15.9±0.1
K0
Cavity Depth
3.1±0.1
t
Carrier Tape Thickness
C
Cover Tape Width
0.35±0.05
21.3
SOP 28W
Symbol
Description
Dimensions in mm
W
Carrier Tape Width
P
Cavity Pitch
12.0±0.1
E
Perforation Position
1.75±0.1
F
Cavity to Perforation (Width Direction)
11.5±0.1
24.0±0.3
D
Perforation Diameter
1.5+0.1
D1
Cavity Hole Diameter
1.5+0.25
P0
Perforation Pitch
4.0±0.1
P1
Cavity to Perforation (Length Direction)
2.0±0.1
A0
Cavity Length
10.85±0.1
B0
Cavity Width
18.34±0.1
K0
Cavity Depth
2.97±0.1
t
Carrier Tape Thickness
0.35±0.01
C
Cover Tape Width
Rev. 1.60
21.3
47
May 3, 2004
HT46R23/HT46C23
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 021-6485-5560
Fax: 021-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
43F, SEG Plaza, Shen Nan Zhong Road, Shenzhen, China 518031
Tel: 0755-8346-5589
Fax: 0755-8346-5590
ISDN: 0755-8346-5591
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 010-6641-0030, 6641-7751, 6641-7752
Fax: 010-6641-0125
Holmate Semiconductor, Inc. (North America Sales Office)
46712 Fremont Blvd., Fremont, CA 94538
Tel: 510-252-9880
Fax: 510-252-9885
http://www.holmate.com
Copyright Ó 2004 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.60
48
May 3, 2004