HOLTEK HT82A851R

HT82A851R
USB Audio MCU
Features
· Operating voltage: fSYS = 6M/12MHz: 3.3V~5.5V
· Two hardware implemented Isochronous transfers
· 16 bidirectional I/O lines (max.)
· Total FIFO size: 464 bytes
(8, 8, 384, 32, 32 for EP0~EP4)
· Two 16-bit programmable timer/event counters and
· Programmable frequency divider (PFD)
overflow interrupts
· 4096´15 program memory ROM
· Integrated SPI hardware circuit
· 384´8 data memory RAM (Bank0,1)
· Play/Record Interrupt
· USB 2.0 full speed compatible
· HALT and wake-up features reduce power
consumption
· USB spec V1.1 full speed operation and USB audio
· Watchdog Timer
device class spec V1.0
· Built-in digital PGA (Programmable Gain Amplifier)
· 16-level subroutine nesting
· 48kHz/8kHz sampling rate for audio playback
· Bit manipulation instruction
· 15-bit table read instruction
controlled by software option
· 8kHz audio recording sampling rate
· 63 powerful instructions
· Supports audio playback digital volume control
· All instructions executed within one or two machine
· 5 endpoints supported (endpoint 0 included)
cycles
· Low voltage reset function (3.0V±0.3V)
· Supports 1 Control, 2 Interrupt, 2 Isochronous
· 24-pin SSOP package
transfer
General Description
gle chip. The play frequency in the HT82A851R operates at a sampling rate of 48/8kHz. HT82A851R has a
digital programmable gain amplifier. The gain range is
from -32dB to +6dB. For the Isochronous input, the digital gain range is from 0dB to 19.5dB.
The HT82A851R is an 8-bit high performance RISC-like
microcontroller designed for wireless USB Phone product applications. The HT82A851R combines a SPI,
USB transceiver, SIE (Serial Interface Engine), audio
class processing unit, FIFO and an 8-bit MCU into a sin-
Rev. 1.20
1
June 15, 2007
HT82A851R
Block Diagram
S T A C K 0
B P
S T A C K 1
S T A C K 2
P ro g ra m
C o u n te r
M
S T A C K 1 5
M
T M R 1 C
M
M P
U
X
P C 1 /T M R 0
fS
U
X
D A T A
M e m o ry
X
/4
Y S
IN T C
T M R 1
In s tr u c tio n
R e g is te r
U
T M R 0
S T A C K 1 4
P ro g ra m
R O M
fS
T M R 0 C
In te rru p t
C ir c u it
E N /D IS
W D T P r e s c a le r
P A C
P O R T A
P A
S T A T U S
A L U
P C C
P O R T C
P C
A C C
O S C I
V 3 3 O
U
fS
X
Y S
/4
W D T O S C
P A 0 ~ P A 7
S h ifte r
T im in g
G e n e ra to r
U S B D P
M
W D T
M U X
In s tr u c tio n
D e c o d e r
U S B D N
/4
P C 2 /T M R 1
W D T S
O S C O
Y S
U S B 1 .1 X C V R
3 .3 V R e g u la to r
F IF O
D ig ita l
P G A
S e r ia l
In te rfa c e
U S B 1 .1
F u ll S p e e d E n g in e
P F D
P C 3
M
U
X
P C 4 ~ P C 7
(S D O , S D I, S C S , S C K )
P C 0 /B Z
D ig ita l V o lu m e
C o n tro l
Pin Assignment
P A 3
1
2 4
P A 4
P A 2
2
2 3
P A 5
P A 1
3
2 2
P A 6
P A 0
4
2 1
P A 7
P C 7 /S C K
5
2 0
D V S S 1
P C 6 /S C S
6
1 9
V 3 3 O
7
1 8
U S B D P
P C 4 /S D O
8
1 7
U S B D N
P C 3
P C 5 /S D I
9
1 6
D V D D 1
P C 2 /T M R 1
1 0
1 5
R E S E T
P C 1 /T M R 0
1 1
1 4
O S C O
P C 0 /B Z
1 2
1 3
O S C I
H T 8 2 A 8 5 1 R
2 4 S S O P -A
Rev. 1.20
2
June 15, 2007
HT82A851R
Pin Description
Pin Name
I/O
Description
PA0~PA7
I/O
Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up input by a
configuration option. Software instructions determine if the pin is a CMOS output or a Schmitt
trigger input. Pull-high resistor can be connected to the pins via configuration options - nibble
option.
PC7/SCK
I/O
Can be software optioned as a bidirectional input/output or serial interface clock signal.
PC6/SCS
I/O
Can be software optioned as a bidirectional input/output or serial interface slave select signal.
PC5/SDI
I/O or
Can be software optioned as a bidirectional input/output or serial data input.
O
PC4/SDO
I/O or
Can be software optioned as a bidirectional input/output or serial data output.
O
PC3
I/O
Bidirectional I/O lines. Software instructions determine if the pin is a CMOS output or a Schmitt
trigger input. Pull-high resistor can be connected to the pins via configuration options.
PC2/TMR1,
PC1/TMR0
I/O
Software instructions determine if the pin is a CMOS output or a Schmitt trigger input. Pull-high
resistor can be connected to the pins via configuration options.TMR0, TMR1 are pin shared with
PC1, PC2 respectively.
PC0/BZ
I/O or
Can be software optioned as a bidirectional input/output or as a PFD output.
O
OSCI
OSCO
I
O
OSCI, OSCO are connected to an 6MHz or 12MHz crystal/resonator (determined by software
instructions) for the internal system clock
RESET
I
Schmitt trigger reset input, active low
DVDD1
¾
Positive digital power supply
USBDN
I/O
USBD- line. The USB function is controlled by a software control register
USBDP
I/O
USBD+ line. The USB function is controlled by a software control register
V33O
O
3.3V regulator output
DVSS1
¾
Negative digital power supply, ground
Absolute Maximum Ratings
Supply Voltage ...........................VSS-0.3V to VSS+6.0V
Storage Temperature ............................-50°C to 125°C
Input Voltage..............................VSS-0.3V to VDD+0.3V
Operating Temperature...........................-40°C to 85°C
IOL Total ..............................................................150mA
IOH Total............................................................-100mA
Total Power Dissipation .....................................500mW
Note: These are stress ratings only. Stresses exceeding the range specified under ²Absolute Maximum Ratings² may
cause substantial damage to the device. Functional operation of this device at other conditions beyond those
listed in the specification is not implied and prolonged exposure to extreme conditions may affect device
reliability.
Rev. 1.20
3
June 15, 2007
HT82A851R
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
VDD
Conditions
¾
Min.
Typ.
Max.
Unit
3.3
5.0
5.5
V
VDD
Operating Voltage
5V
IDD
Operating Current
5V
No load, fSYS=12MHz
¾
5
¾
mA
ISUS
Suspend Current
5V
No load, system HALT,
USB transceiver and 3.3V
regulator on
¾
350
¾
mA
VIL1
Input Low Voltage for I/O Ports
5V
¾
0
¾
0.3VDD
V
VIH1
Input High Voltage for I/O Ports
5V
¾
0.7VDD
¾
VDD
V
VIL2
Input Low Voltage (RESET)
5V
¾
0
¾
0.4VDD
V
VIH2
Input High Voltage (RESET)
5V
¾
0.9VDD
¾
VDD
V
IOL
I/O Port Sink Current
5V
VOL=0.1VDD
¾
5
¾
mA
IOH
I/O Port Source Current
5V
VOH=0.7VDD
¾
-5
¾
mA
RPH
Pull-high Resistance
5V
¾
30
40
80
kW
VLVR
Low Voltage Reset
5V
¾
2.7
3.0
3.3
V
VV33O
3.3V Regulator Output
5V
3.0
3.3
3.6
V
IV33O=-5mA
A.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
0.4
¾
12
MHz
5V
¾
¾
100
¾
ms
RESET Input Pulse Width
¾
¾
1
¾
¾
ms
tSST
System Start-up Timer Period
¾
¾
¾
1024
¾
tSYS
tINT
Interrupt Pulse Width
¾
¾
1
¾
¾
ms
VDD
Conditions
5V
tWDTOSC Watchdog Oscillator Period
tRES
fSYS
System Clock (Crystal OSC)
Note: tSYS=1/fSYS
Rev. 1.20
4
June 15, 2007
HT82A851R
Functional Description
points to the memory word containing the next
instruction code.
Execution Flow
The microcontroller system clock is sourced from a
crystal oscillator. The system clock is internally divided
into four non-overlapping clocks. One instruction cycle
consists of four system clock cycles.
When executing a jump instruction, a conditional skip
execution, loading to the PCL register, performing a
subroutine call or returning from a subroutine, an initial
reset, an internal interrupt, external interrupt or return
from interrupts, the PC manipulates the program
transfer by loading the address corresponding to each
instruction.
Instruction fetching and execution are pipelined in such
a way that a fetch takes an instruction cycle while
decoding and execution takes the next instruction cycle.
However, the pipelining scheme causes each
instruction to be effectively executed in a cycle. If an
instruction changes the program counter, two cycles are
required to complete the instruction.
Program Counter - PC
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise the next instruction is executed.
The program counter, PC, controls the sequence in
which the instructions stored in the program memory are
executed. Its contents specify the full program memory
range.
The lower byte of the program counter, PCL, is a
readable and writeable register. Moving data into the
PCL performs a short jump. The destination will be
within the current program memory page.
After accessing a program memory word to fetch an
instruction code, the contents of the program counter
are incremented by one. The program counter then
When a control transfer takes place, an additional
dummy cycle is required.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
P C + 2
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Program Counter
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial Reset
0
0
0
0
0
0
0
0
0
0
0
0
Reserved
0
0
0
0
0
0
0
0
0
1
0
0
Timer/Event Counter 0 Overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/Event Counter 1 Overflow
0
0
0
0
0
0
0
0
1
1
0
0
Play Interrupt
0
0
0
0
0
0
0
1
0
0
0
0
Serial Interface Interrupt
0
0
0
0
0
0
0
1
0
1
0
0
Record Interrupt
0
0
0
0
0
0
0
1
1
0
0
0
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, Call Branch
#11
#10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from Subroutine
S11
S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Skip
Program Counter+2
Program Counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
Rev. 1.20
@7~@0: PCL bits
5
June 15, 2007
HT82A851R
Program Memory - PROM
rupt is enabled and the stack is not full, the program
begins execution at location 00CH.
The program memory is used to store the executable
program instructions which are to be executed. It also
contains data, table, and interrupt entries, and is organized into 4096´15 bits, addressed by the program
counter and table pointer.
· Location 010H
This area is reserved for the play interrupt service program. If play data is valid, and the interrupt is enabled
and the stack is not full, the program begins execution
at location 010H.
Certain locations in the program memory are reserved
for special usage:
· Location 000H
This area is reserved for program initialization. After a
chip reset, the program always begins execution at location 000H.
· Location 014H
· Location 004H
· Location 018H
This area is reserved for when 8 bits of data have
been received or transmitted successfully from the serial interface. If the related interrupts are enabled, and
the stack is not full, the program begins execution at
location 014H.
This area is reserved for the USB interrupt service
program. If the USB interrupt is activated, the interrupt
is enabled and the stack is not full, the program begins
execution at location 004H.
This area is reserved for the record interrupt service
program. If the record frequency time out (8kHz), the
interrupt is enabled and the stack is not full, the program begins execution at location 018H.
· Location 008H
· Table location
This area is reserved for the Timer/Event Counter 0 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 0 overflow, and if the interrupt is enabled and the stack is not full, the program
begins execution at location 008H.
Any location in the program memory can be used as a
look-up table. There are three method to read the program memory data. The first method uses the
TABRDC instruction to transfer the contents of the
current page lower-order byte to the specified data
memory, and the current page higher-order byte to the
TBLH register. The second method uses the TABRDL
instruction to transfer the contents of the last page
lower-order byte to the specified data memory, and
the last page higher-order byte to the TBLH register.
The third method uses the TABRDC instruction together with the TBLP and TBHP pointers to transfer
the contents of the lower order byte at the specified
address to the specified data memory, and the higher
order byte at the specified address to the TBLH register. Before accessing the table data, the address to be
read must be placed in the table pointer registers,
TBLP and TBHP. Note that if the configuration option
TBHP is disabled, then the value in TBHP has no effect. Only the destination of the lower-order byte in the
table is well-defined, the other bits of the table word
are transferred to the lower portion of TBLH, and the
remaining 1-bit word is read as ²0².The Table
Higher-order byte register, TBLH, is read only. The
TBLH register is read only and cannot be restored. If
the main routine and the ISR (Interrupt Service Routine) both employ the table read instruction, the contents of TBLH in the main routine are likely to be
changed by the table read instruction used in the ISR.
· Location 00CH
This area is reserved for the Timer/Event Counter 1 interrupt service program. If a timer interrupt results
from a Timer/Event Counter 1 overflow, and the inter0 0 0 H
D e v ic e In itia liz a tio n P r o g r a m
0 0 4 H
0 0 8 H
0 0 C H
U S B In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 0 In te r r u p t S u b r o u tin e
T im e r /E v e n t C o u n te r 1 In te r r u p t S u b r o u tin e
0 1 0 H
0 1 4 H
P ro g ra m
M e m o ry
P la y In te r r u p t S u b r o u tin e
S e r ia l In te r fa c e In te r r u p t S u b r o u tin e
0 1 8 H
R e c o r d In te r r u p t S u b r o u tin e
0 1 B H
0 2 0 H
L o o k - u p T a b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
1 to F
Program Memory
Instruction
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table Location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits when TBHP is disabled
P11~P8: Current program counter bits
@7~@0: Table pointer bits
TBHP register bit3~bit0 when TBHP is enabled
Rev. 1.20
6
June 15, 2007
HT82A851R
In such cases errors can occur. Therefore, using the
table read instruction in the main routine and the ISR
simultaneously should be avoided. However, if the table read instruction has to be used in both the main
routine and the ISR, the interrupt should be disabled
prior to the table read instruction. It should not be
re-enabled until TBLH has been backed up.
All table related instructions require two cycles to
complete the operation. These areas may function as
normal program memory depending upon requirements.
0 0
0 1
0 2
0 3
0 4
0 5
0 6
0 7
0 8
0 9
0 A
0 B
0 C
0 D
0 E
0 F
1 0
1 1
1 2
1 3
1 4
1 5
1 6
1 7
1 8
1 9
1 A
1 B
1 C
1 D
1 E
1 F
2 0
2 1
2 2
2 3
2 4
2 5
2 6
2 7
2 8
2 9
2 A
2 B
2 C
2 D
2 E
2 F
3 0
3 1
3 2
3 3
3 4
3 5
3 6
3 7
3 8
3 9
3 A
3 B
3 C
3 D
3 E
3 F
4 0
Stack Register - STACK
This is a special part of the memory which is used to
save the contents of the program counter only. The
stack is organised into 16 levels and is neither part of the
data nor part of the program space, and is neither
readable nor writeable. The activated level is indexed by
the stack pointer, SP, which is neither readable nor
writeable. At a subroutine call or interrupt acknowledge
signal, the contents of the program counter are pushed
onto the stack. At the end of a subroutine or an interrupt
routine, signaled by a return instruction, RET or RETI,
the program counter is restored to its previous value
from the stack. After a chip reset, the SP will point to the
top of the stack.
If the stack is full and a non-masked interrupt takes
place, the interrupt request flag will be recorded but the
acknowledge signal will be inhibited. When the stack
pointer is decremented, using RET or RETI, the
interrupt will be serviced. This feature prevents a stack
overflow allowing the programmer to use the structure
more easily. In a similar case, if the stack is full and a
²CALL² is subsequently executed, a stack overflow will
occur and the first entry will be lost. Only the most recent
16 return addresses are stored.
Data Memory - RAM
The data memory is divided into two functional groups.
These are the special function registers and the general
purpose data memory in Bank0 and Bank1: 384´8 bits.
Most are read/write, but some are read only. The special
function registers are overlapped in all banks.
Any unused space before 40H is reserved for future
expanded usage and if read will return a value of ²00H².
The general purpose data memory, addressed from 40H
to FFH, is used for data and control information under
instruction commands.
All data memory areas can handle arithmetic, logical,
increment, decrement and rotate operations directly.
Except for some dedicated bits, each bit in the data
memory can be set and reset by ²SET [m].i² and ²CLR
[m].i². They are also indirectly accessible through the
memory pointer registers, MP0 or MP1.
B a n k 0 S p e c ia l R e g is te r
In d ir e c t A d d r e s s in g R e g is te r 0
M P 0
In d ir e c t A d d r e s s in g R e g is te r 1
M P 1
B P
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C 0
T M R 0 H
T M R 0 L
T M R 0 C
T M R 1 H
T M R 1 L
T M R 1 C
P A
P A C
P B
P B C
P C
P C C
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
U S V C
H
H
IN T C 1
T B H P
U S C
U S R
U C C
A W R
S T A L L
S IE S
M IS C
S E T IO
F IF O 0
F IF O 1
F IF O 2
F IF O 3
F IF O 4
D A C _ L IM IT _ L
D A C _ L IM IT _ H
D A C _ W R
P G A _ C T R L
P F D C
P F D D
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
S p e c ia l P u r p o s e
D a ta M e m o ry
H
M O D E
S B
S B
R E C O R
R E C O R
H
H
H
H
H
_ C T R L
C R
D R
D _ IN _ L
D _ IN _ H
H
H
H
H
H
H
H
H
F F H
P L A Y _ D A T A L _ L
P L A Y _ D A T A L _ H
P L A Y _ D A T A R _ L
P L A Y _ D A T A R _ H
R E C O R D _ D A T A _ L
R E C O R D _ D A T A _ H
G e n e ra l P u rp o s e
D a ta R A M
(1 9 2 B y te s )
(B a n k 0 /B a n k 1 )
: U n u s e d
R e a d a s "0 0 "
RAM Mapping
Rev. 1.20
7
June 15, 2007
HT82A851R
Indirect Addressing Register
Status Register - STATUS
Locations 00H and 02H are the indirect addressing
registers, however they are not physically implemented.
Any read/write operation to [00H] or [02H] will access
the data memory pointed to by MP0 and MP1. Reading
location 00H or 02H indirectly will return a result of 00H.
Writing indirectly results in no operation.
This 8-bit register contains the zero flag (Z), carry flag
(C), auxiliary carry flag (AC), overflow flag (OV), power
down flag (PDF), and watchdog time-out flag (TO). It
also records the status information and controls the
operation sequence.
With the exception of the TO and PDF flags, bits in the
status register can be altered by instructions like most
other registers. Any data written into the status register
will not change the TO or PDF flag. In addition,
operations related to the status register may give
different results from those intended.
Data transfer between two indirect addressing registers
is not supported. The memory pointer registers, MP0
and MP1, are 8-bit registers which are used to access
the Data Memory in combination with indirect
addressing registers.
The TO flag can be affected only by a system power-up,
a WDT time-out or executing the ²CLR WDT² or ²HALT²
instruction. The PDF flag can be affected only by
executing the ²HALT² or ²CLR WDT² instruction or
during a system power-up.
Bank Pointer
The bank pointer is used to select the required Data
Memory bank. If Data Memory bank 0 is to be selected,
then a ²0² should be loaded into the BP register. Data
Memory locations before 40H in any bank are
overlapped.
The Z, OV, AC and C flags generally reflect the status of
the latest operations.
Accumulator
The accumulator is closely related to ALU operations. It
is also mapped to location 05H of the data memory and
can carry out immediate data operations. The data
movement between two data memory locations must
pass through the accumulator.
In addition, upon entering the interrupt sequence or executing a subroutine call, the status register will not be
automatically pushed onto the stack. If the contents of
the status are important and if the subroutine can corrupt the status register, precautions must be taken to
save it properly.
Arithmetic and Logic Unit - ALU
Interrupt
This circuit performs 8-bit arithmetic and logic
operations. The ALU provides the following functions:
The device provides a USB interrupt, internal
timer/event counter interrupts, play/record data valid
interrupt and a serial interface interrupt. The Interrupt
Control Register0 (INTC0;0BH) and the interrupt control
register1 (INTC1;1EH) both contain the interrupt control
bits that are used to set the enable/disable status and
interrupt request flags.
· Arithmetic operations - ADD, ADC, SUB, SBC, DAA
· Logic operations - AND, OR, XOR, CPL
· Rotation - RL, RR, RLC, RRC
· Increment and Decrement - INC, DEC
· Branch decision - SZ, SNZ, SIZ, SDZ ....
Once an interrupt subroutine is serviced, all the other
interrupts will be blocked (by clearing the EMI bit). This
scheme may prevent any further interrupt nesting. Other
The ALU not only saves the results of a data operation
but also changes the status register.
Bit No.
Label
Function
0
C
C is set if an operation results in a carry during an addition operation or if a borrow does not
take place during a subtraction operation; otherwise C is cleared. C is also affected by a rotate
through carry instruction.
1
AC
AC is set if an operation results in a carry out of the low nibbles in addition or no borrow from
the high nibble into the low nibble in subtraction; otherwise AC is cleared.
2
Z
3
OV
OV is set if an operation results in a carry into the highest-order bit but not a carry out of the
highest-order bit, or vice versa; otherwise OV is cleared.
4
PDF
PDF is cleared by a system power-up or executing the ²CLR WDT² instruction.
PDF is set by executing the ²HALT² instruction.
5
TO
TO is cleared by a system power-up or executing the ²CLR WDT² or ²HALT² instruction.
TO is set by a WDT time-out.
6~7
¾
Unused bit, read as ²0²
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is cleared.
Status (0AH) Register
Rev. 1.20
8
June 15, 2007
HT82A851R
interrupt requests may occur during this interval but only
the interrupt request flag is recorded. If a certain
interrupt requires servicing within the service routine,
the EMI bit and the corresponding bit of the INTC0 or
INTC1 may be set to allow interrupt nesting. If the stack
is full, the interrupt request will not be acknowledged,
even if the related interrupt is enabled, until the stack
pointer is decremented. If immediate service is desired,
the stack must be prevented from becoming full.
When the interrupt is enabled, the stack is not full and
the USB interrupt is active, a subroutine call to location
04H will occur. The interrupt request flag (USBF) and
EMI bits will be cleared to disable other interrupts.
When the PC Host accesses the FIFO of the
HT82A851R, the corresponding request bit of the USR
is set, and a USB interrupt is triggered. So the user can
easily determine which FIFO has been accessed. When
the interrupt has been served, the corresponding bit
should be cleared by firmware. When the HT82A851R
receives a USB Suspend signal from the Host PC, the
suspend line (bit0 of USC) of the HT82A851R is set and
a USB interrupt is also triggered.
All these kinds of interrupts have a wake-up capability.
As an interrupt is serviced, a control transfer occurs by
pushing the program counter onto the stack, followed by
a branch to a subroutine at specified location in the
program memory. Only the program counter is pushed
onto the stack. If the contents of the register or status
register (STATUS) are altered by the interrupt service
program which corrupts the desired control sequence,
the contents should be saved in advance.
Also when the HT82A851R receives a Resume signal
from the Host PC, the resume line (bit3 of USC) of the
HT82A851R is set and a USB interrupt is triggered.
The internal Timer/Event Counter 0 interrupt is
initialized by setting the Timer/Event Counter 0 interrupt
request flag (bit 5 of INTC0), caused by a timer 0
overflow. When the interrupt is enabled, the stack is not
full and the T0F bit is set, a subroutine call to location
08H will occur. The related interrupt request flag (T0F)
will be reset and the EMI bit cleared to disable further
interrupts.
The USB interrupts are triggered by the following USB
events and the related interrupt request flag (USBF; bit
4 of the INTC0) will be set.
· Accessing the corresponding USB FIFO from the PC
· The USB suspend signal from the PC
· The USB resume signal from the PC
· USB Reset signal
Bit No.
Label
0
EMI
Function
Controls the master (global) interrupt (1=enable; 0=disable)
1
EUI
Controls the USB interrupt (1=enable; 0=disable)
2
ET0I
Controls the Timer/Event Counter 0 interrupt (1=enable; 0=disable)
3
ET1I
Controls the Timer/Event Counter 1 interrupt (1=enable; 0=disable)
4
USBF
USB interrupt request flag (1=active; 0=inactive)
5
T0F
Internal Timer/Event Counter 0 request flag (1=active; 0=inactive)
6
T1F
Internal Timer/Event Counter 1 request flag (1=active; 0=inactive)
7
¾
Unused bit, read as ²0²
INTC0 (0BH) Register
Bit No.
Label
Function
0
EPLAYI
1
ESII
Control Serial interface interrupt (1=enable; 0=disable)
2
RECI
Record interrupt (1=enable; 0=disable)
3, 7
¾
4
PLAYF
5
SIF
6
RECF
Play interrupt (1=enable; 0=disable)
Unused bit, read as ²0²
Play interrupt request flag (1=active; 0=inactive)
Serial interface interrupt request flag (1=active; 0=inactive)
Record interrupt request flag (1=active; 0=inactive)
INTC1 (1EH) Register
Rev. 1.20
9
June 15, 2007
HT82A851R
The internal Timer/Event counter 1 interrupt is initialized
by setting the Timer/Event Counter 1 interrupt request
flag (bit 6 of INTC0), caused by a timer 1 overflow. When
the interrupt is enabled, the stack is not full and T1F is
set, a subroutine call to location 0CH will occur. The
related interrupt request flag (T1F) will be reset and the
EMI bit cleared to disable further interrupts.
It is recommended that a program does not use the
²CALL subroutine² within the interrupt subroutine.
Interrupts often occur in an unpredictable manner or
need to be serviced immediately in some applications. If
only one stack is left and enabling the interrupt is not
well controlled, the original control sequence will be
damaged once the ²CALL² operates in the interrupt
subroutine.
The play interrupt is initialized by setting the play
interrupt request flag (bit 4 of INTC1), caused by a play
data valid. When the interrupt is enabled, the stack is not
full and the PLAYF is set, a subroutine call to location
10H will occur. The related interrupt request flag
(PLAYF) will be reset and the EMI bit cleared to disable
further interrupts. If PLAY_MODE (bit 3 of MODE_CTRL
register) is set to ²1², the play interrupt frequency will
change to 8kHz, otherwise the interrupt frequency is
48kHz.
Oscillator Configuration
The microcontroller contains an integrated oscillator circuit.
O S C I
O S C O
C r y s ta l O s c illa to r
The serial interface interrupt is indicated by the interrupt
flag (SIF; bit 5 of INTC1), that is generated by the
reception or transfer of a complete 8-bits of data
between the HT82A851R and the external device. The
serial interface interrupt is controlled by setting the
Serial interface interrupt control bit (ESII; bit 1 of
INTC1). After the interrupt is enabled (by setting SBEN;
bit 4 of SBCR), and the stack is not full and the SIF is set,
a subroutine call to location 14H occurs.
System Oscillator
This oscillator is designed for the system clock. The
HALT mode stops the system oscillator and ignores any
external signals to conserve power.
A crystal across OSCI and OSCO is needed to provide
the feedback and phase shift required for the oscillator.
No other external components are required. If preferred,
a resonator can also be connected between OSCI and
OSCO for oscillation to occur, but two external
capacitors connected between OSCI, OSCO and
ground are required.
The record interrupt is initialized by setting the record
interrupt request flag (bit 6 of INTC1), caused by a
record frequency time out (8kHz). When the interrupt is
enabled, the stack is not full and RECF is set, a
subroutine call to location 18H will occur. The related
interrupt request flag (RECF) will be reset and the EMI
bit cleared to disable further interrupts.
The WDT oscillator is a free running on-chip RC oscillator, and no external components are required. Even if
the system enters the power down mode, the system
clock stops running, but the WDT oscillator still
continues to run. The WDT oscillator can be disabled by
a configuration option to conserve power.
During the execution of an interrupt subroutine, other
interrupt acknowledge signals are held until the ²RETI²
instruction is executed or the EMI bit and the related
interrupt control bit are set to 1 (if the stack is not full). To
return from the interrupt subroutine, ²RET² or ²RETI²
may be invoked. RETI will set the EMI bit to enable an
interrupt service, but RET will not.
Watchdog Timer - WDT
The WDT clock source is implemented by a dedicated
RC oscillator (WDT oscillator) or the instruction clock
(system clock/4). The timer is designed to prevent a
software malfunction or sequence from jumping to an
unknown location with unpredictable results. The WDT
can be disabled by a configuration option. However, if
the WDT is disabled, all executions related to the WDT
lead to no operation.
Interrupts, occurring in the interval between the rising
edges of two consecutive T2 pulses, will be serviced on
the latter of the two T2 pulses, if the corresponding
interrupts are enabled. In the case of simultaneous
requests the following table shows the priority that is
applied. These can be masked by resetting the EMI bit.
Interrupt Source
Priority
Vector
USB interrupt
1
04H
Timer/Event Counter 0 overflow
2
08H
Timer/Event Counter 1 overflow
3
0CH
Play Interrupt
4
10H
Serial Interface Interrupt
5
14H
Record Interrupt
6
18H
Rev. 1.20
When the WDT clock source is selected, it will be first
divided by 256 (8-stage) to get the nominal time-out
period. By invoking the WDT prescaler, longer time-out
periods can be realized. Writing data to WS2, WS1,
WS0 can give different time-out periods.
The WDT OSC period is typically 65ms. This time-out
period may vary with temperature, VDD and process
variations. The WDT OSC always keeps running in any
operation mode.
10
June 15, 2007
HT82A851R
Bit No.
Label
0
1
2
WS0
WS1
WS2
3~7
¾
Function
Watchdog Timer division ratio selection bits
Bit 2,1,0 = 000, Division Ratio = 1:1
Bit 2,1,0 = 001, Division Ratio = 1:2
Bit 2,1,0 = 010, Division Ratio = 1:4
Bit 2,1,0 = 011, Division Ratio = 1:8
Bit 2,1,0 = 100, Division Ratio = 1:16
Bit 2,1,0 = 101, Division Ratio = 1:32
Bit 2,1,0 = 110, Division Ratio = 1:64
Bit 2,1,0 = 111, Division Ratio = 1:128
Unused bit, read as ²0²
WDTS (09H) Register
W D T O S C
S y s te m C lo c k /4
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
W S 0 ~ W S 2
7 - b it C o u n te r
8 -to -1 M U X
W D T T im e - o u t
Watchdog Timer
· The WDT and WDT prescaler will be cleared and will
If the instruction clock is selected as the WDT clock
source, the WDT operates in the same manner except in
the halt mode. In the HALT mode, the WDT stops counting and lose its protecting purpose. In this situation the
logic can only be re-started by external logic. The high
nibble of the WDTS is reserved for the DAC write mode.
start counting again if the WDT clock is sourced from
the internal WDT oscillator.
· All of the I/O ports remain in their original condition.
· The PDF flag is set and the TO flag is cleared.
The system can leave the Power-down mode by means
of an external reset, an interrupt, an external falling
edge signal on port A or a WDT overflow. An external
reset causes a device initialisation and the WDT
overflow performs a ²warm reset². After the TO and PDF
flags are examined, the cause for the device reset can
be determined. The PDF flag is cleared by a system
power-up or by executing the ²CLR WDT² instruction
and is set when executing the ²HALT² instruction. The
TO flag is set if the WDT time-out occurs, and causes a
wake-up that only resets the program counter and SP;
the others remain in their original status.
The WDT overflow under normal operation initializes a
²chip reset² and sets the status bit ²TO². In the HALT
mode, the overflow initializes a ²warm reset², and only
the program counter and stack pointer are reset to zero.
To clear the contents of the WDT, there are three methods to be adopted, i.e., an external reset (a low level to
RESET), a software instruction, and a ²HALT² instruction. There are two types of software instructions; ²CLR
WDT² and the other set ²CLR WDT1² and ²CLR
WDT2². Of these two types of instruction, only one type
of instruction can be active at a time depending on the
configuration option ²CLR WDT² times selection option.
If the ²CLR WDT² is selected (i.e., CLR WDT times
equal one), any execution of the ²CLR WDT² instruction
clears the WDT. In the case that ²CLR WDT1² and ²CLR
WDT2² are chosen (i.e., CLR WDT times equal two),
these two instructions have to be executed to clear the
WDT; otherwise, the WDT may reset the chip due to a
time-out.
A port A wake-up and interrupt methods can be
considered as a continuation of normal execution. Each
pin in port A can be independently selected to wake-up
the device using configuration options. After awakening
from an I/O port stimulus, the program will resume
execution at the next instruction. If the device is
awakened from an interrupt, two sequence may occur. If
the related interrupt is disabled or the interrupt is
enabled but the stack is full, the program will resume
execution at the next instruction. If the interrupt is
enabled and the stack is not full, the regular interrupt
response takes place. If an interrupt request flag is set to
²1² before entering the Power-down mode, the wake-up
function of the related interrupt will be disabled. Once a
wake-up event occurs, it takes 1024 tSYS (system clock
periods) to resume normal operation, i.e., a dummy
period is inserted. If the wake-up results from an
Power Down Operation - HALT
The Power-down mode is entered by the execution of a
²HALT² instruction and results in the following:
· The system oscillator will be turned off but the WDT
oscillator keeps running if the internal WDT oscillator
is selected.
· The contents of the on-chip data memory and regis-
ters remain unchanged.
Rev. 1.20
11
June 15, 2007
HT82A851R
interrupt acknowledge signal, the actual interrupt
subroutine execution will be delayed by one or more
cycles. If the wake-up results in the next instruction
execution, this will be executed immediately after the
dummy period is finished.
The functional unit chip reset status are shown below.
Program Counter
000H
Interrupt
Disable
WDT
Clear. After master reset,
WDT begins counting
To minimise power consumption, all the I/O pins should
be carefully managed before entering the Power-down
mode.
Timer/event Counter Off
Input/output Ports
Input mode
Reset
Stack Pointer
Points to the top of the stack
There are four ways in which a reset can occur:
V
D D
· RES reset during normal operation
· RES reset during HALT
0 .0 1 m F
1 0 0 k W
· WDT time-out reset during normal operation
R E S E T
· USB reset
1 0 k W
The WDT time-out during HALT is different from other
chip reset conditions, since it can perform a ²warm re set² that resets only the program counter and stack
pointer, leaving the other circuits in their original state.
Some registers remain unchanged during other reset
conditions. Most registers are reset to the ²initial condition² when the reset conditions are met. By examining
the PDF and TO flags, the program can distinguish between different ²chip resets².
TO
PDF
0
0
RESET reset during power-up
u
u
RESET reset during normal operation
0
1
RESET wake-up HALT
0 .1 m F
Reset Circuit
V D D
R E S
C h ip
RESET Conditions
1
u
WDT time-out during normal operation
1
1
WDT wake-up HALT
tS
S T
S S T T im e - o u t
R e s e t
Reset Timing Chart
H A L T
W a rm
R e s e t
W D T
R E S E T
Note: ²u² stands for ²unchanged²
To guarantee that the system oscillator is started and
stabilized, the SST (System Start-up Timer) provides an
extra delay of 1024 system clock pulses when the system resets (power-up, WDT time-out or RES reset) or
the system awakes from the HALT state.
O S C I
S S T
1 0 - b it R ip p le
C o u n te r
S y s te m
C o ld
R e s e t
R e s e t
Reset Configuration
When a system reset occurs, the SST delay is added
during the reset period. Any wake-up from HALT will enable the SST delay.
Rev. 1.20
12
June 15, 2007
HT82A851R
The registers status are summarized in the following table.
Register
MP0
Reset
(Power On)
xxxx xxxx
WDT
RES Reset
Time-out
RES Reset
(Normal
(Normal
(HALT)
Operation)
Operation)
WDT
Time-Out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
BP
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
0000 0000
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
000H
000H
000H
000H
000H
000H
000H
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
0000 0111
0000 0111
Program
Counter
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
--uu uuuu
--01 uuuu
INTC0
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1000
00-0 1000
00-0 1000
00-0 1000
uu-u uuuu
00-0 1000
00-0 1000
TMR1H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
00-0 1---
00-0 1---
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
PCC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
1111 1111
1111 1111
USVC
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
INTC1
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
-000 0000
-000 0000
TBHP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
USC
1000 0000
uuxx uuuu
10xx 0000
10xx 0000
10xx uuuu
1000 0u00
1000 0u00
USR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
00uu 0000
00uu 0000
UCC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
AWR
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
STALL
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SIES
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0u00 u000
0u00 u000
MISC
0000 0000
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
0000 0000
SETIO
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
xxxx x010
FIFO0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO2
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO3
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
FIFO4
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
0000 0000
0000 0000
PGA_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
00uu uuuu
00uu uuuu
Rev. 1.20
13
June 15, 2007
HT82A851R
Register
Reset
(Power On)
WDT
RES Reset
Time-out
RES Reset
(Normal
(Normal
(HALT)
Operation)
Operation)
WDT
Time-Out
(HALT)*
USB Reset USB Reset
(Normal)
(HALT)
PFDC
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0uuu 0000
0uuu 0000
PFDD
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
0uuu 0000
0uuu 0000
MODE_CTRL
0000 0000
0000 0000
0000 0000
0000 0000
0000 0uuu
0000 0uuu
0000 0uuu
SBCR
0110 0000
0110 0000
0110 0000
0110 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
SBDR
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_IN_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
RECORD_IN_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAL_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAL_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAR_L
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
PLAY_DATAR_H
0000 0000
0000 0000
0000 0000
0000 0000
uuuu uuuu
uuuu uuuu
uuuu uuuu
Note: ²*² stands for ²warm reset²
²u² stands for ²unchanged²
²x² stands for ²unknown²
²-² stands for ²undefined²
Two timer/event counters are implemented in the
microcontroller. Each timer contains a 16-bit
programmable count-up counter whose clock may be
sourced from an external or internal clock source. The
internal clock source comes from fSYS/4. The external
clock input allows external events to be counted, time
intervals or pulse widths to be measured, or to generate
an accurate time base. There are three registers related
to Timer/Event Counter 0, TMR0H, TMR0L and TMR0C,
and another three related to Timer/Event Counter 1,
TMR1H, TMR1L and TMR1C. When writing data to the
TMR0L and TMR1L registers, note that the data will only
be written into a lower-order byte buffer. The data will
not be actually written into the TMR0L and TMR1L
registers until a write operation to the TMR0H and
TMR1H registers is implemented. Reading the TMR0L
and TMR1L registers will read the contents of the
lower-order byte buffer. The TMR0C and TMR1C
registers are the Timer/Event Counter control registers,
which define the operating mode, the count enable or
disable and the active edge.
In the event count or timer mode, the timer/event
counter starts counting from the current contents in the
timer/event counter and ends at FFFFH . Once an
overflow occurs, the counter is reloaded from the
timer/event counter preload register, and generates an
interrupt request flag (T0F; bit 5 of INTC0, or T1F; bit 6
of INTC0). In the pulse width measurement mode with
the values of the TON and TE bits equal to 1, after the
TMR0 or TMR1 pin has received a transient from low to
high, or high to low if the TE bit is ²0², it will start counting
until the TMR0 or TMR1 pin returns to its original level
and resets the TON bit. The measured result remains in
the timer/event counter even if the activated transient
occurs again. Therefore, only 1-cycle measurement is
made. Not until the TON bit is again set can the cycle
measurement re-function. In this operational mode, the
timer/event counter begins counting not according to
the logic level but to the transient edges. In the case of
counter overflows, the counter is reloaded from the
timer/event counter register and issues an interrupt
request, as in the other two modes, i.e., event and timer
modes.
The TM0 and TM1 bits define the operation mode. The
event count mode is used to count external events,
which means that the clock source is sourced from the
external TMR0 or TMR1 pin. The timer mode functions
as a normal timer with the clock source coming from the
internal clock. Finally, the pulse width measurement
mode can be used to count the high level or low level
duration of an external signal on pins TMR0 or TMR1,
whose counting is based on the internal clock source.
To enable a count operation, the Timer ON bit (TON; bit
4 of TMR0C or TMR1C) should be set to 1. In the pulse
width measurement mode, TON is automatically
cleared after the measurement cycle is completed. But
in the other two modes, the TON bit can only be reset by
instructions. A Timer/Event Counter overflow is one of
the wake-up sources. No matter what the operational
mode is, writing a 0 to ET0I or ET1I disables the related
interrupt service.
Timer/Event Counter
Rev. 1.20
14
June 15, 2007
HT82A851R
Bit No.
Label
0~2, 5
¾
Unused bit, read as ²0²
3
TE
Defines the TMR active edge of the timer/event counter
In Event counter mode (TM1, TM0)=(0, 1):
1=count on falling edge;
0=count on rising edge
In Pulse width measurement mode (TM1, TM0)=(1, 1):
1=start counting on the rising edge, stop on the falling edge;
0=start counting on the falling edge, stop on the rising edge
4
TON
Enable/disable the timer counting (0=disable; 1=enable)
TM0
TM1
Defines the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
6
7
Function
TMR0C (0EH), TMR1C (11H) Register
fS
Y S /4
f IN
D a ta B u s
T
T M 1
T M 0
T M R 0 /1
1 6 B its
T im e r /E v e n t C o u n te r
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
1 6 B its
T im e r /E v e n t C o u n te r
(T M R 0 /1 )
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/Event Counter 0/1
without pull-high resistor structures can be reconfigured
dynamically (i.e. on-the-fly) under software control. To
function as an input, the corresponding latch of the
control register must write ²1². The input source also
depends on the control register. If the control register bit
is ²1² the input will read the pad state. If the control
register bit is ²0² the contents of the latches will move to
the internal bus. The latter is possible in the
²Read-modify-write² instruction. For output function,
CMOS configurations can be selected. These control
registers are mapped to locations 13H, 17H.
If the timer/event counter is turned OFF, writing data to
the timer/event counter preload register will also reload
the data into the timer/event counter. But if the
timer/event counter is turned on, data written to the
timer/event counter is kept only in the timer/event
counter preload register. The timer/event counter keeps
operating until an overflow occurs.
When the timer/event counter is read, the clock is
blocked to avoid errors, which may result in a counting
error. Blocking of the clock should be taken into account
by the programmer.
After a chip reset, these input/output lines remain at high
levels or floating state (depending on the pull-high
options). Each bit of these input/output latches can be
set or cleared by ²SET [m].i² and ²CLR [m].i² (m=12H,
16H) instructions.
Input/Output Ports
There are 16 bidirectional input/output lines in the
microcontroller, labeled from PA, PC which are mapped
to the data memory of [12H], [16H] respectively. All of
these I/O ports can be used for input and output
operations. For input operation, these ports are
non-latching, that is, the inputs must be ready at the T2
rising edge of instruction ²MOV A,[m]² (m=12H, 16H).
For output operation, all the data is latched and remains
unchanged until the output latch is rewritten.
Some instructions first input data and then follow the
output operations. For example, ²SET [m].i², ²CLR
[m].i², ²CPL [m]², ²CPLA [m]² read the entire port states
into the CPU, execute the defined operations
(bit-operation), and then write the results back to the
latches or the accumulator.
Each I/O line has its own control register (PAC, PCC) to
control the input/output configuration. With this control
register, CMOS output or Schmitt trigger input with or
Rev. 1.20
Each line of port A has the capability of waking-up the
device.
15
June 15, 2007
HT82A851R
C o n tr o l B it
D a ta B u s
W r ite C o n tr o l R e g is te r
Q
D
C K
V
P u ll- H ig h
O p tio n
Q
S
P A
P C
P C
P C
P C
P C
P C
P C
P C
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite D a ta R e g is te r
D a ta B it
Q
D
C K
S
M
U
A 7
Z
M R 0
M R 1
D O
D I
C S
C K
X
W a k e - u p ( P A o n ly )
B Z fo r P
T M R 0 fo r P
T M R 1 fo r P
P
S D O fo r P
S D I fo r P
S C S fo r P
S C K fo r P
0 ~ P
0 /B
1 /T
2 /T
3
4 /S
5 /S
6 /S
7 /S
Q
R e a d D a ta R e g is te r
S y s te m
D D
C o n fig u r a tio n O p tio n
C 0
C 1
C 2
C 3
C 4
C 5
C 6
C 7
Input/Output Ports
Low Voltage Reset - LVR (by Configuration Option)
The LVR includes the following specifications:
the Resume line (bit 3 of USC) will be set. In order to
make the HT82A851R work properly, the firmware must
set USBCKEN (bit 3 of UCC) to ²1² and clear SUSP2
(bit4 of the UCC). Since the Resume signal will be
cleared before the Idle signal is sent out by the host and
the Suspend line (bit 0 of USC) will go to ²0². So when
the MCU is detecting the Suspend line (bit0 of USC), the
condition of the Resume line should be noted and taken
into consideration.
· The low voltage (0.9V~VLVR) condition has to remain
The following is the timing diagram:
The LVR option is 3.0V.
The microcontroller provides a low voltage reset circuit
in order to monitor the supply voltage of the device. If the
supply voltage of the device is within the range
0.9V~VLVR, the LVR will automatically reset the device
internally.
in its condition for a time exceeding 1ms. If the low
voltage state does not exceed 1ms, the LVR will ignore it and will not perform a reset function.
S U S P E N D
U S B R e s u m e S ig n a l
· The LVR uses the ²OR² function with the external
RESET signal to perform a chip reset.
U S B _ IN T
Suspend Wake-Up and Remote Wake-Up
If there is no signal on the USB bus for over 3ms, the
HT82A851R will go into a suspend mode. The Suspend
line (bit 0 of the USC) will be set to ²1² and a USB
interrupt is triggered to indicate that the HT82A851R
should jump to the suspend state to meet the
requirements of the USB suspend current spec.
The device with remote wake up function can wake-up
the USB Host by sending a wake-up pulse through
RMWK (bit 1 of USC). Once the USB Host receives the
wake-up signal from the HT82A851R, it will send a
Resume signal to the device. The timing is as follows:
S U S P E N D
In order to meet the requirements of the suspend
current, the firmware should disable the USB clock by
clearing USBCKEN (bit3 of UCC) to ²0².
R M W K
M in . 2 .5 m s
Also the user can further decrease the suspend current
by setting SUSP2 (bit4 of the UCC).
U S B R e s u m e S ig n a l
When the resume signal is sent out by the host, the
HT82A851R will be woken up by the USB interrupt and
Rev. 1.20
M in . 1
U S B C L K
U S B _ IN T
16
June 15, 2007
HT82A851R
USB Interface
The HT82A851R device has 5 Endpoints (EP0~EP4). EP0 supports Control transfer. EP1 and EP4 support Interrupt
transfer. EP2 supports Isochronous out transfer. EP3 supports Isochronous in transfer.
These registers, including USC (20H), USR (21H), UCC (22H), AWR (23H), STALL (24H), SIES (25H), MISC (26H),
FIFO0 (28H), FIFO1 (29H), FIFO2 (2AH), FIFO3 (2BH), FIFO4 (2CH) are used for the USB function.
The FIFO size of each FIFO is 8 bytes (FIFO0), 8 bytes (FIFO1), 384 bytes (FIFO2), 32 bytes (FIFO3), 32 bytes
(FIFO4). The total is 464 bytes.
URD (bit7 of USC) is the USB reset signal control function definition bit.
Bit No.
Label
R/W
Reset
Functions
0
SUSP
R
0
Read only, USB suspend indication. When this bit is set to ²1² (set by
SIE), it indicates that the USB bus has entered the suspend mode. The
USB interrupt is also triggered when this bit changes from low to high.
1
RMWK
R/W
0
USB remote wake-up command. It is set by MCU to force the USB host
to leave the suspend mode.
0
USB reset indication. This bit is set/cleared by the USB SIE. This bit is
used to detect a USB reset event on the USB bus. When this bit is set to
²1², this indicates that a USB reset has occurred and that a USB
interrupt will be initialized.
2
URST
R/W
3
RESUME
R
0
USB resume indication. When the USB leaves the suspend mode, this
bit is set to ²1² (set by SIE). When the RESUME is set by SIE, an
interrupt will be generated to wake-up the MCU. In order to detect the
suspend state, the MCU should set USBCKEN and clear SUSP2 (in the
UCC register) to enable the SIE detect function. RESUME will be
cleared when the SUSP goes to ²0². When the MCU is detecting the
SUSP, the condition of RESUME (causes the MCU to wake-up) should
be noted and taken into consideration.
4
V33C
R/W
0
0/1: Turn-off/on V33O output
5~6
¾
¾
¾
Undefined bit, read as ²0².
7
URD
R/W
1
USB reset signal control function definition
1: USB reset signal will reset MCU
0: USB reset signal cannot reset MCU
USC (20H) Register
Rev. 1.20
17
June 15, 2007
HT82A851R
The USR (USB endpoint interrupt status register) register is used to indicate which endpoint is accessed and to select
the serial bus (USB). The endpoint request flags (EP0F, EP1F, EP2F, EP3F, EP4F) are used to indicate which endpoints are accessed. If an endpoint is accessed, the related endpoint request flag will be set to ²1² and the USB interrupt will occur (if the USB interrupt is enabled and the stack is not full). When the active endpoint request flag is
serviced, the endpoint request flag has to be cleared to ²0² by software.
Bit No.
Label
R/W
Reset
Functions
0
EP0F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 0 has
been accessed and a USB interrupt will occur. When the interrupt has
been serviced, this bit should be cleared by software.
1
EP1F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 1 has
been accessed and a USB interrupt will occur. When the interrupt has
been serviced, this bit should be cleared by software.
2
EP2F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 2 has
been accessed and a USB interrupt will occur. When the interrupt has
been serviced, this bit should be cleared by software.
3
EP3F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 3 has
been accessed and a USB interrupt will occur. When the interrupt has
been serviced, this bit should be cleared by software.
4
EP4F
R/W
0
When this bit is set to ²1² (set by SIE), it indicates that endpoint 4 has
been accessed and a USB interrupt will occur. When the interrupt has
been serviced, this bit should be cleared by software.
5~7
¾
¾
¾
Undefined bit, read as ²0².
USR (21H) Register
There is a system clock control register implemented to select the clock used in the MCU. This register consists of a
USB clock control bit (USBCKEN), a second suspend mode control bit (SUSP2) and a system clock selection bit
(SYSCLK).
The endpoint selection is determined by EPS2, EPS1 and EPS0.
Bit No.
Label
R/W
Reset
Functions
0~2
EPS0~
EPS2
R/W
0
Accessing endpoint FIFO selection, EPS2, EPS1, EPS0:
000: Select endpoint 0 FIFO
001: Select endpoint 1 FIFO
010: Select endpoint 2 FIFO
011: Select endpoint 3 FIFO
100: Select endpoint 4 FIFO
101: reserved for future expansion, cannot be used
110: reserved for future expansion, cannot be used
111: reserved for future expansion, cannot be used
If the selected endpoints do not exist, the related function will be
absent.
3
USBCKEN
R/W
0
USB clock control bit. When this bit is set to ²1², it indicates that the
USB clock is enabled. Otherwise, the USB clock is turned-off.
4
SUSP2
R/W
0
This bit is used for reducing power consumption in the suspend mode.
In normal mode, clear this bit to ²0²
In the HALT mode, set this bit to ²1² to reducing power consumption.
0
Defines the MCU system clock - sourced from the external OSC or from
the PLL output - 16MHz clock.
0: system clock sourced from OSC
1: system clock sourced from the PLL output - 16MHz
0
Used to specify the system clock oscillator frequency used by MCU.
If a 6MHz crystal oscillator or resonator is used, this bit should be set to
²1².
If a 12MHz crystal oscillator or resonator is used. this bit should be
cleared to ²0².
5
6
fSYS16MHz
SYSCLK
R/W
R/W
UCC (22H) Register
Rev. 1.20
18
June 15, 2007
HT82A851R
The AWR register contains the current address and a remote wake up function control bit. The initial value of AWR is
²00H². The address value extracted from the the USB command has not to be loaded into this register until the SETUP
stage has finished.
Bit No.
Label
R/W
Power-on
0
WKEN
R/W
0
1~7
AD0~AD6
R/W
0000000
Functions
USB remote-wake-up enable/disable (1/0)
USB device address
AWR (23H) Register
The STALL register shows if the corresponding endpoint works properly or not. As soon as the endpoint works improperly, the related bit in the STALL has to be set to ²1². The STALL register will be cleared by a USB reset signal.
Bit No.
Label
R/W
Power-on
Functions
Set by the user when related USB endpoints were stalled.
Cleared by a USB reset and a Setup Token event.
0~4
STL0~STL4
R/W
00000
5~7
STL5~STL7
¾
000
Undefined bit, read as ²0².
STALL (24H) Register
Bit No.
Label
R/W
Power-on
Functions
0
ASET
R/W
0
This bit is used to configure the SIE to automatically change the device
address by the value stored in the AWR register. When this bit is set to
²1² by firmware, the SIE will update the device address by the value
stored in the AWR register after the PC host has successfully read the
data from the device by an IN operation. Otherwise, when this bit is
cleared to ²0², the SIE will update the device address immediately after
an address is written to the AWR register. So, in order to work properly,
the firmware has to clear this bit after a next valid SETUP token is
received.
1
ERR
R/W
0
This bit is used to indicate that some errors have occurred when the
FIFO0 is accessed. This bit is set by SIE and should be cleared by
firmware.
2
OUT
R/W
0
This bit is used to indicate the OUT token (except the OUT zero length
token) has been received. The firmware clears this bit after the OUT data
has been read. Also, this bit will be cleared by SIE after the next valid
SETUP token is received.
3
IN
R
0
This bit is used to indicate the current USB receiving signal from PC host
is an IN token.
4
NAK
R
0
This bit is used to indicate the SIE is a transmitted NAK signal to the host
in response to the PC host IN or OUT token.
5
CRCF
R/W
0
Error condition failure flag include CRC, PID, no integrate token error,
CRCF will be set by hardware and the CRCF need to be cleared by
firmware.
6
EOT
R
1
Token pakcage active flag, low active.
0
NAK token interrupt mask flag. If this bit set, when the device sent a NAK
token to the host, an interrupt will be disabled. Otherwise if this bit is
cleared, when the device sends a NAK token to the host, it will enter the
interrupt sub-routine.
7
NMI
R/W
SIES (25H) Register
Rev. 1.20
19
June 15, 2007
HT82A851R
The MISC register combines command and status to control the desired endpoint FIFO action and to show the status of
the desired endpoint FIFO. MISC will be cleared by a USB reset signal.
Bit No.
0
Label
REQUEST
R/W
R/W
Power-on
Functions
0
After setting the status of the desired one, FIFO can be requested
by setting this bit high . After finishing, this bit must be set low.
1
TX
R/W
0
To represent the direction and transition end MCU access. When
set to logic 1, the MCU desires to write data to the FIFO. After
finishing, this bit must be set to logic 0 before terminating request to
represent transition end. For an MCU read operation, this bit must
be set to logic 0 and set to logic 1 after finishing.
2
CLEAR
R/W
0
MCU requests to clear the FIFO, even if the FIFO is not ready. After
clearing the FIFO, the USB interface will send force_tx_err to tell
the Host that data under-run if the Host wants to read data.
3
ISO_IN_EN
R/W
0
Enables the isochronous in pipe interrupt.
4
ISO_OUT_EN
R/W
0
Enables the isochronous out pipe interrupt.
5
SETCMD
R/W
0
To show that the data in the FIFO is a setup command. This bit will
remain in this state until the next one enters the FIFO.
6
READY
R
0
To show that the desired FIFO is ready
7
LEN0
R
0
To show that the host sent a 0-sized packet to the MCU. This bit
must be cleared by a read action to the corresponding FIFO.
MISC (26H) Register
Bit No.
Label
R/W
Power-on
Functions
0
DATATG*
R/W
0
DATA token toggle bit
1
SETIO1**
R/W
1
Set endpoint1 input or output pipe (1/0), default input pipe(1)
2
SETIO2**
R/W
0
Set endpoint2 input or output pipe (1/0), default output pipe(0)
3
SETIO3**
R/W
1
Set endpoint3 input or output pipe (1/0), default input pipe(1)
4
SETIO4**
R/W
1
Set endpoint4 input or output pipe (1/0), default input pipe(1)
5~7
¾
¾
¾
Undefined bit, read as ²0²
Note: *USB definition: when the host sends a ²set Configuration², the Data pipe should send the DATA0 (about the
Data toggle) first. So, when the Device receives a ²set configuration² setup command, the user needs to toggle
this bit as the following data will send a Data0 first.
**It is only required to set the data pipe as an input pile or output pile. The purpose of this function is to avoid the
host sending a abnormal IN or OUT token and disabling the endpoint.
SETIO (27H) Register, USB Endpoint 1 ~ Endpoint 4 Set IN/OUT Pipe Register
The speaker output volume and speaker mute/un-mute are controlled by the USB Speaker Volume Control register.
The range of the volume is set from 6 dB to -32 dB by software.
Speaker mute control:
MUTE=0: Mute Speaker output
MUTE=1: Normal
Bit No.
Label
R/W
Power-on
Functions
0~6
USVC0~
USVC6
R/W
0
Volume control Bit0~Bit6
7
MUTE
R/W
0
Mute control, low active.
USB Speaker Volume Control (1CH) Register
Rev. 1.20
20
June 15, 2007
HT82A851R
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
Result (dB)
USVC
6
000_1100
-2
111_1100
-10
110_1100
-24
101_1100
5.5
000_1011
-2.5
111_1011
-10.5
110_1011
-25
101_1011
5
000_1010
-3
111_1010
-11
110_1010
-26
101_1010
4.5
000_1001
-3.5
111_1001
-11.5
110_1001
-27
101_1001
4
000_1000
-4
111_1000
-12
110_1000
-28
101_1000
3.5
000_0111
-4.5
111_0111
-13
110_0111
-29
101_0111
3
000_0110
-5
111_0110
-14
110_0110
-30
101_0110
2.5
000_0101
-5.5
111_0101
-15
110_0101
-31
101_0101
2
000_0100
-6
111_0100
-16
110_0100
-32
101_0100
1.5
000_0011
-6.5
111_0011
-17
110_0011
¾
¾
1
000_0010
-7
111_0010
-18
110_0010
¾
¾
0.5
000_0001
-7.5
111_0001
-19
110_0001
¾
¾
0
000_0000
-8
111_0000
-20
110_0000
¾
¾
-0.5
111_1111
-8.5
110_1111
-21
101_1111
¾
¾
-1
111_1110
-9
110_1110
-22
101_1110
¾
¾
-1.5
111_1101
-9.5
110_1101
-23
101_1101
¾
¾
Speaker Volume Control Table
Label
R/W
FIFO0~
FIFO4
Power-on
Functions
xxH
EPi accessing register (i = 0~4). When an endpoint is disabled, the corresponding
accessing register should be disabled.
R/W
FIFO0~4 (28H~2CH) USB Endpoint Accessing Register Definitions
Digital PGA
Bit No.
0~5
Label
Functions
There are six bits to control the digital PGA (0~19.5 dB). The PGA is a digital amplifier
PGA0~PGA5 used to amplify the 16-bit data that comes from the PCM ADC. The PGA value versus
gain relationship is shown in the follow table.
6
¾
7
MUTE_MKB
Undefined bit, read as ²0².
Microphone mute Control:
MUTE_MKB =0: Mute microphone input.
MUTE_MKB =1: Normal.
PGA_CTRL (30H) Register
PGA_CRTL Value (PGA5~PGA0)
Gain (dB)
000000
»0
000001
» 0.5
:
:
:
:
100111
» 19.5
101000
» 19.5
:
:
:
:
111111
» 19.5
Rev. 1.20
21
June 15, 2007
HT82A851R
Writing to RECORD_IN_L register will only put the written data to an internal lower-order byte buffer (8-bit) and writing
RECORD_IN _H will transfer the RECORD_IN _L and RECORD_IN_H registers content to isochronous in buffer.
When record interrupt happened, firmware should write 16-bit 2¢s complement value to RECORD_IN_L and RECORD_IN_H registers.
PFD Control
Label
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PFDC
0
PRES1
PRES0
PFDEN
0
0
PFD_IO
Reserved
PFDD
PFDD7
PFDD6
PFDD5
PFDD4
PFDD3
PFDD2
PFDD1
PFDD0
The PFD (programmable frequency divider) is implemented in the HT82A851R. It is composed of two portions: a
prescaler and a general counter.
The prescaler is controlled by the register bits, PRES0 and PRES1. The 4-stage prescaler is divided by 16. The general
counter is programmed by an 8-bit register PFDD.
The PFDD is inhibited to write while the PFD is disabled. To modify the PFDD contents, the PFD must be enabled.
When the generator is disabled, the PFDD is cleared by hardware.
PFD prescaler selection:
PRES1
PRES0
Prescaler Output
0
0
PFD frequency source ¸ 1
0
1
PFD frequency source ¸ 2
1
0
PFD frequency source ¸ 4
1
1
PFD frequency source ¸ 8
The bit PFD_IO is used to determine whether PC0 is a general purpose I/O port or a PFD output.
Label
Functions
PFD_IO=1
²PC0² is PFD output
PFD_IO=0
²PC0² is a general purpose IO Port (Default =0)
fS
Y S
/4
4 - S ta g e P r e s c a le r
(1 /1 6 )
P F D
F re q u e n c y
P r e s c a le r
P r e s c a le r
O u tp u t
Rev. 1.20
O u tp u t F re q u e n c y =
P r e s c a le r O u tp u t
2 ´ (N + 1 )
P F D
O u tp u t
P F D E N
P R E S 1 , P R E S 0
N o te : P F D
P F D D
, w h e re N
22
= th e v a lu e o f th e P F D
d a ta
June 15, 2007
HT82A851R
SPI
The serial interface function is similar to the Motorola SPI, where four basic signals are included. These are the SDI
(Serial Data Input), SDO (Serial Data Output), SCK (serial clock) and SCS (slave select pin).
S C S
S C K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
SPI Timing
Label
SBCR
Default
SBDR
Default
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
Serial Bus
Data Register
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Note: ²U² unchanged
Two registers, SBCR and SBDR, are provided for serial interface control, status and data storage.
· SBCR: Serial bus control register
¨
¨
Bit7 (CKS): clock source selection: fSIO = fSYS/2, select as 0; fSIO = fSYS, select as 1
Bit6 (M1), Bit5 (M0): master/slave mode and baud rate selection
-
¨
M1, M0=
00: Master mode, baud rate = fSIO
01: Master mode, baud rate = fSIO/4
10: Master mode, baud rate = fSIO/16
11: Slave mode
Bit4 (SBEN): Serial bus enable/disable (1/0)
-
Enable: (SCS dependent on CSEN bit)
Disable ® enable: SCK, SDI, SDO, SCS =0 (SCK=²0²) and wait to write data to SBDR (TXRX buffer)
Master mode: write data to SBDR (TXRX buffer) ® start transmission/reception automatically
Master mode: when data has been transferred ® set TRF
Slave mode: when a SCK (and SCS dependent on CSEN) is received, data in the TXRX buffer is shifted-out and
data on SDI is shifted-in.
-
Disable: SCK (SCK), SDI, SDO, SCS floating and related pins are IO ports.
Label
Functions
SBEN=1
PC4~PC7 are SPI function pins (pin SCS will go low if CSEN=1).
SBEN=0
PC4~PC7 are general purpose I/O Port pins - default
Note: 1. If SBEN=²1², the pull-high resistors on PC4~PC7 will be disabled. When this happens external pull-high
resistors should be added to the SPI related pins if necessary (EX: pin SCS).
2. If CSEN=²0², the SCS pin will enter a floating state.
¨
Bit3 (MLS): MSB or LSB (1/0) shift first control bit
¨
Bit2 (CSEN): serial bus selection signal enable/disable (SCS), when CSEN=0, SCS is floating
¨
Bit1 (WCOL): this bit is set to 1 if data is written to SBDR (TXRX buffer) when the data is transferring
® writing will be ignored if data is written to SBDR (TXRX buffer) when the data is transferring
WCOL will be set by hardware and cleared by software.
¨
Bit 0 (TRF): data transferred or data received ® used to generate an interrupt
Note: data reception is still operational when the MCU enters the Power-down mode
Rev. 1.20
23
June 15, 2007
HT82A851R
· SBDR: Serial bus data register
Data written to SBDR ® write data to the TXRX buffer only
Data read from SBDR ® read from SBDR only
¨
Operating Mode description:
Master transmitter: clock sending and data I/O started by writing to SBDR
Master clock sending started by writing to SBDR
Slave transmitter: data I/O started by clock reception
Slave receiver: data I/O started by clock reception
· Clock polarity = rising (CLK) or falling (CLK): 1 or 0 (software option)
Serial Interface Operation:
Label
Functions
· Select CKS and select M1,M0 = 00, 01, 10
· Select CSEN, MLS (same as slave)
· Set SBEN
· Writing data to SBDR ® data is stored in the TXRX buffer ® output CLK (and SCS) signals ® go
Master
·
·
·
·
·
to step 5 ® (SIO internal operation ® data stored in the TXRX buffer, and the SDI data is shifted
into the TXRX buffer ® data transferred, data in the TXRX buffer is latched into SBDR)
Check WCOL; WCOL = 1 ® clear WCOL and go to step 4; WCOL = 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
· CKS don¢t care and select M1, M0 = 11
· Select CSEN, MLS (same as master)
· Set SBEN
· Writing data to SBDR ® data is store in the TXRX buffer ® waiting for master clock signal (and
Slavehans
·
·
·
·
·
SCS): CLK ® go to step 5 ® (SIO internal operations ® CLK (SCS) received ® output data in
TXRX buffer and SDI data is shifted into the TXRX buffer ® data transferred, data in the TXRX
buffer is latched into SBDR)
Check WCOL; WCOL = 1 ® clear WCOL, go to step 4; WCOL = 0 ® go to step 6
Check TRF or waiting for SBI (serial bus interrupt)
Read data from SBDR
Clear TRF
Go to step 4
· WCOL: master/slave mode, set if writing to SBDR when data is transferring (transmitting or receiving) and this writing
will be ignored. The WCOL function can be enabled/disabled by a software option (SIO_WCOL bit of MODE_CTRL
register). WCOL is set by SIO and cleared by the user.
· Data transmission and reception will continue to operated when the MCU enters the power-down mode.
· CPOL is used to select the clock polarity of CLK and is a software option (SIO_CPOL bit of MODE_CTRL register).
· MLS: MSB or LSB first selection
· CSEN: chip select function enable/disable, CSEN = 1 ® SCS signal function is active. The master should output a
SCS signal before the CLK signal and slave data transferring should be disabled(enabled) before(after) SCS signal
received. CSEN = 0, SCS signal is not needed, SCS pin (master and slave) should be floating.
· CSEN: CSEN software option (SIO_CSEN bit of MODE_CTRL register) is used to enable/disable software CSEN
function. If CSEN software option is disable, software CSEN always disabled. If CSEN software option is enabled,
software CSEN function can be used.
· SBEN = 1 ® serial bus standby; SCS (CSEN = 1) = 1; SCS = floating (CSEN = 0); SDI = floating; SDO = 1; master
CLK = output 1/0 (dependent on CPOL software option), slave CLK = floating
· SBEN = 0 ® serial bus disable; SCS = SDI = SDO = CLK = floating
· TRF is set by SIO and cleared by the user. When the data is transferring (transmission and reception) is complete,
TRF is set to generate SBI (serial bus interrupt).
Rev. 1.20
24
June 15, 2007
HT82A851R
S B E N = 1 , C S E N = 0 a n d w r ite d a ta to S B D R
S C S
S B E N = 1 , C S E N = 1 a n d w r ite d a ta to S B D R
( if p u ll- h ig h e d )
( if p u ll- h ig h e d )
C L K
S D I
S D O
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
D 7 /D 0
D 6 /D 1
D 5 /D 2
D 4 /D 3
D 3 /D 4
D 2 /D 5
D 1 /D 6
D 0 /D 7
C L K
SIO Timing
Label
SBCR
Default
SBDR
Functions
D7
D6
D5
D4
D3
D2
D1
D0
Serial Bus
Control Register
CKS
M1
M0
SBEN
MLS
CSEN
WCOL
TRF
0
1
1
0
0
0
0
0
D7
D6
D5
D4
D3
D2
D1
D0
U
U
U
U
U
U
U
U
Serial Bus
Data Register
Default
D a ta B u s
S B D R
D 7
( R e c e iv e d D a ta R e g is te r )
D 6
D 5
D 4
D 3
D 2
D 1
D 0
M
U
S D O
X
M L S
A n d , S ta rt
E N
S C K
M
U
X
C 0
A n d , S ta rt
C 1
U
X
S D I
T R F
C 2
A N D
C lo c k
P o la r ity
M a s te r o r
S la v e
S B E N
S D O
S B E N
M
In te rn a l B a u d
R a te C lo c k
B u ffe r
W C O L F la g
In te r n a l B u s y F la g
W r ite S B D R
S B E N
W r ite S B D R E n a b le /D is a b le
W r ite S B D R
A n d , S ta rt
S C S
E N
M a s te r o r S la v e
S B E N
C S E N
Block Diagram of SIO
Rev. 1.20
25
June 15, 2007
HT82A851R
Label
Functions
WCOL
Set by SIO cleared by users
CESN
Enable or disable device selection function pin
Master mode: 1/0=with/without SCS output control
Slave mode: 1/0= with/without SCS input control
SBEN
Enable or disable serial bus (0= initialize all status flags)
When SBEN=0, all status flags should be initialized
When SBEN=0, all SIO related function pins should stay in a floating state
TRF
1= data transmitted or received
0= data is transmitting or still not received
If the clock polarity set to rising edge (SIO_CPOL=1), the serial clock timing will follow CLK, otherwise (SIO_CPOL=0)
CLK is the serial clock timing.
Mode Control
The MODE_CTRL register is used to control SPI function.
Bit No.
Label
Functions
0~2
¾
3
PLAY_MODE
4
SIO_CPOL
There are three bits used to control the mode of SPI operation.
1= clock polarity rising edge
0= clock polarity falling edge (default)
5
SIO_WCOL
1= WCOL bit of SBCR register enable
0= WCOL bit of SBCR register disable (default)
6
SIO_CSEN
1= CSEN bit of SBCR register enable
0= CSEN bit of SBCR register disable (Default)
7
¾
Reserved
Play mode control
1= 8kHz/16-bit
0= 48kHz/16-bit (default)
Undefined bit, read as ²0²
MODE_CTRL (34H) Register
SPI Usage Example
SPI_Test:
clr
UCC.@UCC_SYSCLK
;12MHz SYSCLK
set
SIO_CSEN
;SPI Chip Select Function Enable
clr
SIO_CPOL
;falling edge change data
;Master Mode, SCLK=fSIO
clr
M1
clr
M0
;-------------clr
CKS
;fSIO=fSYS/2
clr
TRF
;clear TRF flag
clr
TRF_INT
;clear Interrupt SPI flag
set
MLS
;MSB shift first
set
CSEN
;Chip Select Enable
set
SBEN
;SPI Enable, SCS will go low
if POLLING_MODE
clr
ESII
;SPI Interrupt Disable
;WRITE INTO ²WRITE ENABLE² INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF
jmp
$0
clr
TRF
else
Rev. 1.20
26
June 15, 2007
HT82A851R
set
ESII
;SPI Interrupt Enable
;WRITE INTO "WRITE ENABLE" INSTRUCTION
MOV
A,OP_WREN
MOV
SBDR,A
$0:
snz
TRF_INT
;set at SPI Interrupt
jmp
$0
clr
TRF_INT
endif
Play/Record Data
The play/record interrupt will be activated when play/record data is valid on PLAY_DATA/ RECORD_DATA registers.
The PLAY_DATA/RECORD_DATA registers will latch data until next interrupt happen. The PLAY_DATA is unsigned
value (0~FFFFH). RECORD_DATA is 2¢s complement value (8000H~7FFFH).
The update rate of RECORD_DATA is 8kHz . The update rate of PLAY_DATA is 48kHz (PLAY_MODE=0) or 8KHz
(PLAY_MODE=1). All these registers (3AH~3FH) are read only.
Address
Label
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PL_D6
PL_D5
PL_D4
PL_D3
3AH
PLAY_DATAL_L
PL_D7
PL_D2
PL_D1
PL_D0
3BH
PLAY_DATAL_H
PL_D15 PL_D14 PL_D13 PL_D12 PL_D11 PL_D10
PL_D9
PL_D8
3CH
PLAY_DATAR_L
PR_D7
PR_D1
PR_D0
3DH
PLAY_DATAR_H
PR_D15 PR_D14 PR_D13 PR_D12 PR_D11 PR_D10 PR_D9
PR_D8
3EH
RECORD_DATA_L
R_D7
R_D6
R_D5
R_D4
R_D3
R_D2
R_D1
R_D0
3FH
RECORD_DATA_H
R_D15
R_D14
R_D13
R_D12
R_D11
R_D10
R_D9
R_D8
PR_D6
PR_D5
PR_D4
PR_D3
PR_D2
Configuration Options
The following table shows all of the configuration options in the microcontroller. All of the OTP options must be defined
to ensure proper system functioning.
No.
Option
1
PA0~PA7 pull-high resistor enabled or disabled (by bit)
2
LVR enable or disable
3
WDT enable or disable
4
WDT clock source: fSYS/4 or WDTOSC
5
CLRWDT instruction(s): 1 or 2
6
PA0~PA7 wake-up enabled or disabled (by bit)
7
PC0~PC7 pull-high resistor enabled or disabled (by nibble)
8
TBHP enable or disable (default disable)
Rev. 1.20
27
June 15, 2007
HT82A851R
Application Circuits
J 1
1
V D D
2
D +
3
D -
U S B U S B +
4
V S S
U S B C O N
0 .1 m F
V S S
1
L 6
B e a d
1 .5 k W
3 3 W
3 3 W
U S B A C T IV E
D 1
3 3 0 k W
P A 0
U S B D P
U S B D N
4 7 p F
V 3 3 O
0 .1 m F
4 7 p F
G L E D
1 0 m F
2
1
V D D
L 1
2
A V D D 1
B e a d F e r r ite
0 .1 m F
1 0 m F
A V D D 2
5 0 k W
3 V 3
U 2
5 /3 .3 V
3
V IN
V O U T
V D D
0 .1 m F
2
G N D
1
1 0 m F
A V D D 2
0 .1 m F
1 0 m F
1
P A 2
2
U 1
P A 3
P A 1
3
P A 0
4
P C 7
5
P C 6
6
P C 5
7
P C 4
8
P C 3
9
P C 2
1 0
P C 1
1 1
P C 0
1 2
P A 3
P A 4
P A 2
P A 5
P A 1
P A 6
P A 0
P A 7
P C 7 /S C K
D V S S 1
P C 6 /S C S
V 3 3 O
P C 5 /S D I
U S B D P
P C 4 /S D O
U S B D N
P C 3
D V D D 1
P C 2 /T M R 1
R E S E T
P C 1 /T M R 0
O S C O
O S C I
P C 0 /B Z
2 4
P A 4
2 3
P A 5
2 2
P A 6
2 1
P A 7
2 0
D V S S 1
1 9
V 3 3 O
1 8
U S B D P
1 7
U S B D N
1 6
D V D D 1
1 5
R E S E T
1 4
O S C O
1 3
L 3
2
B e a d F e r r ite
Rev. 1.20
A V S S 2
A V S S 2
1
P C 3
3
P C 7
5
P C 5
7
G N D
V D D
C E
C S N
S C K
M O S I
M IS O
IR Q
H e a d e r 4 x 2
28
1 0 W
D V D D
0 .1 m F
1 0 m F
1 0 0 k W
Y 1
O S C I
0 .1 m F
S W 1
R e s e t
1 2 M H z
H T 8 2 A 8 5 1 R
1
A V D D 1
2
A V D D 2
4
P C 6
6
P C 4
8
P C 2
June 15, 2007
HT82A851R
Instruction Set
subtract instruction mnemonics to enable the necessary
arithmetic to be carried out. Care must be taken to ensure correct handling of carry and borrow data when results exceed 255 for addition and less than 0 for
subtraction. The increment and decrement instructions
INC, INCA, DEC and DECA provide a simple means of
increasing or decreasing by a value of one of the values
in the destination specified.
Introduction
Central to the successful operation of any
microcontroller is its instruction set, which is a set of program instruction codes that directs the microcontroller to
perform certain operations. In the case of Holtek
microcontrollers, a comprehensive and flexible set of
over 60 instructions is provided to enable programmers
to implement their application with the minimum of programming overheads.
Logical and Rotate Operations
For easier understanding of the various instruction
codes, they have been subdivided into several functional groupings.
The standard logical operations such as AND, OR, XOR
and CPL all have their own instruction within the Holtek
microcontroller instruction set. As with the case of most
instructions involving data manipulation, data must pass
through the Accumulator which may involve additional
programming steps. In all logical data operations, the
zero flag may be set if the result of the operation is zero.
Another form of logical data manipulation comes from
the rotate instructions such as RR, RL, RRC and RLC
which provide a simple means of rotating one bit right or
left. Different rotate instructions exist depending on program requirements. Rotate instructions are useful for
serial port programming applications where data can be
rotated from an internal register into the Carry bit from
where it can be examined and the necessary serial bit
set high or low. Another application where rotate data
operations are used is to implement multiplication and
division calculations.
Instruction Timing
Most instructions are implemented within one instruction cycle. The exceptions to this are branch, call, or table read instructions where two instruction cycles are
required. One instruction cycle is equal to 4 system
clock cycles, therefore in the case of an 8MHz system
oscillator, most instructions would be implemented
within 0.5ms and branch or call instructions would be implemented within 1ms. Although instructions which require one more cycle to implement are generally limited
to the JMP, CALL, RET, RETI and table read instructions, it is important to realize that any other instructions
which involve manipulation of the Program Counter Low
register or PCL will also take one more cycle to implement. As instructions which change the contents of the
PCL will imply a direct jump to that new address, one
more cycle will be required. Examples of such instructions would be ²CLR PCL² or ²MOV PCL, A². For the
case of skip instructions, it must be noted that if the result of the comparison involves a skip operation then
this will also take one more cycle, if no skip is involved
then only one cycle is required.
Branches and Control Transfer
Program branching takes the form of either jumps to
specified locations using the JMP instruction or to a subroutine using the CALL instruction. They differ in the
sense that in the case of a subroutine call, the program
must return to the instruction immediately when the subroutine has been carried out. This is done by placing a
return instruction RET in the subroutine which will cause
the program to jump back to the address right after the
CALL instruction. In the case of a JMP instruction, the
program simply jumps to the desired location. There is
no requirement to jump back to the original jumping off
point as in the case of the CALL instruction. One special
and extremely useful set of branch instructions are the
conditional branches. Here a decision is first made regarding the condition of a certain data memory or individual bits. Depending upon the conditions, the program
will continue with the next instruction or skip over it and
jump to the following instruction. These instructions are
the key to decision making and branching within the program perhaps determined by the condition of certain input switches or by the condition of internal data bits.
Moving and Transferring Data
The transfer of data within the microcontroller program
is one of the most frequently used operations. Making
use of three kinds of MOV instructions, data can be
transferred from registers to the Accumulator and
vice-versa as well as being able to move specific immediate data directly into the Accumulator. One of the most
important data transfer applications is to receive data
from the input ports and transfer data to the output ports.
Arithmetic Operations
The ability to perform certain arithmetic operations and
data manipulation is a necessary feature of most
microcontroller applications. Within the Holtek
microcontroller instruction set are a range of add and
Rev. 1.20
29
June 15, 2007
HT82A851R
Bit Operations
Other Operations
The ability to provide single bit operations on Data Memory is an extremely flexible feature of all Holtek
microcontrollers. This feature is especially useful for
output port bit programming where individual bits or port
pins can be directly set high or low using either the ²SET
[m].i² or ²CLR [m].i² instructions respectively. The feature removes the need for programmers to first read the
8-bit output port, manipulate the input data to ensure
that other bits are not changed and then output the port
with the correct new data. This read-modify-write process is taken care of automatically when these bit operation instructions are used.
In addition to the above functional instructions, a range
of other instructions also exist such as the ²HALT² instruction for Power-down operations and instructions to
control the operation of the Watchdog Timer for reliable
program operations under extreme electric or electromagnetic environments. For their relevant operations,
refer to the functional related sections.
Instruction Set Summary
The following table depicts a summary of the instruction
set categorised according to function and can be consulted as a basic instruction reference using the following listed conventions.
Table Read Operations
Table conventions:
Data storage is normally implemented by using registers. However, when working with large amounts of
fixed data, the volume involved often makes it inconvenient to store the fixed data in the Data Memory. To overcome this problem, Holtek microcontrollers allow an
area of Program Memory to be setup as a table where
data can be directly stored. A set of easy to use instructions provides the means by which this fixed data can be
referenced and retrieved from the Program Memory.
Mnemonic
x: Bits immediate data
m: Data Memory address
A: Accumulator
i: 0~7 number of bits
addr: Program memory address
Description
Cycles
Flag Affected
1
1Note
1
1
1Note
1
1
1Note
1
1Note
1Note
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
Z, C, AC, OV
C
1
1
1
1Note
1Note
1Note
1
1
1
1Note
1
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
1
1Note
1
1Note
Z
Z
Z
Z
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
Add Data Memory to ACC
Add ACC to Data Memory
Add immediate data to ACC
Add Data Memory to ACC with Carry
Add ACC to Data memory with Carry
Subtract immediate data from the ACC
Subtract Data Memory from ACC
Subtract Data Memory from ACC with result in Data Memory
Subtract Data Memory from ACC with Carry
Subtract Data Memory from ACC with Carry, result in Data Memory
Decimal adjust ACC for Addition with result in Data Memory
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
Logical AND Data Memory to ACC
Logical OR Data Memory to ACC
Logical XOR Data Memory to ACC
Logical AND ACC to Data Memory
Logical OR ACC to Data Memory
Logical XOR ACC to Data Memory
Logical AND immediate Data to ACC
Logical OR immediate Data to ACC
Logical XOR immediate Data to ACC
Complement Data Memory
Complement Data Memory with result in ACC
Increment & Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Rev. 1.20
Increment Data Memory with result in ACC
Increment Data Memory
Decrement Data Memory with result in ACC
Decrement Data Memory
30
June 15, 2007
HT82A851R
Mnemonic
Description
Cycles
Flag Affected
Rotate Data Memory right with result in ACC
Rotate Data Memory right
Rotate Data Memory right through Carry with result in ACC
Rotate Data Memory right through Carry
Rotate Data Memory left with result in ACC
Rotate Data Memory left
Rotate Data Memory left through Carry with result in ACC
Rotate Data Memory left through Carry
1
1Note
1
1Note
1
1Note
1
1Note
None
None
C
C
None
None
C
C
Move Data Memory to ACC
Move ACC to Data Memory
Move immediate data to ACC
1
1Note
1
None
None
None
Clear bit of Data Memory
Set bit of Data Memory
1Note
1Note
None
None
Jump unconditionally
Skip if Data Memory is zero
Skip if Data Memory is zero with data movement to ACC
Skip if bit i of Data Memory is zero
Skip if bit i of Data Memory is not zero
Skip if increment Data Memory is zero
Skip if decrement Data Memory is zero
Skip if increment Data Memory is zero with result in ACC
Skip if decrement Data Memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
2
1Note
1note
1Note
1Note
1Note
1Note
1Note
1Note
2
2
2
2
None
None
None
None
None
None
None
None
None
None
None
None
None
Read table (current page) to TBLH and Data Memory
Read table (last page) to TBLH and Data Memory
2Note
2Note
None
None
No operation
Clear Data Memory
Set Data Memory
Clear Watchdog Timer
Pre-clear Watchdog Timer
Pre-clear Watchdog Timer
Swap nibbles of Data Memory
Swap nibbles of Data Memory with result in ACC
Enter power down mode
1
1Note
1Note
1
1
1
1Note
1
1
None
None
None
TO, PDF
TO, PDF
TO, PDF
None
None
TO, PDF
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
Note: 1. For skip instructions, if the result of the comparison involves a skip then two cycles are required,
if no skip takes place only one cycle is required.
2. Any instruction which changes the contents of the PCL will also require 2 cycles for execution.
3. For the ²CLR WDT1² and ²CLR WDT2² instructions the TO and PDF flags may be affected by
the execution status. The TO and PDF flags are cleared after both ²CLR WDT1² and
²CLR WDT2² instructions are consecutively executed. Otherwise the TO and PDF flags
remain unchanged.
Rev. 1.20
31
June 15, 2007
HT82A851R
Instruction Definition
ADC A,[m]
Add Data Memory to ACC with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the Accumulator.
Operation
ACC ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADCM A,[m]
Add ACC to Data Memory with Carry
Description
The contents of the specified Data Memory, Accumulator and the carry flag are added. The
result is stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m] + C
Affected flag(s)
OV, Z, AC, C
ADD A,[m]
Add Data Memory to ACC
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
ADD A,x
Add immediate data to ACC
Description
The contents of the Accumulator and the specified immediate data are added. The result is
stored in the Accumulator.
Operation
ACC ¬ ACC + x
Affected flag(s)
OV, Z, AC, C
ADDM A,[m]
Add ACC to Data Memory
Description
The contents of the specified Data Memory and the Accumulator are added. The result is
stored in the specified Data Memory.
Operation
[m] ¬ ACC + [m]
Affected flag(s)
OV, Z, AC, C
AND A,[m]
Logical AND Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical AND operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² [m]
Affected flag(s)
Z
AND A,x
Logical AND immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical AND
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²AND² x
Affected flag(s)
Z
ANDM A,[m]
Logical AND ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical AND operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²AND² [m]
Affected flag(s)
Z
Rev. 1.20
32
June 15, 2007
HT82A851R
CALL addr
Subroutine call
Description
Unconditionally calls a subroutine at the specified address. The Program Counter then increments by 1 to obtain the address of the next instruction which is then pushed onto the
stack. The specified address is then loaded and the program continues execution from this
new address. As this instruction requires an additional operation, it is a two cycle instruction.
Operation
Stack ¬ Program Counter + 1
Program Counter ¬ addr
Affected flag(s)
None
CLR [m]
Clear Data Memory
Description
Each bit of the specified Data Memory is cleared to 0.
Operation
[m] ¬ 00H
Affected flag(s)
None
CLR [m].i
Clear bit of Data Memory
Description
Bit i of the specified Data Memory is cleared to 0.
Operation
[m].i ¬ 0
Affected flag(s)
None
CLR WDT
Clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT1
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT2 and must be executed alternately with CLR WDT2 to have effect. Repetitively executing this instruction without alternately executing CLR WDT2 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
CLR WDT2
Pre-clear Watchdog Timer
Description
The TO, PDF flags and the WDT are all cleared. Note that this instruction works in conjunction with CLR WDT1 and must be executed alternately with CLR WDT1 to have effect. Repetitively executing this instruction without alternately executing CLR WDT1 will have no
effect.
Operation
WDT cleared
TO ¬ 0
PDF ¬ 0
Affected flag(s)
TO, PDF
Rev. 1.20
33
June 15, 2007
HT82A851R
CPL [m]
Complement Data Memory
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa.
Operation
[m] ¬ [m]
Affected flag(s)
Z
CPLA [m]
Complement Data Memory with result in ACC
Description
Each bit of the specified Data Memory is logically complemented (1¢s complement). Bits
which previously contained a 1 are changed to 0 and vice versa. The complemented result
is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
Z
DAA [m]
Decimal-Adjust ACC for addition with result in Data Memory
Description
Convert the contents of the Accumulator value to a BCD ( Binary Coded Decimal) value resulting from the previous addition of two BCD variables. If the low nibble is greater than 9 or
if AC flag is set, then a value of 6 will be added to the low nibble. Otherwise the low nibble
remains unchanged. If the high nibble is greater than 9 or if the C flag is set, then a value of
6 will be added to the high nibble. Essentially, the decimal conversion is performed by adding 00H, 06H, 60H or 66H depending on the Accumulator and flag conditions. Only the C
flag may be affected by this instruction which indicates that if the original BCD sum is
greater than 100, it allows multiple precision decimal addition.
Operation
[m] ¬ ACC + 00H or
[m] ¬ ACC + 06H or
[m] ¬ ACC + 60H or
[m] ¬ ACC + 66H
Affected flag(s)
C
DEC [m]
Decrement Data Memory
Description
Data in the specified Data Memory is decremented by 1.
Operation
[m] ¬ [m] - 1
Affected flag(s)
Z
DECA [m]
Decrement Data Memory with result in ACC
Description
Data in the specified Data Memory is decremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] - 1
Affected flag(s)
Z
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock. The contents
of the Data Memory and registers are retained. The WDT and prescaler are cleared. The
power down flag PDF is set and the WDT time-out flag TO is cleared.
Operation
TO ¬ 0
PDF ¬ 1
Affected flag(s)
TO, PDF
Rev. 1.20
34
June 15, 2007
HT82A851R
INC [m]
Increment Data Memory
Description
Data in the specified Data Memory is incremented by 1.
Operation
[m] ¬ [m] + 1
Affected flag(s)
Z
INCA [m]
Increment Data Memory with result in ACC
Description
Data in the specified Data Memory is incremented by 1. The result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC ¬ [m] + 1
Affected flag(s)
Z
JMP addr
Jump unconditionally
Description
The contents of the Program Counter are replaced with the specified address. Program
execution then continues from this new address. As this requires the insertion of a dummy
instruction while the new address is loaded, it is a two cycle instruction.
Operation
Program Counter ¬ addr
Affected flag(s)
None
MOV A,[m]
Move Data Memory to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
None
MOV A,x
Move immediate data to ACC
Description
The immediate data specified is loaded into the Accumulator.
Operation
ACC ¬ x
Affected flag(s)
None
MOV [m],A
Move ACC to Data Memory
Description
The contents of the Accumulator are copied to the specified Data Memory.
Operation
[m] ¬ ACC
Affected flag(s)
None
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
No operation
Affected flag(s)
None
OR A,[m]
Logical OR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² [m]
Affected flag(s)
Z
Rev. 1.20
35
June 15, 2007
HT82A851R
OR A,x
Logical OR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical OR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²OR² x
Affected flag(s)
Z
ORM A,[m]
Logical OR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical OR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²OR² [m]
Affected flag(s)
Z
RET
Return from subroutine
Description
The Program Counter is restored from the stack. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
Affected flag(s)
None
RET A,x
Return from subroutine and load immediate data to ACC
Description
The Program Counter is restored from the stack and the Accumulator loaded with the
specified immediate data. Program execution continues at the restored address.
Operation
Program Counter ¬ Stack
ACC ¬ x
Affected flag(s)
None
RETI
Return from interrupt
Description
The Program Counter is restored from the stack and the interrupts are re-enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit (bit 0; register INTC). If an interrupt was pending when the RETI instruction is executed, the pending Interrupt routine
will be processed before returning to the main program.
Operation
Program Counter ¬ Stack
EMI ¬ 1
Affected flag(s)
None
RL [m]
Rotate Data Memory left
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ [m].7
Affected flag(s)
None
RLA [m]
Rotate Data Memory left with result in ACC
Description
The contents of the specified Data Memory are rotated left by 1 bit with bit 7 rotated into bit
0. The rotated result is stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ [m].7
Affected flag(s)
None
Rev. 1.20
36
June 15, 2007
HT82A851R
RLC [m]
Rotate Data Memory left through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7
replaces the Carry bit and the original carry flag is rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; (i = 0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RLCA [m]
Rotate Data Memory left through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated left by 1 bit. Bit 7 replaces
the Carry bit and the original carry flag is rotated into the bit 0. The rotated result is stored in
the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; (i = 0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
C
RR [m]
Rotate Data Memory right
Description
The contents of the specified Data Memory are rotated right by 1 bit with bit 0 rotated into
bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ [m].0
Affected flag(s)
None
RRA [m]
Rotate Data Memory right with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit with bit 0 rotated into bit 7. The rotated result is stored in the Accumulator and the contents of the Data
Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ [m].0
Affected flag(s)
None
RRC [m]
Rotate Data Memory right through Carry
Description
The contents of the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0
replaces the Carry bit and the original carry flag is rotated into bit 7.
Operation
[m].i ¬ [m].(i+1); (i = 0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
C
RRCA [m]
Rotate Data Memory right through Carry with result in ACC
Description
Data in the specified Data Memory and the carry flag are rotated right by 1 bit. Bit 0 replaces the Carry bit and the original carry flag is rotated into bit 7. The rotated result is
stored in the Accumulator and the contents of the Data Memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); (i = 0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
C
Rev. 1.20
37
June 15, 2007
HT82A851R
SBC A,[m]
Subtract Data Memory from ACC with Carry
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Accumulator. Note that if the result
of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or
zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SBCM A,[m]
Subtract Data Memory from ACC with Carry and result in Data Memory
Description
The contents of the specified Data Memory and the complement of the carry flag are subtracted from the Accumulator. The result is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is
positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m] - C
Affected flag(s)
OV, Z, AC, C
SDZ [m]
Skip if decrement Data Memory is 0
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0 the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] - 1
Skip if [m] = 0
Affected flag(s)
None
SDZA [m]
Skip if decrement Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first decremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0, the program proceeds with the following instruction.
Operation
ACC ¬ [m] - 1
Skip if ACC = 0
Affected flag(s)
None
SET [m]
Set Data Memory
Description
Each bit of the specified Data Memory is set to 1.
Operation
[m] ¬ FFH
Affected flag(s)
None
SET [m].i
Set bit of Data Memory
Description
Bit i of the specified Data Memory is set to 1.
Operation
[m].i ¬ 1
Affected flag(s)
None
Rev. 1.20
38
June 15, 2007
HT82A851R
SIZ [m]
Skip if increment Data Memory is 0
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. As this requires the insertion of a dummy instruction while
the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the program
proceeds with the following instruction.
Operation
[m] ¬ [m] + 1
Skip if [m] = 0
Affected flag(s)
None
SIZA [m]
Skip if increment Data Memory is zero with result in ACC
Description
The contents of the specified Data Memory are first incremented by 1. If the result is 0, the
following instruction is skipped. The result is stored in the Accumulator but the specified
Data Memory contents remain unchanged. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not
0 the program proceeds with the following instruction.
Operation
ACC ¬ [m] + 1
Skip if ACC = 0
Affected flag(s)
None
SNZ [m].i
Skip if bit i of Data Memory is not 0
Description
If bit i of the specified Data Memory is not 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is 0 the program proceeds with the following instruction.
Operation
Skip if [m].i ¹ 0
Affected flag(s)
None
SUB A,[m]
Subtract Data Memory from ACC
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
ACC ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUBM A,[m]
Subtract Data Memory from ACC with result in Data Memory
Description
The specified Data Memory is subtracted from the contents of the Accumulator. The result
is stored in the Data Memory. Note that if the result of subtraction is negative, the C flag will
be cleared to 0, otherwise if the result is positive or zero, the C flag will be set to 1.
Operation
[m] ¬ ACC - [m]
Affected flag(s)
OV, Z, AC, C
SUB A,x
Subtract immediate data from ACC
Description
The immediate data specified by the code is subtracted from the contents of the Accumulator. The result is stored in the Accumulator. Note that if the result of subtraction is negative, the C flag will be cleared to 0, otherwise if the result is positive or zero, the C flag will
be set to 1.
Operation
ACC ¬ ACC - x
Affected flag(s)
OV, Z, AC, C
Rev. 1.20
39
June 15, 2007
HT82A851R
SWAP [m]
Swap nibbles of Data Memory
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged.
Operation
[m].3~[m].0 « [m].7 ~ [m].4
Affected flag(s)
None
SWAPA [m]
Swap nibbles of Data Memory with result in ACC
Description
The low-order and high-order nibbles of the specified Data Memory are interchanged. The
result is stored in the Accumulator. The contents of the Data Memory remain unchanged.
Operation
ACC.3 ~ ACC.0 ¬ [m].7 ~ [m].4
ACC.7 ~ ACC.4 ¬ [m].3 ~ [m].0
Affected flag(s)
None
SZ [m]
Skip if Data Memory is 0
Description
If the contents of the specified Data Memory is 0, the following instruction is skipped. As
this requires the insertion of a dummy instruction while the next instruction is fetched, it is a
two cycle instruction. If the result is not 0 the program proceeds with the following instruction.
Operation
Skip if [m] = 0
Affected flag(s)
None
SZA [m]
Skip if Data Memory is 0 with data movement to ACC
Description
The contents of the specified Data Memory are copied to the Accumulator. If the value is
zero, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two cycle instruction. If the result is not 0 the
program proceeds with the following instruction.
Operation
ACC ¬ [m]
Skip if [m] = 0
Affected flag(s)
None
SZ [m].i
Skip if bit i of Data Memory is 0
Description
If bit i of the specified Data Memory is 0, the following instruction is skipped. As this requires the insertion of a dummy instruction while the next instruction is fetched, it is a two
cycle instruction. If the result is not 0, the program proceeds with the following instruction.
Operation
Skip if [m].i = 0
Affected flag(s)
None
TABRDC [m]
Read table (current page) to TBLH and Data Memory
Description
The low byte of the program code (current page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
TABRDL [m]
Read table (last page) to TBLH and Data Memory
Description
The low byte of the program code (last page) addressed by the table pointer (TBLP) is
moved to the specified Data Memory and the high byte moved to TBLH.
Operation
[m] ¬ program code (low byte)
TBLH ¬ program code (high byte)
Affected flag(s)
None
Rev. 1.20
40
June 15, 2007
HT82A851R
XOR A,[m]
Logical XOR Data Memory to ACC
Description
Data in the Accumulator and the specified Data Memory perform a bitwise logical XOR operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XORM A,[m]
Logical XOR ACC to Data Memory
Description
Data in the specified Data Memory and the Accumulator perform a bitwise logical XOR operation. The result is stored in the Data Memory.
Operation
[m] ¬ ACC ²XOR² [m]
Affected flag(s)
Z
XOR A,x
Logical XOR immediate data to ACC
Description
Data in the Accumulator and the specified immediate data perform a bitwise logical XOR
operation. The result is stored in the Accumulator.
Operation
ACC ¬ ACC ²XOR² x
Affected flag(s)
Z
Rev. 1.20
41
June 15, 2007
HT82A851R
Package Information
24-pin SSOP (209mil) Outline Dimensions
1 3
2 4
A
B
1 2
1
C
C '
G
H
D
E
Symbol
Rev. 1.20
a
F
Dimensions in mil
Min.
Nom.
Max.
A
291
¾
323
B
196
¾
220
C
9
¾
15
C¢
311
¾
345
D
65
¾
73
E
¾
26
¾
F
4
¾
10
G
22
¾
37
H
4
¾
8
a
0°
¾
8°
42
June 15, 2007
HT82A851R
Holtek Semiconductor Inc. (Headquarters)
No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan
Tel: 886-3-563-1999
Fax: 886-3-563-1189
http://www.holtek.com.tw
Holtek Semiconductor Inc. (Taipei Sales Office)
4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan
Tel: 886-2-2655-7070
Fax: 886-2-2655-7373
Fax: 886-2-2655-7383 (International sales hotline)
Holtek Semiconductor Inc. (Shanghai Sales Office)
7th Floor, Building 2, No.889, Yi Shan Rd., Shanghai, China 200233
Tel: 86-21-6485-5560
Fax: 86-21-6485-0313
http://www.holtek.com.cn
Holtek Semiconductor Inc. (Shenzhen Sales Office)
5/F, Unit A, Productivity Building, Cross of Science M 3rd Road and Gaoxin M 2nd Road, Science Park, Nanshan District,
Shenzhen, China 518057
Tel: 86-755-8616-9908, 86-755-8616-9308
Fax: 86-755-8616-9722
Holtek Semiconductor Inc. (Beijing Sales Office)
Suite 1721, Jinyu Tower, A129 West Xuan Wu Men Street, Xicheng District, Beijing, China 100031
Tel: 86-10-6641-0030, 86-10-6641-7751, 86-10-6641-7752
Fax: 86-10-6641-0125
Holtek Semiconductor Inc. (Chengdu Sales Office)
709, Building 3, Champagne Plaza, No.97 Dongda Street, Chengdu, Sichuan, China 610016
Tel: 86-28-6653-6590
Fax: 86-28-6653-6591
Holtek Semiconductor (USA), Inc. (North America Sales Office)
46729 Fremont Blvd., Fremont, CA 94538
Tel: 1-510-252-9880
Fax: 1-510-252-9885
http://www.holtek.com
Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used
solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable
without further modification, nor recommends the use of its products for application that may present a risk to human life
due to malfunction or otherwise. Holtek¢s products are not authorized for use as critical components in life support devices
or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information,
please visit our web site at http://www.holtek.com.tw.
Rev. 1.20
43
June 15, 2007