ETC HT99C411(28SDIP)

HT99C410/HT99C411
Cordless Phone Controller
Features
·
·
·
·
·
·
·
·
Provide mask type, OTP type and CERDIP
window type versions
Operating voltage: 2.4V~5.0V (mask type),
3.0V~5.0V (OTP type)
24 bidirectional I/O lines
One interrupt input
One 8-bit and one 16-bit programmable
timer/event counters with overflow interrupt
On-chip crystal and RC oscillator
Watchdog timer
4K´15 program memory ROM
·
·
·
·
·
·
·
·
·
160´8 data memory RAM
Halt function and wake-up feature reduce
power consumption
63 powerful instructions
Up to 1ms instruction cycle with 4MHz system clock at VDD=5V
All instructions in 1 or 2 machine cycles
15-bit table read instructions
4-level subroutine nesting
Bit manipulation instructions
Built-in 8-bit D/A converter
General Description
fast evaluation of private products during the
development stages.
The HT99C410 is an 8-bit high performance
RISC-like microcontroller which combines
HT48C50 8-bit microcontroller and 8-bit D/A
converter in one chip. It is specifically designed
for multiple I/O product applications. It also
provides UV-erasable CERDIP window type
version HT99C411C and OTP type version
HT99C411, both support designers in making
The device is particularly suitable for use in
products such as cordless phone controllers, mC
dialers, feature phone controllers and various
subsystem controllers. A halt feature is included to reduce power consumption.
Selection Table
Function
ROM
(Bits)
RAM
(Bits)
I/O
(Lines)
WDT
Timer/
Counter
DAC
(Bits)
HT99C410
HT99C411
HT99C411C
Mask
OTP
4K´15
CERDIP window
160´8
24
Ö
2
8
HT99C810
HT99C811
HT99C811C
Mask
OTP
8K´16
CERDIP window
224´8
48
Ö
2
8
Part No.
Type
1
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November 17, 1999
HT99C410/HT99C411
Block Diagram
S Y S C L K /4
T M R 0 C
S T A C K 0
S T A C K 1
P ro g ra m
R O M
In te rru p t
C ir c u it
S T A C K 2
S T A C K 3
P ro g ra m
C o u n te r
M P 0
M P 1
M
U
IN T C
X
T M R 0
X
T M R 1
1 6 - b it
S Y S C L K /4
M
T M R 1
T M R 1 C
In s tr u c tio n
R e g is te r
M
T M R 0
IN T
U
8 - b it
U
S Y S C L K /4
X
W D T S
D A T A
M e m o ry
W D T P r e s c a le r
M
W D T
U
X
R C O S C
S T A T U S
P C C
S h ifte r
P C
P B C
O S C 2
R E
V D
V S
A V D
A V S
O S C 1
S
S
A C C
P A C
P A
D
2
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P D 0 ~ P D 7
8 - b it R /2 R
D /A C o n v e rte r
P O R T B
P B
D
S
P O R T D
P D
A L U
T im in g
G e n e ra to r
P D C
M U X
In s tr u c tio n
D e c o d e r
P O R T A
A O U T
P B 0 ~ P B 7
P A 0 ~ P A 7
November 17, 1999
HT99C410/HT99C411
Pin Assignment
P B 5
1
2 8
P B 4
2
2 7
P A 3
3
2 6
P A 2
4
2 5
P B 6
P B 5
P B 7
P B 4
P A 4
2
2 7
P A 3
P A 5
3
2 6
P A 2
P A 6
4
2 5
P A 1
P A 7
5
2 4
P A 0
O S C 2
6
2 3
P B 1
O S C 1
7
2 2
P B 0
V D D
8
2 1
V S S
9
2 0
1
2 8
P A 3
1
2 8
P B 7
P A 2
2
2 7
P A 4
P A 1
3
2 6
P A 5
P A 0
4
2 5
P A 6
P B 3
5
2 4
P A 7
P B 2
6
2 3
O S C 2
P B 1
7
O S C 1
2 2
P B 0
8
V D D
2 1
P D 6
P D 5
9
2 0
T M R 1
P D 4
1 0
1 9
1 1
1 8
P D 3
P D 2
1 2
1 7
1 3
1 6
1 4
1 5
P A 1
5
2 4
P A 0
6
2 3
P B 1
7
2 2
P B 0
8
2 1
V S S
9
2 0
IN T
1 0
1 9
R E S
IN T
1 0
1 9
R E S
T M R 0
N C
1 1
1 8
1 8
1 6
N C
1 7
1 3
P D 0
1 2
P D 2
P D 1
N C
1 7
T M R 0
N C
1 1
1 2
P D 2
P D 1
1 5
N C
1 6
1 4
A O U T
1 3
1 4
1 5
N C
H T 9 9 C 4 1 0 /H T 9 9 C 4 1 1
2 8 S D IP
P B 5
1
4 0
P B 4
2
3 9
P A 3
3
3 8
P A 2
4
3 7
P A 1
5
3 6
P A 0
6
3 5
P B 3
7
3 4
P B 2
8
3 3
9
3 2
1 0
3 1
1 1
3 0
1 2
2 9
1 3
2 8
1 4
2 7
1 5
2 6
1 6
2 5
IN T
T M R 0
N C
1 7
2 4
1 8
2 3
N C
1 9
2 2
2 0
2 1
P B 1
P B 0
P D 7
P D 6
P D 5
P D 4
V S S
A V S S
H T 9 9 C 4 1 0
4 0
* T h e a n
* T h e a n
* T h e T M
/H T 9
D IP
a lo g
a lo g
R 0
P D 0
A O U T
H T 9 9 C 4 1 1 C
2 8 C E R D IP w in d o w
P B 5
1
4 8
P B 6
P B 4
2
4 7
P B 7
N C
3
4 6
N C
N C
4
4 5
N C
P B 6
P A 3
5
4 4
P A 4
P B 7
P A 2
4 3
P A 5
P A 4
6
P A 1
4 2
P A 6
P A 5
7
P A 0
4 1
P A 7
P A 6
8
P B 3
4 0
O S C 2
P A 7
9
P B 2
3 9
O S C 1
O S C 2
1 0
P B 1
3 8
N C
O S C 1
1 1
P B 0
3 7
N C
V D D
1 2
P D 7
1 3
3 6
N C
P D 6
3 5
V D D
R E S
1 4
P D 5
3 4
A V D D
T M R 1
1 5
P D 4
3 3
R E S
P D 3
1 6
V S S
3 2
T M R 1
P D 2
1 7
A V S S
3 1
P D 3
P D 1
1 8
IN T
3 0
P D 2
P D 0
1 9
T M R 0
2 0
2 9
N C
A O U T
N C
2 1
2 8
N C
N C
N C
2 2
2 7
P D 1
N C
N C
2 3
2 6
P D 0
N C
N C
2 4
2 5
A O U T
A V D D
9 C 4 1 1
H T 9 9 C 4 1 0 /H T 9 9 C
4 8 S S O P
V D D ( A V D D ) p a d a n d d ig ita l V D D
V S S ( A V S S ) p a d a n d d ig ita l V S S p
a n d T M R 1 p a d s m u s t b e b o n d e d to
3
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P A 4
P B 6
V S S
IN T
T M R 0
P A 5
P A 6
P A 7
O S C 2
O S C 1
V D D
R E S
P D 1
P D 0
A O U T
H T 9 9 C 4 1 0 /H T 9 9 C 4 1 1
2 8 S O P
4 1 1
p a d m u s t b e b o n d e d to V D D p in .
a d m u s t b e b o n d e d to V S S p in .
V D D o r V S S ( if n o t u s e d ) .
November 17, 1999
HT99C410/HT99C411
Pad Assignment
HT99C410
P D 7
6
P D 6
7
P D 5
8
P D 4
9
P A 6
5
P A 5
P B 0
P A 4
4
P B 7
P B 1
P B 6
3
P B 5
P B 2
P B 4
2
P A 3
P B 3
P A 2
1
P A 1
P A 0
3 5
3 4
3 3
3 2
3 1
3 0
2 9
2 8
2 7
2 6
P A 7
2 5
O S C 2
2 4
V S S
(0 ,0 ).
1 0
A V S S
2 3
O S C 1
2 2
V D D
2 1
A V D D
2 0
R E S
1 9
T M R 1
1 8
P D 3
1 7
P D 2
1 1
T M R 0
1 5
1 6
P D 1
IN T
1 4
P D 0
1 3
A O U T
1 2
2
Chip size: 2750 ´ 3750 (mm)
* The IC substrate should be connected to VSS in the PCB layout artwork.
HT99C411
P B 5
P B 6
P B 7
3 1
3 0
2 9
2 8
2 7
2 6
P A 7
P B 4
3 2
P A 6
P A 3
3 3
P A 5
P A 2
3 4
P A 4
P A 1
3 5
2 5
P A 0
1
2 4
P B 3
2
P B 2
3
P B 1
4
2 3
P B 0
5
P D 7
6
2 2
2 1
O S C 2
O S C 1
V D D
A V D D
P D 6
(0 ,0 ).
7
V S S
1 0
1 1
1 3
1 4
1 5
R E S
1 9
T M R 1
1 8
P D 3
1 7
P D 2
1 6
P D 1
A V S S
1 2
P D 0
9
A O U T
P D 4
T M R 0
8
IN T
P D 5
2 0
2
Chip size: 2810 ´ 3480 (mm)
* The IC substrate should be connected to VSS in the PCB layout artwork.
4
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HT99C410/HT99C411
Pad Coordinates
HT99C411
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Unit: mm
X
-1173.40
-1173.40
-1173.40
-1173.40
-1173.40
-1173.40
-1173.40
-1173.40
-1173.40
-1205.30
-1164.30
-1139.70
-957.20
551.30
783.10
1118.70
1121.20
1121.20
Y
1494.90
1263.00
903.60
712.60
352.60
135.90
-113.90
-356.90
-606.70
-1141.10
-1302.10
-1589.00
-1589.00
-1540.00
-1563.50
-1608.40
-1018.20
-835.70
Pad No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
X
1121.20
1121.20
1130.40
1178.00
1204.90
1173.50
1134.60
814.60
627.20
435.30
245.80
58.10
-133.50
-321.20
-510.70
-702.60
-890.00
HT99C411
Pad No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Y
-646.90
-462.10
177.40
332.40
493.30
1104.00
1436.80
1606.80
1606.80
1606.80
1572.90
1572.90
1572.90
1572.90
1606.80
1606.80
1606.80
Unit: mm
X
-1212.30
-1163.60
-1163.60
-1163.60
-1163.60
-1163.60
-1163.60
-1163.60
-1163.60
-1176.50
-1021.50
-866.50
-696.50
747.55
968.65
1171.80
1175.00
1175.00
Y
1124.95
933.35
752.40
551.90
370.95
170.15
-765.40
-965.90
-1146.85
-1464.95
-1465.00
-1464.85
-1465.00
-1459.80
-1460.00
-1460.00
-1023.15
-868.15
Pad No.
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
5
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X
1148.75
1162.85
1186.35
1215.00
1184.30
1216.00
899.70
709.55
547.10
360.00
127.45
-53.45
-254.85
-435.75
-668.30
-855.40
-1017.85
Y
-696.90
-30.45
221.50
376.50
610.40
1119.60
1300.70
1432.25
1432.25
1432.25
1469.55
1469.55
1469.55
1469.55
1437.25
1437.25
1437.25
November 17, 1999
HT99C410/HT99C411
Pad Description
HT99C410
Pad No. Pad Name I/O
Mask
Option
Description
Bidirectional 8-bit Input/Output port. Each bit can
be configured as a wake-up input by mask option.
Software instructions determine the CMOS output
or schmitt trigger input with or without pull high resistor (mask option).
1
35~33
28~25
PA0~PA7
I/O
Wake-up
Pull-high
or None
5~2
32~29
PB0~PB7
I/O
¾
Bidirectional 8-bit Input/Output port
Software instructions determine the NMOS open
drain output or schmitt trigger input.
10
11
VSS
AVSS
¾
¾
Negative power supply, GND
Analog negative power supply, AGND
12
INT
I
¾
External interrupt schmitt trigger input with pull
high resistor. Edge triggered activated during
high to low transition.
13
TMR0
I
¾
Schmitt trigger input for timer/event counter 0
19
TMR1
I
¾
Schmitt trigger input for timer/event counter 1
14
AOUT
O
¾
The D/A converter output can be programmed by
D/A controlled register. The register has a total of
eight digits from MSB to LSB, and it offers 8-bit
resolution for the D/A converter and one LSB is
1/256 VDD.
20
RES
I
¾
Schmitt trigger reset input, active low
22
21
VDD
AVDD
¾
¾
Positive power supply, VDD
Analog positive power supply, AVDD
9~6
15~18
PD7~PD4
PD0~PD3
Bidirectional 8-bit Input/Output port.
Pull-high
Software instructions determine the CMOS outI/O
or None
put or schmitt trigger input with or without pull
(mask type only)
high resistor (mask option).
23
24
OSC1
OSC2
I
O
Crystal
or RC
OSC1, OSC2 are connected to an RC network or a
crystal (determined by mask option) for the internal system clock. In the case of RC operation,
OSC2 is the output terminal for 1/4 system clock.
6
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HT99C410/HT99C411
Absolute Maximum Ratings
Supply Voltage..............................-0.3V to 5.5V
Storage Temperature.................-50°C to 125°C
Input Voltage .................VSS-0.3V to VDD+0.3V
Operating Temperature ..............-25°C to 70°C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged
exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol
Parameter
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
2.4
¾
5.0
V
¾
3.0
¾
5.0
V
No load,
fSYS=4MHz
¾
1
2
mA
¾
2.5
5
mA
No load,
fSYS=2MHz
¾
0.75
1.5
mA
¾
1.5
5
mA
No load,
system halt
¾
¾
5
mA
¾
¾
20
mA
No load,
system halt
¾
¾
1
mA
¾
¾
2
mA
VDD
Conditions
VDD(mask) Operating Voltage
¾
VDD(OTP)
¾
3V
IDD1
Operating Current
(Crystal OSC)
IDD2
Operating Current
(RC OSC)
ISTB1
Standby Current
(WDT Enabled)
3V
ISTB2
Standby Current
(WDT Disabled)
3V
VIL
Input Low Voltage for I/O
Ports
3V
¾
0
¾
0.9
V
5V
¾
0
¾
1.5
V
VIH
Input High Voltage for I/O
Ports
3V
¾
2.1
¾
3
V
5V
¾
3.5
¾
5
V
VIL1
Input Low Voltage
(RES, TMR0, TMR1, INT)
3V
¾
0
¾
0.7
V
5V
¾
0
¾
1.3
V
VIH1
Input High Voltage
(RES, TMR0, TMR1, INT)
3V
¾
2.3
¾
3
V
5V
¾
3.8
¾
5
V
IOL
I/O Port Sink Current
3V
VOL=0.3V
1.5
2.5
¾
mA
5V
VOL=0.5V
¾
6
¾
mA
IOH
I/O Port Source Current
3V
VOH=2.7V
-1
-1.5
¾
mA
5V
VOH=4.5V
¾
-3
¾
mA
5V
3V
5V
5V
5V
7
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HT99C410/HT99C411
Symbol
Parameter
Test Conditions
VDD
Conditions
Min.
Typ.
Max.
Unit
RPH
Pull-high Resistance of
I/O Ports and INT
3V
¾
40
60
80
kW
5V
¾
10
30
50
kW
VDAC
DAC Output Level
¾
¾
AVSS
¾
AVDD
V
IDAC
DAC Drive Current
5V
¾
50
¾
mA
VOH=0.9VDD
A.C. Characteristics
Symbol
fSYS1
Parameter
System Clock
(Crystal OSC)
Ta=25°C
Test Conditions
Min.
Typ.
Max.
Unit
¾
400
¾
4000
kHz
5V
¾
400
¾
4000
kHz
3V
¾
400
¾
2000
kHz
5V
¾
400
¾
3000
kHz
3V
¾
0
¾
4000
kHz
5V
¾
0
¾
4000
kHz
3V
¾
45
90
180
ms
5V
¾
35
65
130
ms
12
23
45
ms
9
17
35
ms
¾
1024
¾
tSYS
1
¾
¾
ms
¾
1024
¾
tSYS
1
¾
¾
ms
VDD
Conditions
3V
fSYS2
System Clock
(RC OSC)
fTIMER
Timer I/P Frequency
(TMR)
tWDTOSC
Watchdog Oscillator
tWDT1
Watchdog Time-out Period
(RC)
tWDT2
Watchdog Time-out Period
(System Clock)
¾
tRES
External Reset Low Pulse
Width
¾
tXST
System Start-up Timer
Period
¾
tINT
Interrupt Pulse Width
¾
3V
5V
Without WDT
prescaler
Without WDT
prescaler
¾
Power-up or
wake-up from
halt
¾
Note: tSYS=1/fSYS
For other important system architecture and function description, refer to HT48CX0
data sheet.
8
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November 17, 1999
HT99C410/HT99C411
Functional Description
The HT99C410/HT99C411 general I/O PROTC
is replaced by D/A converter register to control
the D/A output value and shows in below:
D/A converter description
The HT99C410/HT99C411 built-in 8-bit D/A
converter is one of the simple designed methods
of the D/A converter. The R/2R lattice method is
used in HT99C410/HT99C411 which offers
8-bit resolution.
PORTC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
(MSB)
Determine
D/A values
PC0
(LSB)
1/4
AVDD
1/2
AVDD
1/8
AVDD
1/16
AVDD
1/32
AVDD
1/64
AVDD
1/128
AVDD
1/256
AVDD
* D/A converter has isolated power line layout itself, in addition, AVDD and AVSS pads are included.
D/A converter circuit
D a ta B u s
Q
D
W r ite C o n tr o l R e g is te r
C K
Q
A V D D
S
C h ip R e s e t
R e a d C o n tr o l R e g is te r
W r ite I/O
P C 0 ~ P C 7
Q
D
C K
Q
S
A V S S
M
R e a d I/O
2 R
A V S S
2 R
P C 0
(D 0 )
2 R
P C 1
(D 1 )
X
R
R
R
U
2 R
P C 2
(D 2 )
R
R
2 R
2 R
P C 3
(D 3 )
P C 4
(D 4 )
R
2 R
P C 5
(D 5 )
R
2 R
P C 6
(D 6 )
A O U T
2 R
P C 7
(D 7 )
R = 1 0 k W
9
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HT99C410/HT99C411
The conditional skip is activated by instruction.
Once the condition is met, the next instruction,
fetched during the current instruction execution, is discarded and a dummy cycle replaces it
to get the proper instruction. Otherwise proceed with the next instruction.
Execution flow
The system clock for the HT99C410/HT99C411
is derived from either a crystal or an RC oscillator. The system clock is internally divided into
four non-overlapping clocks. One instruction
cycle consists of four system clock cycles.
Instruction fetching and execution are
pipelined in such a way that a fetch takes one
instruction cycle while decoding and execution
takes the next instruction cycle. However, the
pipelining scheme causes each instruction to effectively execute in one cycle. If an instruction
changes the program counter, two cycles are required to complete the instruction.
The lower byte of the program counter (PCL) is
a readable and writeable register (06H).
Moving data into the PCL performs a short
jump. The destination will be within 256 locations.
Program counter - PC
The program memory is used to store the program instructions which are to be executed. It
also contains data, table, and interrupt entries,
and is organized into 4096 ´ 15 bits, addressed
by the program counter and table pointer.
When a control transfer takes place, an additional
dummy cycle is required.
Program memory - ROM
The 12-bit program counter (PC) controls the
sequence in which the instructions stored in
program ROM are executed and its contents
specify a maximum of 4096 addresses.
After accessing a program memory word to
fetch an instruction code, the contents of the
program counter are incremented by one. The
program counter then points to the memory
word containing the next instruction code.
Certain locations in the program memory are
reserved for pecial usage:
· Location 000H
This area is reserved for the initialization
program. After chip reset, the program always begins execution at location 000H.
· Location 004H
This area is reserved for the external interrupt service program. If the INT input pin is
activated, and the interrupt is enabled and
the stack is not full, the program begins execution at location 004H.
When executing a jump instruction, conditional
skip execution, loading PCL register, subroutine call, initial reset, internal interrupt, external interrupt or return from subroutine, the PC
manipulates the program transfer by loading
the address corresponding to each instruction.
S y s te m
C lo c k
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
T 1
T 2
T 3
T 4
O S C 2 ( R C o n ly )
( N M O S o p e n d r a in o u tp u t)
P C
P C
P C + 1
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
P C + 2
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution flow
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HT99C410/HT99C411
· Location 008H
0 0 0 H
This area is reserved for the timer/event
counter 0 interrupt service program. If timer
interrupt results from a timer/event counter 0
overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at location 008H.
E x te r n a l in te r r u p t s u b r o u tin e
0 0 8 H
T im e r /e v e n t c o u n te r 0 in te r r u p t s u b r o u tin e
0 0 C H
· Location 00CH
T im e r /e v e n t c o u n te r 1 in te r r u p t s u b r o u tin e
n 0 0 H
This area is reserved for the timer/event
counter 1 interrupt service program. If timer
interrupt results from a timer/event counter 1
overflow, and if the interrupt is enabled and
the stack is not full, the program begins execution at location 00CH.
· Table location
Any location in the ROM space can be used as
look-up tables. The instructions TABRDC [m]
(the current page, 1 page=256 words) and
TABRDL [m] (the last page) transfer the contents of the lower-order byte to the specified
data memory, and the higher-order byte to
TBLH (08H). Only the destination of the
lower-order byte in the table is well-defined,
the other bits of the table word are transferred to the lower portion of TBLH, the remaining one bit is read as 0. The Table
Higher-order byte register (TBLH) is read
Mode
D e v ic e in itia liz a tio n p r o g r a m
0 0 4 H
P ro g ra m
R O M
L o o k - u p ta b le ( 2 5 6 w o r d s )
n F F H
L o o k - u p ta b le ( 2 5 6 w o r d s )
F F F H
1 5 b its
N o te : n ra n g e s fro m
0 to F
Program memory
only. The TBLH is read only and cannot be restored. If the main routine and the ISR (Interrupt Service Routine) both employ the table
read instruction, the contents of the TBLH in
the main routine are likely to be changed by
the table read instruction used in the ISR. Errors can occur. In other words, simultaneously using the table read instruction in
the main routine and the ISR should be
Program Counter
*11
*10 *9
*8
*7
*6
*5
*4
*3
*2
*1
*0
Initial reset
0
0
0
0
0
0
0
0
0
0
0
0
External interrupt
0
0
0
0
0
0
0
0
0
1
0
0
Timer/event counter 0 overflow
0
0
0
0
0
0
0
0
1
0
0
0
Timer/event counter 1 overflow
0
0
0
0
0
0
0
0
1
1
0
0
Skip
PC+2
Loading PCL
*11
*10
*9
*8
@7
@6
@5
@4
@3
@2
@1
@0
Jump, call branch
#11 #10
#9
#8
#7
#6
#5
#4
#3
#2
#1
#0
Return from subroutine
S11 S10
S9
S8
S7
S6
S5
S4
S3
S2
S1
S0
Program counter
Note: *11~*0: Program counter bits
S11~S0: Stack register bits
#11~#0: Instruction code bits
@7~@0: PCL bits
11
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HT99C410/HT99C411
similar case, if the stack is full and a "CALL" is
subsequently executed, stack overflow occurs and
the first entry will be lost (only the most recent
four return addresses are stored).
avoided. However, if the table read instruction has to be applied in both the main routine
and the ISR, the interrupt(s) is supposed to be
disabled prior to the table read instruction,
and will not be enabled until the TBLH has
been backed-up. The table pointer (TBLP) is a
read/write register (07H), which indicates the
table location. Before accessing the table, the
location must be placed in TBLP. All table related instructions need 2 cycles to complete the
operation. These areas may function as normal
program memory depending upon the requirements.
Data memory - RAM
The data memory is designed with 184 ´ 8 bits.
The data memory is divided into two functional
groups: special function registers and general
purpose data memory (160´8). Most of them are
read/write, but some are read only.
The special function registers include the indirect
addressing register 0 (00H), the memory pointer
register 0 (MP0;01H), the indirect addressing
register 1 (02H), the memory pointer register 1
(MP1;03H), the accumulator (ACC;05H), the program counter lower-byte register (PCL;06H), the
table pointer (TBLP;07H), the table higher-order
byte register (TBLH;08H), the watchdog timer
option setting register (WDTS;09H), the status
register (STATUS;0AH), the interrupt control
register (INTC;0BH), the timer/event counter 0
higher-order byte register (TMR0H;0CH), the
timer/event counter 0 lower-order byte register
(TMR0L;0DH), the timer/event counter 0 control
register (TMR0C;0EH), the timer/event counter 1
(TMR1;10H), the timer/event counter 1 control
register (TMR1C;11H), the I/O registers (PA;12H,
PB;14H, PD;18H) and the I/O control registers
(PAC;13H, PBC;15H, PDC;19H). The remaining
space before the 60H is reserved for future expansion usage and reading these locations will get a
"00H" value. The general purpose data memory,
addressed from 60H to FFH, is used for data
and control information under instruction command.
Stack register - STACK
This is a special part of the memory which is
used to save the contents of the program counter (PC) only. The stack is organized into 4 levels and is neither part of the data nor part of the
program space, and is neither readable nor
writeable. The activated level of the stack register is indexed by the stack pointer (SP) and is
neither readable nor writeable. At a subroutine
call or interrupt acknowledgment, the contents
of the program counter are pushed onto the
stack. At the end of a subroutine or an interrupt
routine, as signaled by a return instruction
(RET or RETI), the program counter is restored
to its previous value from the stack. After a chip
reset, the SP will point to the top of the stack.
If the stack is full and a non-masked interrupt
takes place, the interrupt request flag will be recorded but acknowledging will be inhibited.
When the stack pointer is decremented (by RET
or RETI), the interrupt will be serviced. This feature prevents stack overflow allowing the programmer to use the structure more easily. In a
Instruction(s)
Table Location
*11
*10
*9
*8
*7
*6
*5
*4
*3
*2
*1
*0
TABRDC [m]
P11
P10
P9
P8
@7
@6
@5
@4
@3
@2
@1
@0
TABRDL [m]
1
1
1
1
@7
@6
@5
@4
@3
@2
@1
@0
Table location
Note: *11~*0: Table location bits
P11~P8: Current program counter bits
@7~@0: Table pointer bits
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HT99C410/HT99C411
0 0 H
0 1 H
0 2 H
0 3 H
0 4 H
0 5 H
0 6 H
0 7 H
0 8 H
0 9 H
0 A H
0 B H
0 C H
0 D H
0 E H
0 F H
1 0 H
1 1 H
1 2 H
1 3 H
1 4 H
1 5 H
1 6 H
1 7 H
1 8 H
1 9 H
1 A H
1 B H
1 C H
1 D H
1 E H
1 F H
2 0 H
In d ir e c t A d d r e s s
M P
In d ir e c t A d d r e s s
M P
in g R e g is te r 1
1
A C C
P C L
T B L P
T B L H
W D T S
S T A T U S
IN T C
T M R 0 H
T M R 0 L
T M R 0 C
T M R
T M R 1
P A
P A C
P B
P B C
D /A O u tp u t
D /A C o n tro l
P D
P D C
MP1 (03H) respectively. Reading location 00H
or 02H indirectly will return the result 00H.
Writing indirectly results in no operation.
in g R e g is te r 0
0
The function of data movement between two indirect addressing registers, is not supported.
The memory pointer registers, MP0 and MP1,
are 8-bit registers which can be used to access
the data memory by combining corresponding
indirect addressing registers.
S p e c ia l P u r p o s e
D A T A M E M O R Y
Accumulator
The accumulator closely relates to the ALU operations. It is also mapped to location 05H of
the data memory and is capable of carrying out
immediate data operations. The data movement between these two data memories has to
pass through the accumulator.
1
C
R e g is te r
R e g is te r
Arithmetic and logic unit - ALU
This circuit performs 8-bit arithmetic and logic operations. The ALU provides the following functions:
· Arithmetic operations (ADD, ADC, SUB,
SBC, DAA)
: U n u s e d
· Logic operations (AND, OR, XOR, CPL)
· Rotation (RL, RR, RLC, RRC)
R e a d a s "0 0 "
· Increment and Decrement (INC, DEC)
· Branch decision (SZ, SNZ, SIZ, SDZ ....)
6 0 H
G e n e ra l P u rp o s e
D A T A M E M O R Y
(1 6 0 B y te s )
F F H
The ALU not only saves the results of a data operation but also changes the contents of the status register.
RAM mapping
Status register - STATUS
All data memory areas can execute arithmetic,
logic, increment, decrement and rotate operations directly. Except for some dedicated bits,
each bit in the data memory can be set and reset by the SET [m].i and CLR [m].i instructions,
respectively. They are also indirectly accessible
through Memory pointer registers (MP0;01H,
MP1;03H).
This 8-bit status register (0AH) contains the
zero flag (Z), carry flag (C), auxiliary carry flag
(AC), overflow flag (OV), power down flag (PD)
and watchdog time-out flag (TO). The status
register not only records the status information
but also controls the operation sequence.
With the exception of the TO and PD flags, bits
in the status register can be altered by instructions like most other registers. Any data written into the status register will not change the
TO or PD flags. It should be noted that operations related to the status register may give different results from those intended. The TO and
PD flags can only be changed by system power
Indirect addressing register
Location 00H and 02H are indirect addressing
registers that are not physically implemented.
Any read/write operation of [00H] and [02H] access data memory pointed to by MP0 (01H) and
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HT99C410/HT99C411
EMI bit and the corresponding bit of the INTC
may be set to permit interrupt nesting. If the
stack is full, the interrupt request will not be acknowledged, even if the related interrupt is enabled, until the SP is decremented. If immediate
service is desired, the stack must be prevented
from becoming full.
up, watchdog timer overflow, executing the
HALT instruction and clearing the Watchdog
Timer.
The Z, OV, AC and C flags generally reflect the
status of the latest operations.
On entering the interrupt sequence or executing a subroutine call, the status register will
not be automatically pushed onto the stack. If
the contents of the status are important and the
subroutine can corrupt the status register, precautions must be taken to save it properly.
All these kinds of interrupt have a wake-up capability. As an interrupt is serviced, a control
transfer occurs by pushing the program counter
onto the stack, followed by a branch to a subroutine at the specified location in the program
memory. Only the contents of the program
counter is pushed onto the stack. If the contents
of the register and Status register (STATUS)
are altered by the interrupt service program
which corrupt the desired control sequence, the
contents should be saved in advance.
Interrupt
The HT99C410/HT99C411 provides an external interrupt and internal timer/event counter
interrupts. The Interrupt Control register
(INTC;0BH) contains the interrupt control bits
to set the enable/disable and the interrupt request flags.
External interrupt is triggered by a high to low
transition of INT and the related interrupt request flag (EIF; bit 4 of INTC) will be set. When
the interrupt is enabled, and the stack is not
full and the external interrupt is active, a subroutine call to location 04H will occur. The interrupt request flag (EIF) and EMI bits will be
cleared to disable other interrupts.
Once an interrupt subroutine is serviced, all
other interrupts will be blocked (by clearing the
EMI bit). This scheme may prevent any further
interrupt nesting. Other interrupt requests may
occur during this interval but only the interrupt
request flag is recorded. If a certain interrupt
needs servicing within the service routine, the
Labels
Bits
Function
C
0
C is set if the operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation; otherwise C is cleared. C
is also affected by a rotate through carry instruction.
AC
1
AC is set if the operation results in a carry out of the low nibbles in addition or a
borrow does not take place from the high nibble into the low nibble in a subtraction; otherwise AC is cleared.
Z
2
Z is set if the result of an arithmetic or logic operation is zero; otherwise Z is
cleared.
OV
3
OV is set if the operation results in a carry into the highest-order bit but not a
carry out of the highest-order bit, or vice versa; otherwise OV is cleared.
PD
4
PD is cleared when either a system power-up or executing the CLR WDT instruction. PD is set by executing the HALT instruction.
TO
5
TO is cleared by a system power-up or executing the CLR WDT or HALT instruction. TO is set by a WDT time-out.
¾
6
Undefined, read as "0"
¾
7
Undefined, read as "0"
STATUS register
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HT99C410/HT99C411
abled. In case of simultaneous requests the following table shows the priority that is applied.
These can be masked by resetting the EMI bit.
The internal timer/event counter 0 interrupt is
initialized by setting the timer/event counter 0
interrupt request flag (T0F; bit 5 of INTC), which
is normally caused by a timer/event counter 0
overflow. When the interrupt is enabled, and the
stack is not full and the T0F bit is set, a subroutine call to location 08H will occur. The related interrupt request flag (T0F) will be reset and the
EMI bit cleared to disable further interrupts.
No. Interrupt Source Priority Vector
The timer/event counter 1 interrupt is operated
in the same manner as the timer/event counter
0. The related interrupt control bits ET1I and
T1F of timer/event counter 1 are bit 3 and bit 6
of the INTC respectively.
Interrupts occurring in the interval between
the rising edges of two consecutive T2 pulses,
will be serviced on the latter of the two T2
pulses, if the corresponding interrupts are en-
INTC
(0BH)
External interrupt
1
04H
b
Timer/event
counter 0 overflow
2
08H
c
Timer/event
counter 1 overflow
3
0CH
The timer/event counter 0/1 interrupt request
flag (T0F/T1F), External interrupt request flag
(EIF), Enable timer/event counter 0/1 bit
(ET0I/ET1I), Enable external interrupt bit
(EEI) and Enable master interrupt bit (EMI)
constitute an interrupt control register (INTC)
which is located at 0BH in the data memory.
EMI, EEI, ET0I, ET1I are used to control the
enabling/disabling of interrupts. These bits
prevent the requested interrupt from being serviced. Once the interrupt request flags (T0F,
T1F, EIF) are set, they will remain in the INTC
register until the interrupts are serviced or
cleared by a software instruction.
During the execution of an interrupt subroutine,
other interrupt acknowledgments are held until
the RETI instruction is executed or the EMI bit
and the related interrupt control bit are set to 1
(if the stack is not full). To return from the interrupt subroutine, the RET or RETI instruction
may be invoked. RETI will set the EMI bit to enable an interrupt service, but RET will not.
Register
a
Bit No.
Label
Function
0
EMI
Controls the master (global) interrupt
(1=enabled; 0=disabled)
1
EEI
Controls the external interrupt
(1=enabled; 0=disabled)
2
ET0I
Controls the timer/event counter 0 interrupt
(1=enabled; 0=disabled)
3
ET1I
Controls the timer/event counter 1 interrupt
(1=enabled; 0=disabled)
4
EIF
External interrupt request flag
(1=active; 0=inactive)
5
T0F
Internal timer/event counter 0 request flag
(1=active; 0=inactive)
6
T1F
Internal timer/event counter 1 request flag
(1=active; 0=inactive)
7
¾
Unused bit, read as "0"
INTC register
15
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HT99C410/HT99C411
of a crystal, a resonator can also be connected
between OSC1 and OSC2 to get a frequency reference, but two external capacitors in OSC1
and OSC2 are required.
It is suggested that a program does not use the
"CALL" subroutine within the interrupt subroutine. Because interrupts often occur in an unpredictable manner or need to be serviced
immediately in some applications, if only one
stack is left and enabling the interrupt is not well
controlled, once the CALL subroutine operates in
the interrupt subroutine, it will damage the original
control sequence.
The WDT oscillator is a free running on-chip
RC oscillator, and no external components are
required. Even if the system enters the power
down mode, the system clock is stopped, but the
WDT oscillator still works with a period of approximately 78 ms. The WDT oscillator can be
disabled by mask option to conserve power.
Oscillator configuration
There are two oscillator circuits in the
HT99C410/HT99C411. Both are designed for
system clocks: the RC oscillator and the crystal
oscillator, which are determined by mask options. No matter what oscillator type is selected, the signal provides the system clock.
The HALT mode stops the system oscillator and
ignores the external signal to conserve power.
Watchdog timer - WDT
The WDT clock source is implemented by a dedicated RC oscillator (WDT oscillator) or instruction clock (system clock divided by 4), decided
by mask option. This timer is designed to prevent a software malfunction or the program sequence from jumping to an unknown location
with unpredictable results. The watchdog
timer can be disabled by mask option. If the
watchdog timer is disabled, all the executions
related to the WDT result in no operation.
If an RC oscillator is used, an external resistor
between OSC1 and VDD is needed and the resistance must range from 51kW to 1MW. The
system clock, divided by four, is available on
OSC2, which can be used to synchronize external logic. The RC oscillator provides the most
cost effective solution. However, the frequency
of the oscillation may vary with VDD, temperature and the chip itself due to process variations. It is, therefore, not suitable for timing
sensitive operations where accurate oscillator
frequency is desired.
Once the internal WDT oscillator (RC oscillator
with period 78ms normally) is selected, it is first
divided by 256 (8-stages) to get the nominal
time-out period of approximately 20 ms. This
time-out period may vary with temperature,
VDD and process variations. By invoking the
WDT prescaler, longer time-out periods can be
realized. Writing data to WS2, WS1, WS0 (bit
2,1,0 of the WDTS) can give different time-out
periods. If WS2, WS1, WS0 are all equal to 1,
the division ratio is up to 1:128, and the maximum time-out period is 2.6 seconds.
If a crystal oscillator is used, a crystal across
OSC1 and OSC2 is needed to provide the feedback and phase shift needed for oscillator. No
other external components are needed. Instead
If the WDT oscillator is disabled, the WDT clock
may still come from the instruction clock and
operate in the same manner except that in the
HALT state the WDT may stop counting and
lose its protection purpose. In this situation the
WDT logic can only be restarted by external
logic. The high nibble and bit 3 of the WDTS are
reserved for user defined flags, which can be
used to indicate some specified status.
V D D
O S C 1
O S C 1
0 .0 1 m F
O S C 2
C r y s ta l O s c illa to r
fS Y S /4
(N M O S o p e n
d r a in o u tp u t)
O S C 2
R C
If the device operates in a noisy environment,
using the on-chip RC oscillator (WDT OSC) is
strongly recommended, since the HALT will
stop the system clock.
O s c illa to r
System oscillator
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HT99C410/HT99C411
WS2
WS1
WS0
Division Ratio
0
0
0
1:1
0
0
1
1:2
0
1
0
1:4
0
1
1
1:8
1
0
0
1:16
1
0
1
1:32
1
1
0
1:64
1
1
1
1:128
Power down operation - HALT
The HALT mode is initialized by the HALT instruction and results in the following...
· The system oscillator will turn off but the
·
·
·
WDTS register
·
The system can quit the HALT mode by means
of an external reset, an interrupt, an external
falling edge signal on port A or a WDT overflow.
An external reset causes a device initialization
and the WDT overflow performs a "warm reset"
Examining the TO and PD flags, the reason for
the chip reset can be determined. The PD flag is
cleared when system power-up or executing the
CLR WDT instruction and is set when the HALT
instruction is executed. The TO flag is set if the
WDT time-out occurs, which causes a wake-up
that only resets the PC and SP, and leaves the
others in their original status.
The overflow of the WDT under normal operation will initialize "chip reset" and set the status bit "TO". An overflow in the HALT mode
initializes a "warm reset" only when the PC and
SP are reset to zero. To clear the contents of the
WDT (including the WDT prescaler ), there are
three methods to be adopted; external reset (a
low level to RES), software instruction, and a
HALT instruction. There are two types of software instruction, CLR WDT and CLR WDT1/
CLR WDT2. But only one of these two types of
instruction can be active depending on the
mask option - "CLR WDT times selection option". If the "CLR WDT" is selected (i.e. CLR
WDT times equal one), any execution of the
CLR WDT instruction will clear the WDT. In
case CLR WDT1 and CLR WDT2 are chosen (i.e. CLRWDT times equal two), these two
instructions must be executed to clear the
WDT; otherwise, the WDT may reset the chip
due to a time-out.
S y s te m
WDT oscillator keeps running (if the WDT oscillator is selected).
The contents of the on-chip RAM and registers remain unchanged.
WDT and WDT prescaler will be cleared and
counted again (if the WDT clock is from the
WDT oscillator).
All I/O ports remain in their original status.
The PD flag is set and the TO flag is cleared.
The port A wake-up and interrupt methods can
be considered as a continuation of normal execution. Each bit in port A can be independently
selected to wake up the device by mask option.
Awakening from an I/O port stimulus, the program will resume execution of the next instruction. However, if the program awakens from an
interrupt, two sequences may occur. The pro-
C lo c k /4
W D T
O S C
M a s k
O p tio n
S e le c t
W D T P r e s c a le r
8 - b it C o u n te r
7 - b it C o u n te r
8 -to -1 M U X
W S 0 ~ W S 2
W D T T im e - o u t
Watchdog timer
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HT99C410/HT99C411
V D D
gram will resume execution at the next instruction if the related interrupt(s) is (are) disabled
or the interrupt(s) is enabled but the stack is
full. A regular interrupt response takes place if
the interrupt is enabled and the stack is not
full.
1 0 0 k W
R E S
0 .1 m F
Once the wake-up event(s) occurs, and the system clock comes from a crystal, it takes 1024
tSYS (system clock period) to resume normal operation. In other words, a dummy period will be
inserted after the wake-up. If the system clock
comes from an RC oscillator, it continues operating immediately. If the wake-up results from
an interrupt acknowledgment, the actual interrupt subroutine execution will delay by one
more cycle. If the wake-up results in the next
instruction execution, this will be executed immediately after the dummy period is completed.
Reset circuit
To minimize power consumption, all I/O pins
should be carefully managed before entering
the HALT status.
· RES reset during normal operation
· RES reset during HALT
· WDT time-out reset during normal operation
0
0
RES reset during power-up
u
u
RES reset during normal
operation
0
1
RES wake-up HALT
1
u
WDT time-out during normal
operation
1
1
WDT wake-up HALT
When the system power up occurs, the SST delay is added during the reset period. But when
the reset comes from the RES pin, the SST delay is disabled. Any wake-up from HALT will
enable the SST delay.
The WDT time-out during HALT is different
from other chip reset conditions, since it can
perform a warm reset that just resets the PC
and SP, leaving the other circuits in their original state. Some registers remain unchanged
during other reset conditions. Most registers
are reset to the "initial condition" when the reset conditions are met. By examining the PD
and TO flags, the program can distinguish between different "chip resets".
H A L T
W D T
O S C 1
tS
W a rm
W D T
R e s e t
T im e - o u t
R e s e t
R E S
V D D
R E S
RESET Conditions
To guarantee that the system oscillator has
started and stabilized, the SST (System
Start-up Timer) provides an extra-delay, to delay 1024 system clock pulses when the system
powers up or awakes from the HALT state.
There are three ways in which a reset can occur:
S T
C o ld
R e s e t
S S T
1 0 -s ta g e
R ip p le C o u n te r
P o w e r - o n D e te c tio n
S S T T im e - o u t
R e s e t
PD
Note: "u" means "unchanged"
Reset
C h ip
TO
Reset configuration
tS
S T
: d e p e n d s o n O S C
m a s k o p tio n
Reset timing chart
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HT99C410/HT99C411
There are three registers related to the
timer/event counter 0; TMR0H (0CH), TMR0L
(0DH), TMR0C (0EH). Writing TMR0L only
writes the data into a low byte buffer, and writing
TMR0H will write the data and the contents of
the low byte buffer into the timer/event counter 0
preload register (16-bit) simultaneously. The
timer/event counter 0 Preload register is changed
by writing TMR0H operations and writing
TMR0L will keep the timer/event counter 0
Preload register unchanged.
The functional unit chip reset status is shown
below.
PC
000H
Interrupt
Disabled
Prescaler
Cleared
WDT
Cleared. After master
reset, WDT starts
counting
Timer/event
counter (0/1)
Off
Input/output Ports
Input mode
SP
Points to the top of
the stack
Reading TMR0H will also latch the TMR0L
into the low byte buffer to avoid the false timing
problem. Reading TMR0L returns the contents
of the low byte buffer. In other words, the low
byte of timer/event counter 0 can not be read directly. It must read the TMR0H first to make
the low byte content of timer/event counter 0
latched into the buffer.
Timer/event counter
Two timer/event counters are implemented in
the HT99C410/HT99C411. The timer/event
counter 0 and timer/event counter 1 contain
16-bit and 8-bit programmable count-up counters respectively and the clock may come from
an external source or the system clock divided by
4.
There are two sets of registers related to the
timer/event counter 1; TMR1 (10H), TMR1C
(11H). Writing TMR1 puts the starting value in
the timer/event counter 1 Preload register and
reading TMR1 gets the contents of the
timer/event counter 1.
The TMR0C is the timer/event counter 0 control
register, which defines the timer/event counter 0
options. The timer/event counter 1 has the same
options as the timer/event counter 0 and is defined by TMR1C.
Using the internal instruction clock, there is
only one reference time-base. The external
clock input allows the user to count external
events, measure time intervals or pulse width,
or generate an accurate time base.
Label
Bits
¾
0~2
TE
3
To define the TMR0/TMR1 active edge of the timer/event counter
(0=active on low to high; 1=active on high to low)
TON
4
To enable/disable timer counting
(0=disabled; 1=enabled)
¾
5
Unused bits, read as "0"
6
7
To define the operating mode
01=Event count mode (external clock)
10=Timer mode (internal clock)
11=Pulse width measurement mode
00=Unused
TM0
TM1
Function
Unused bits, read as "0"
TMR0C/TMR1C register
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HT99C410/HT99C411
The states of the registers are summarized in the following table:
Register
Reset
(power on)
WDT timeout (normal
operation)
RES reset
(normal
operation)
RES reset
(HALT)
WDT
time-out*
(HALT)
TMR1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR1C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
TMR0H
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0L
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TMR0C
00-0 1---
00-0 1---
00-0 1---
00-0 1---
uu-u u---
PC
000H
000H
000H
000H
000H
MP0
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
MP1
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
ACC
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLP
xxxx xxxx
uuuu uuuu
uuuu uuuu
uuuu uuuu
uuuu uuuu
TBLH
-xxx xxxx
-uuu uuuu
-uuu uuuu
-uuu uuuu
-uuu uuuu
STATUS
--00 xxxx
--1u uuuu
--uu uuuu
--01 uuuu
--11 uuuu
INTC
-000 0000
-000 0000
-000 0000
-000 0000
-uuu uuuu
WDTS
0000 0111
0000 0111
0000 0111
0000 0111
uuuu uuuu
PA
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PAC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PB
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PBC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
D/A Output Register
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
D/A Control Register
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PD
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
PDC
1111 1111
1111 1111
1111 1111
1111 1111
uuuu uuuu
Note: "*" means "warm reset"
"x" means "unknown"
"u" means "unchanged"
"-" means "undefined"
The bits of the special function registers are denoted as "-" if they are not defined
in the microcontrollers.
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HT99C410/HT99C411
In the pulse width measurement mode with the
TON and TE bits equal to one, when the
TMR0/TMR1 receives a transient from low to
high (or high to low; if the TE bit is 0) it will start
counting until the TMR0/TMR1 returns to the
original level and resets the TON as well. The
measured result will remain in the timer/event
counter even if the activated transient occurs
again. In other words, only one cycle measurements can be made until the TON is set. The cycle measurement will function again as long as it
receives further transient pulse. Note that, in
this operation mode, the timer/event counter
starts counting not according to the logic level but
according to the transient edges. In the case of
counter overflows, the counter is reloaded from
the timer/event counter preload register and issues an interrupt request similar to the other two
modes.
The timer/event counter control registers define the operating mode, counting enable or disable and active edge.
The TM0, TM1 bits define the operating mode.
The event count mode is used to count external
events, which means the clock source comes
from an external (TMR0/TMR1) pin. The Timer
mode functions as a normal timer with the
clock source coming from the instruction clock.
The pulse width measurement mode can be
used to count the high or low level duration of
the external signal (TMR0/TMR1). The counting is based on the instruction clock.
In the event count or timer mode, once the
timer/event counter starts counting, it will
count from the current contents in the
timer/event counter to FFFFH (TMR0)/FFH
(TMR1). Once an overflow occurs, the counter is
reloaded from the Timer/event Counter Preload
register and generates the corresponding interrupt request flag (T0F/T1F; bit 5/6 of INTC) at
the same time.
S y s te m
C lo c k /4
T M R 0
To enable the counting operation, the Timer ON
bit (TON; bit 4 of TMR0C/TMR1C) should be
set to 1. In the pulse width measurement mode,
D a ta B u s
T M 1
T M 0
T im e r /E v e n t C o u n te r 0
P r e lo a d R e g is te r
R e lo a d
T E
T im e r /E v e n t
C o u n te r 0
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
T M 1
T M 0
T O N
O v e r flo w
to In te rru p t
L o w B y te
B u ffe r
Timer/event counter 0
S y s te m
C lo c k /4
T M R 1
D a ta B u s
T M 1
T M 0
T im e r /E v e n t C o u n te r 1
P r e lo a d R e g is te r
R e lo a d
T E
T M 1
T M 0
T O N
T im e r /E v e n t
C o u n te r 1
P u ls e W id th
M e a s u re m e n t
M o d e C o n tro l
O v e r flo w
to In te rru p t
Timer/event counter 1
21
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HT99C410/HT99C411
tions. For input operation, these ports are
non-latching, that is, the inputs must be ready
at the T2 rising edge of instruction MOV A,[m]
(m=12H, 14H, or 18H). For output operation, all
data is latched and remains unchanged until the
output latch is rewritten.
the TON will be cleared automatically after the
measurement cycle is completed. But in the
other two modes the TON can only be reset by
instruction. The overflow of the timer/event
counter is one of the wake-up sources. No matter what the operation mode is, writing a 0 to
ET0I/ET1I can disable the corresponding interrupt service.
Each I/O line has its own control register (PAC,
PBC, PDC) to control the input/output configuration. With this control register, CMOS output or
schmitt trigger input with or without pull-high
resistor (mask option) structures can be reconfigured dynamically (i.e., on-the-fly) under software
control. To function as an input, the corresponding latch of the control register must write a 1 .
The pull-high resistance will exhibit automatically if the pull-high option is selected. The input
source(s) also depend(s) on the control register. If
the control register bit is "1", the input will read
the pad state. If the control register bit is "0", the
contents of the latches will move to the internal
bus. The latter is possible in "read-modify-write"
instruction. For output function, CMOS is the
only configuration. These control registers are
mapped to locations 13H, 15H, and 19H.
In the case of timer/event counter OFF condition, writing data to the timer/event counter
Preload register will also reload that data to
timer/event counter. But if the Timer/event
counter is turned on, data written to the
timer/event counter will only be kept in the
Timer/event counter Preload register. The
Timer/event counter will still operate until
an overflow occurs.
When the timer/event counter (reading
TMR0H/TMR1) is read, the clock will be
blocked to avoid errors. As this may result in a
counting error, this must be taken into consideration by the programmer.
Input/output ports
After a chip reset, these input/output lines stay
at high levels or floating (mask option). Each
bit of these input/output latches can be set or
cleared by the SET [m].i or CLR [m].i (m=12H,
14H or 18H) instruction.
There are 24 bidirectional input/output lines in
the HT99C410/HT99C411, labeled PA, PB and
PD, which are mapped to the data memory of
[12H], [14H], and [18H] respectively. All these
I/O ports can be used for input and output opera-
D a ta B u s
V D D
Q
D
W r ite C o n tr o l R e g is te r
C K
Q
V D D
S
C h ip R e s e t
o n ly
P A 0 ~ P A 7
P B 0 ~ P B 7
P D 0 ~ P D 7
Q
D
C K
S
Q
M
R e a d I/O
S y s te m
P A 0 ~ P A 7
P D 0 ~ P D 7
M a s k O p tio n
R e a d C o n tr o l R e g is te r
W r ite I/O
W e a k
P u ll- u p
U
X
W a k e - u p ( P A o n ly )
M a s k O p tio n
Input/output ports
22
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HT99C410/HT99C411
data memory of [16H] and its corresponding
control register is mapped to location [17H]
which must be set to 0 after initialization,
when using the D/A function.
Some instructions first input data and then follow the output operations. For example, the
SET [m].i, CLR [m].i, CPL [m] and CPLA [m]
instructions read the entire port states into the
C P U , ex ec ute t he d ef i ned op e r a t i o n s
(bit-operation), and then write the results back
to the latches or the accumulator.
Mask option
The following table shows five kinds of mask options in the HT99C410/HT99C411. All the mask
options must be defined to ensure proper system
functioning.
Each line of port A has the capability to wake-up
the device.
The 8-bit D/A output register is mapped to the
No.
Mask Option
1
OSC type selection. This option is to decide whether an RC or Crystal oscillator is chosen as system clock. If the Crystal oscillator is selected, the XST (Crystal Start-up
Timer) default is activated; otherwise the XST is disabled.
2
WDT source selection. There are three types of selection: on-chip RC oscillator, instruction clock or disable the WDT.
3
CLRWDT times selection. This option defines how to clear the WDT by instruction.
One time means that the CLR WDT instruction can clear the WDT. Two times
means that only if both of the CLR WDT1 and CLR WDT2 instructions have been executed, then the WDT can be cleared.
4
Wake-up selection. This option defines the activity of the wake-up function. External
I/O pins (PA only) all have the capability to wake-up the chip from a HALT.
5
Pull-high selection. This option is to determine whether the pull-high resistance is visible or not in the input mode of the I/O ports. Each bit of an I/O port can be independently selected. (See Note)
Note: There are no pull-high selections in port B of HT99C410/HT99C411.
There are pull-high selections in port A and port D of HT99C410 but they are always
pulled-high in port A and port D of HT99C411.
There are no mask option in port C of HT99C410/HT99C411
23
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HT99C410/HT99C411
Select the TSEL and OSEL to program and verify the program PROM and the option PROM.
Use the R/W(PA6) to select either programming
or verification
HT99C411 PROM programming and verification
The program memory used in the HT99C411 is
arranged into a 4K´15 bits program PROM and
a 1´14 bits option PROM. The program code
and option code are stored in the program
PROM and option PROM. The programming of
PROM can be summarized in nine steps as described below:
The address is incremented by one automatically after a code verification cycle. If the discontinued address programming or verification
is carried out, the automatic addressing increment is disabled. For the discontinued address
programming and verification, the CS pin must
return to a high level for a programming or verification cycle, i.e. if a discontinued address is
implemented, the programming or verification
cycle must be interrupted and restarted as well.
· Power on
· Set VPP (RES) to 12.5V
· Set CS (PA5) to low
Let PA3~PA0 (AD3~AD0) be the address and
data bus and the PA4 (CLK) be the clock input.
The data on the AD3~AD0 pins will be clocked
into or out of the HT99C411 on the falling edge
of PA4 (CLK) for PROM programming and verification.
The related pins of PROM programming and
verification are listed in the following table.
Pin
Function
Name
The address data contains the code address (11
bits) and two option bits. A complete write cycle
will contain 4 CLK cycles. The first cycle, bits
0~3 of the address are latched into the
HT99C411. The second and third cycles, bits
4~7 and bits 8~10 are latched respectively. The
fourth cycle, bit 2 is the TSEL option bit and bit
3 is the OSEL option bit. Bit 3 in the third cycle
and bits 0~1 in the fourth cycle are undefined.
If the TSEL is "1" and the OSEL is "0", the
TEST memory will be read. If the TSEL is "0"
and the OSEL is "1", the option PROM will be
accessed. If both the TSEL and OSEL are "0",
the program PROM will be managed.
PA0
AD0
Bit 0 of address/data bus
PA1
AD1
Bit 1 of address/data bus
PA2
AD2
Bit 2 of address/data bus
PA3
AD3
Bit 3 of address/data bus
PA4
CLK
Serial clock input for address and data
PA5
CS
Chip select, active low
PA6
R/W
Read/write control input
RES
VPP
Programming power
supply
The timing charts of programming and verification are as shown. There is a LOCK signal for
code protection. If the LOCK is "1", reading the
code will return the result "1". However, if the
LOCK is "0", the code protection is disabled and
the code always can be read until the LOCK is
programmed as "1".
The code data is 14 bits wide. A complete
read/write cycle contains 4 CLK cycles. In the
first cycle, bits 0~3 of the code data are accessed. In the second and third, bits 4~7 and
bits 8~11 are accessed respectively. In the
fourth cycle, bits 12~13 are accessed. Bits
14~15 are undefined. During code verification,
reading will return the result "00".
24
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Description
November 17, 1999
HT99C410/HT99C411
Application Circuits
Cordless phone controller arrangement
· Base unit: HT99C410/HT99C411
PA0
PO
PB0
INUSE
PD0
MODE
PA1
PA2
PA3
DATI
DATO
TXEN
PB1
PB2
PB3
KT
RING
HKS
PD1
PD2
PD3
M/BR
CARRY
LED
PA4
PA5
PA6
PA7
PWDN
FTS
FCD
INT/PAGE
PB4
PB5
PB6
PB7
HDO
HLEN
BLEN
SPKEN
PD4
PD5
PD6
PD7
D0
D1
D2
D3
A N T
S p litte r
AOUT
DTMF
T IP
S P K
B a s e U n it
R IN G
R F U n it R e c e iv e r
W a v e
S h a p in g
D A T I
3 .5 8 M H z
X 2
X 1
C A R R Y
F re q u e n c y
S y n th e s iz e r
P o w e r o n
R e s e t
S P K
S P K E N
M IC
K T
D 1
P O
M O D E
M /B R
F T S
H K S
P A G E
C h a rg e
T e r m in a l
P A G E
R E S
V S S
S W
T X E N
M IC
H L E N
R IN G
D T M F
D 3
O P T IO N
H D O
B L E N
D 0
D 2
S p e e c h
C ir c u it
&
H y b r id
C ir c u it
F C D
V D D
S e c u r ity
C o d e
D C
P o w e r
S u p p ly
A C 1 1 0 V
D A T O
R F U n it T r a n s m itte r
H T 9 9 C 4 1 0 /H T 9 9 C 4 1 1
W a v e
S h a p in g
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HT99C410/HT99C411
Instruction Set Summary
Mnemonic
Description
Flag Affected
Add data memory to ACC
Add ACC to data memory
Add immediate data to ACC
Add data memory to ACC with carry
Add ACC to register with carry
Subtract immediate data from ACC
Subtract data memory from ACC
Subtract data memory from ACC with result in data memory
Subtract data memory from ACC with carry
Subtract data memory from ACC with carry, result in data
memory
Decimal adjust ACC for addition with result in data memory
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Z,C,AC,OV
Arithmetic
ADD A,[m]
ADDM A,[m]
ADD A,x
ADC A,[m]
ADCM A,[m]
SUB A,x
SUB A,[m]
SUBM A,[m]
SBC A,[m]
SBCM A,[m]
DAA [m]
C
Logic Operation
AND A,[m]
OR A,[m]
XOR A,[m]
ANDM A,[m]
ORM A,[m]
XORM A,[m]
AND A,x
OR A,x
XOR A,x
CPL [m]
CPLA [m]
AND data memory to ACC
OR data memory to ACC
Exclusive-OR data memory to ACC
AND ACC to data memory
OR ACC to data memory
Exclusive-OR ACC to data memory
AND immediate data to ACC
OR immediate data to ACC
Exclusive-OR immediate data to ACC
Complement data memory
Complement data memory with result in ACC
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Z
Increment and Decrement
INCA [m]
INC [m]
DECA [m]
DEC [m]
Increment data memory with result in ACC
Increment data memory
Decrement data memory with result in ACC
Decrement data memory
Z
Z
Z
Z
Rotate
RRA [m]
RR [m]
RRCA [m]
RRC [m]
RLA [m]
RL [m]
RLCA [m]
RLC [m]
Rotate data memory right with result in ACC
Rotate data memory right
Rotate data memory right through carry with result in ACC
Rotate data memory right through carry
Rotate data memory left with result in ACC
Rotate data memory left
Rotate data memory left through carry with result in ACC
Rotate data memory left through carry
26
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None
None
C
C
None
None
C
C
November 17, 1999
HT99C410/HT99C411
Mnemonic
Description
Flag Affected
Data Move
MOV A,[m]
MOV [m],A
MOV A,x
Move data memory to ACC
Move ACC to data memory
Move immediate data to ACC
None
None
None
Clear bit of data memory
Set bit of data memory
None
None
Jump unconditional
Skip if data memory is zero
Skip if data memory is zero with data movement to ACC
Skip if bit i of data memory is zero
Skip if bit i of data memory is not zero
Skip if increment data memory is zero
Skip if decrement data memory is zero
Skip if increment data memory is zero with result in ACC
Skip if decrement data memory is zero with result in ACC
Subroutine call
Return from subroutine
Return from subroutine and load immediate data to ACC
Return from interrupt
None
None
None
None
None
None
None
None
None
None
None
None
None
Read ROM code (current page) to data memory and TBLH
Read ROM code (last page) to data memory and TBLH
None
None
Bit Operation
CLR [m].i
SET [m].i
Branch
JMP addr
SZ [m]
SZA [m]
SZ [m].i
SNZ [m].i
SIZ [m]
SDZ [m]
SIZA [m]
SDZA [m]
CALL addr
RET
RET A,x
RETI
Table Read
TABRDC [m]
TABRDL [m]
Miscellaneous
NOP
CLR [m]
SET [m]
CLR WDT
CLR WDT1
CLR WDT2
SWAP [m]
SWAPA [m]
HALT
No operation
Clear data memory
Set data memory
Clear the watchdog timer
Pre-clear the watchdog timer
Pre-clear the watchdog timer
Swap nibbles of data memory
Swap nibbles of data memory with result in ACC
Enter power down mode
Note: x: 8-bit immediate data
None
None
None
TO,PD
TO*,PD*
TO*,PD*
None
None
TO,PD
addr: 12-bit program memory address
m: 8-bit data memory address
Ö : Flag(s) is affected
A: accumulator
-: Flag(s) is not affected
i: 0~7 number of bits
*: Flag(s) may be affected by the execution status
27
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HT99C410/HT99C411
Instruction Definition
ADC A,[m]
Add data memory and carry to accumulator
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADCM A,[m]
Add accumulator and carry to data memory
Description
The contents of the specified data memory, accumulator and the carry flag
are added simultaneously, leaving the result in the specified data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,[m]
Add data memory to accumulator
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the accumulator.
Operation
ACC ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
ADD A,x
Add immediate data to accumulator
Description
The contents of the accumulator and the specified data are added, leaving
the result in the accumulator.
Operation
ACC ¬ ACC+x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
28
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HT99C410/HT99C411
ADDM A,[m]
Add accumulator to data memory
Description
The contents of the specified data memory and the accumulator are added.
The result is stored in the data memory.
Operation
[m] ¬ ACC+[m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
AND A,[m]
Logical AND accumulator with data memory
Description
Data in the accumulator and the specified data memory performs a bitwise
logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC AND [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
AND A,x
Logical AND immediate data to accumulator
Description
Data in the accumulator and the specified data performs a bitwise logical_AND operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC AND x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ANDM A,[m]
Logical AND data memory with accumulator
Description
Data in the specified data memory and the accumulator performs a bitwise
logical_AND operation. The result is stored in the data memory.
Operation
[m] ¬ ACC AND [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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CALL addr
Subroutine call
Description
The instruction unconditionally calls a subroutine located at the indicated
address. The program counter increments once to obtain the address of the
next instruction, and pushes this onto the stack. The indicated address is
then loaded. Program execution continues with the instruction at this address.
Operation
Stack ¬ PC+1
PC ¬ addr
Affected flag(s)
CLR [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Clear data memory
Description
The contents of the specified data memory are cleared to zero.
Operation
[m] ¬ 00H
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR [m].i
Clear bit of data memory
Description
The bit i of the specified data memory is cleared to zero.
Operation
[m].i ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
CLR WDT
Clear the watchdog timer
Description
The WDT and the WDT Prescaler are cleared (re-counting from zero). The
power down bit (PD) and time-out bit (TO) are cleared.
Operation
WDT and WDT Prescaler ¬ 00H
PD and TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
0
¾
¾
¾
¾
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CLR WDT1
Preclear the watchdog timer
Description
The PD, TO flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction had been executed. Only execution of this instruction without the other preclear instruction just sets the
indicating flag which implies that this instruction was executed and the PD
and TO flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CLR WDT2
Preclear the watchdog timer
Description
The PD and TO flags, WDT and the WDT Prescaler are cleared (re-counting
from zero), if the other preclear WDT instruction had been executed. Only execution of this instruction without the other preclear instruction, sets the indicating flag which implies that this instruction was executed and the PD
and TO flags remain unchanged.
Operation
WDT and WDT Prescaler ¬ 00H*
PD and TO ¬ 0*
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0*
0*
¾
¾
¾
¾
CPL [m]
Complement data memory
Description
Each bit of the specified data memory is logically complemented (1 s complement). Bits which previously contain a one are changed to zero and
vice-versa.
Operation
[m] ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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CPLA [m]
Complement data memory and place result in accumulator
Description
Each bit of the specified data memory is logically complemented (1's complement). Bits which previously contained a one are changed to zero and
vice-versa. The complemented result is stored in the accumulator and the
contents of the data memory remain unchanged.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
DAA [m]
Decimal-Adjust the accumulator for addition
Description
The accumulator value is adjusted to the BCD (Binary Code Decimal) code.
The accumulator is divided into two nibbles. Each nibble is adjusted to the
BCD code and an internal carry (AC1) will be done if the low nibble of the accumulator is greater than 9. The BCD adjustment is done by adding 6 to the
original value if the original value is greater than 9 or a carry (AC or C) is set;
otherwise the original value remains unchanged. The result is stored in the
data memory and only the carry flag (C) may be affected.
Operation
If (ACC.3~ACC.0) >9 or AC=1
then ([m].3~[m].0) ¬ (ACC.3~ACC.0)+6, AC1=AC
else ([m].3~[m].0) ¬ (ACC.3~ACC.0), AC1=0
If (ACC.7~ACC.4)+AC1 >9 or C=1
then ([m].7~[m].4) ¬ (ACC.7~ACC.4)+6+AC1, C=1
else ([m].7~[m].4) ¬ (ACC.7~ACC.4)+AC1, C=C
Affected flag(s)
DEC [m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
Decrement data memory
Description
Data in the specified data memory is decremented by one.
Operation
[m] ¬ [m] 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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DECA [m]
Decrement data memory and place result in accumulator
Description
Data in the specified data memory is decremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m] 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
HALT
Enter power down mode
Description
This instruction stops the program execution and turns off the system clock.
The contents of the RAM and registers are retained. The WDT and prescaler
are cleared. The power down bit (PD) is set and the WDT time-out bit (TO) is
cleared.
Operation
PC ¬ PC+1
PD ¬ 1
TO ¬ 0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
0
1
¾
¾
¾
¾
INC [m]
Increment data memory
Description
Data in the specified data memory is incremented by one.
Operation
[m] ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
INCA [m]
Increment data memory and place result in accumulator
Description
Data in the specified data memory is incremented by one, leaving the result
in the accumulator. The contents of the data memory remain unchanged.
Operation
ACC ¬ [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
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JMP addr
Direct Jump
Description
Bits 0~11 of the program counter are replaced with the directly-specified address unconditionally, and control passed to this destination.
Operation
PC ¬ addr
Affected flag(s)
MOV A,[m]
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Move data memory to accumulator
Description
The contents of the specified data memory is copied to the accumulator.
Operation
ACC ¬ [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV A,x
Move immediate data to accumulator
Description
The 8 bit data specified by the code is loaded into the accumulator .
Operation
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
MOV [m],A
Move accumulator to data memory
Description
The contents of the accumulator is copied to the specified data memory (one
of the data memory).
Operation
[m] ¬ ACC
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
NOP
No operation
Description
No operation is performed. Execution continues with the next instruction.
Operation
PC ¬ PC+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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OR A,[m]
Logical OR accumulator with data memory
Description
Data in the accumulator and the specified data memory (one of the data
memory) performs a bitwise logical_OR operation. The result is stored in the
accumulator.
Operation
ACC ¬ ACC OR [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
OR A,x
Logical OR immediate data to accumulator
Description
Data in the accumulator and the specified data performs a bitwise logical_OR operation. The result is stored in the accumulator.
Operation
ACC ¬ ACC OR x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
ORM A,[m]
Logical OR data memory with accumulator
Description
Data in the data memory (one of the data memory) and the accumulator performs a bitwise logical_OR operation. The result is stored in the data memory.
Operation
[m] ¬ ACC OR [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
RET
Return from subroutine
Description
The program counter is restored from the stack. This is a two cycle instruction.
Operation
PC ¬ Stack
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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RET A,x
Return and place immediate data in accumulator
Description
The program counter is restored from the stack and the accumulator loaded
with the specified 8-bit immediate data.
Operation
PC ¬ Stack
ACC ¬ x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RETI
Return from interrupt
Description
The program counter is restored from the stack, and the interrupts are enabled by setting the EMI bit. EMI is the enable master (global) interrupt bit
(bit 0; register INTC).
Operation
PC ¬ Stack
EMI ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RL [m]
Rotate data memory left
Description
The contents of the specified data memory is rotated left, one bit with bit 7 rotated into bit 0.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RLA [m]
Rotate data memory left and place result in accumulator
Description
Data in the specified data memory is rotated left, one bit with bit 7 rotated
into bit 0, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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RLC [m]
Rotate data memory left through carry
Description
The contents of the specified data memory and the carry flag are together rotated left one bit. Bit 7 replaces the carry bit; the original carry flag is rotated
into the bit 0 position.
Operation
[m].(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
[m].0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RLCA [m]
Rotate left through carry and place result in accumulator
Description
Data in the specified data memory and the carry flag are together rotated left
one bit. Bit 7 replaces the carry bit and the original carry flag is rotated into
bit 0 position. The rotated result is stored in the accumulator but the contents of the data memory remain unchanged.
Operation
ACC.(i+1) ¬ [m].i; [m].i:bit i of the data memory (i=0~6)
ACC.0 ¬ C
C ¬ [m].7
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RR [m]
Rotate data memory right
Description
The contents of the specified data memory are rotated right one bit with bit 0
rotated to bit 7.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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RRA [m]
Rotate right and place result in accumulator
Description
Data in the specified data memory is rotated right one bit with bit 0 rotated
into bit 7, leaving the rotated result in the accumulator. The contents of the
data memory remain unchanged.
Operation
ACC.(i) ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
RRC [m]
Rotate data memory right through carry
Description
The contents of the specified data memory and the carry flag are together rotated right one bit. Bit 0 replaces the carry bit; the original carry flag is rotated into the bit 7 position.
Operation
[m].i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
[m].7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
RRCA [m]
Rotate right through carry and place result in accumulator
Description
Data of the specified data memory and the carry flag are together rotated
right one bit. Bit 0 replaces the carry bit and the original carry flag is rotated
into the bit 7 position. The rotated result is stored in the accumulator. The
contents of the data memory remain unchanged.
Operation
ACC.i ¬ [m].(i+1); [m].i:bit i of the data memory (i=0~6)
ACC.7 ¬ C
C ¬ [m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
Ö
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SBC A,[m]
Subtract data memory and carry from accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are together subtracted from the accumulator, leaving the result in the
accumulator.
Operation
ACC ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SBCM A,[m]
Subtract data memory and carry from accumulator
Description
The contents of the specified data memory and the complement of the carry
flag are together subtracted from the accumulator, leaving the result in the
data memory.
Operation
[m] ¬ ACC+[m]+C
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SDZ [m]
Skip if decrement data memory is zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. If the result is zero, the following
instruction, fetched during the current instruction execution, is discarded
and a dummy cycle replaced to get the proper instruction. This makes a 2 cycle instruction. Otherwise proceed with the next instruction.
Operation
Skip if ([m] 1)=0, [m] ¬ ([m] 1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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SDZA [m]
Decrement data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory are decremented by one. If the result is zero, the next instruction is skipped. The result is stored in the accumulator but the data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle is replaced to get the proper instruction, that
makes a 2 cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m] 1)=0, ACC ¬ ([m] 1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SET [m]
Set data memory
Description
Each bit of the specified data memory is set to one.
Operation
[m] ¬ FFH
Affected flag(s)
SET [m].i
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
Set bit of data memory
Description
Bit i of the specified data memory is set to one.
Operation
[m].i ¬ 1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SIZ [m]
Skip if increment data memory is zero
Description
The contents of the specified data memory is incremented by one. If the result is zero, the following instruction, fetched during the current instruction
execution, is discarded and a dummy cycle is replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m]+1)=0, [m] ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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SIZA [m]
Increment data memory and place result in ACC, skip if zero
Description
The contents of the specified data memory is incremented by one. If the result is zero, the next instruction is skipped and the result stored in the accumulator. The data memory remains unchanged. If the result is zero, the
following instruction, fetched during the current instruction execution, is
discarded and a dummy cycle replaced to get the proper instruction. This is a
2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if ([m]+1)=0, ACC ¬ ([m]+1)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SNZ [m].i
Skip if bit i of the data memory is not zero
Description
If bit i of the specified data memory is not zero, the next instruction is
skipped. If bit i of the data memory is not zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction. This is a 2-cycle instruction.
Otherwise proceed to the next instruction.
Operation
Skip if [m].i¹0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SUB A,[m]
Subtract data memory from accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+[m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SUBM A,[m]
Subtract data memory from accumulator
Description
The specified data memory is subtracted from the contents of the accumulator, leaving the result in the data memory.
Operation
[m] ¬ ACC [m]+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
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SUB A,x
Subtract immediate data from accumulator
Description
The immediate data specified by the code is subtracted from the contents of
the accumulator, leaving the result in the accumulator.
Operation
ACC ¬ ACC+x+1
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
Ö
Ö
Ö
Ö
SWAP [m]
Swap nibbles within the data memory
Description
The low-order and high-order nibbles of the specified data memory (one of
the data memory) are interchanged.
Operation
[m].3~[m].0 « [m].7~[m].4
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SWAPA [m]
Swap data memory and place result in accumulator
Description
The low-order and high-order nibbles of the specified data memory are interchanged, writing the result to the accumulator. The contents of the data
memory remain unchanged.
Operation
ACC.3~ACC.0 ¬ [m].7~[m].4
ACC.7~ACC.4 ¬ [m].3~[m].0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m]
Skip if data memory is zero
Description
If the contents of the specified data memory is zero, the following instruction,
fetched during the current instruction execution, is discarded and a dummy
cycle is replaced to get the proper instruction. This is a 2-cycle instruction.
Otherwise proceed to the next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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SZA [m]
Move data memory to ACC, skip if zero
Description
The contents of the specified data memory is copied to accumulator. If the
contents is zero, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the
proper instruction. This is a 2-cycle instruction. Otherwise proceed to the
next instruction.
Operation
Skip if [m]=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
SZ [m].i
Skip if bit i of the data memory is zero
Description
If bit i of the specified data memory is zero, the following instruction, fetched
during the current instruction execution, is discarded and a dummy cycle is
replaced to get the proper instruction. This is a 2-cycle instruction. Otherwise proceed to the next instruction.
Operation
Skip if [m].i=0
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDC [m]
Move ROM code (current page) to TBLH and data memory
Description
The low byte of ROM code (current page) addressed by the table pointer
(TBLP) is moved to the specified data memory and the high byte transferred
to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
TABRDL [m]
Move ROM code (last page) to TBLH and data memory
Description
The low byte of ROM code (last page) addressed by the table pointer (TBLP)
is moved to the data memory and the high byte transferred to TBLH directly.
Operation
[m] ¬ ROM code (low byte)
TBLH ¬ ROM code (high byte)
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
¾
¾
¾
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HT99C410/HT99C411
XOR A,[m]
Logical XOR accumulator with data memory
Description
Data in the accumulator and the indicated data memory performs a bitwise
logical Exclusive_OR operation and the result is stored in the accumulator.
Operation
ACC ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XORM A,[m]
Logical XOR data memory with accumulator
Description
Data in the indicated data memory and the accumulator perform a bitwise
logical Exclusive_OR operation. The result is stored in the data memory. The
zero flag is affected.
Operation
[m] ¬ ACC "XOR" [m]
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
XOR A,x
Logical XOR immediate data to accumulator
Description
Data in the the accumulator and the specified data perform a bitwise logical
Exclusive_OR operation. The result is stored in the accumulator. The zero
flag is affected.
Operation
ACC ¬ ACC "XOR" x
Affected flag(s)
TC2
TC1
TO
PD
OV
Z
AC
C
¾
¾
¾
¾
¾
Ö
¾
¾
44
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HT99C410/HT99C411
Holtek Semiconductor Inc. (Headquarters)
No.3 Creation Rd. II, Science-based Industrial Park, Hsinchu, Taiwan, R.O.C.
Tel: 886-3-563-1999
Fax: 886-3-563-1189
Holtek Semiconductor Inc. (Taipei Office)
5F, No.576, Sec.7 Chung Hsiao E. Rd., Taipei, Taiwan, R.O.C.
Tel: 886-2-2782-9635
Fax: 886-2-2782-9636
Fax: 886-2-2782-7128 (International sales hotline)
Holtek Semiconductor (Hong Kong) Ltd.
RM.711, Tower 2, Cheung Sha Wan Plaza, 833 Cheung Sha Wan Rd., Kowloon, Hong Kong
Tel: 852-2-745-8288
Fax: 852-2-742-8657
Copyright Ó 1999 by HOLTEK SEMICONDUCTOR INC.
The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek
assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are
used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications
will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holtek reserves the right to alter its products without prior
notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
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