HYNIX HY5PS1G431LF-E4

HY5PS1G431(L)F
HY5PS1G831(L)F
1Gb DDR2 SDRAM
HY5PS1G431(L)F
HY5PS1G831(L)F
This document is a general product description and is subject to change without notice. Hynix Semiconductor does not assume any
responsibility for use of circuits described. No patent licenses are implied.
Rev. 1.2 / Dec 2006
1
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Revision History
Rev.
0.1
0.2
History
Preliminary
Corrected typos of Pin description & tRFC spec. ,
Added IDD spec.
Draft Date
Feb.2004
Apr.2004
Editorial Clean up, Transfered Functional description, command truth table pages and
Some contents of Operating conditions to <Device Operation & timing diagram>
Jul. 2004
Updated IDD spec.
Feb. 2005
1.1
Corrected typo, and removed improper note in ODT DC spec.
July 2006
1.2
Corrected Pinout Numbering
Dec 2006
1.0
Rev. 1.2 / Dec 2006
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1HY5PS1G431(L)F
1HY5PS1G831(L)F
Contents
1. Description
1.1 Device Features and Ordering Information
1.1.1 Key Feaures
1.1.2 Ordering Information
1.1.3 Ordering Frequency
1.2 Pin configuration
1.3 Pin Description
2. Maximum DC ratings
2.1 Absolute Maximum DC Ratings
2.2 Operating Temperature Condition
3. AC & DC Operating Conditions
3.1 DC Operating Conditions
5.1.1 Recommended DC Operating Conditions(SSTL_1.8)
5.1.2 ODT DC Electrical Characteristics
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
3.2.2 Input AC Logic Level
3.2.3 AC Input Test Conditions
3.2.4 Differential Input AC Logic Level
3.2.5 Differential AC output parameters
3.3 Output Buffer Levels
3.3.1 Output AC Test Conditions
3.3.2 Output DC Current Drive
3.3.3 OCD default chracteristics
3.4 IDD Specifications & Measurement Conditions
3.5 Input/Output Capacitance
4. AC Timing Specifications
5. Package Dimensions
Rev. 1.2 / Dec 2006
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1HY5PS1G431(L)F
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1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
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VDD=1.8V
VDDQ=1.8V +/- 0.1V
All inputs and outputs are compatible with SSTL_18 interface
Fully differential clock inputs (CK, /CK) operation
Double data rate interface
Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
Differential Data Strobe (DQS, DQS)
Data outputs on DQS, DQS edges when read (edged DQ)
Data inputs on DQS centers when write(centered DQ)
On chip DLL align DQ, DQS and DQS transition with CK transition
DM mask write data-in at the both rising and falling edges of the data strobe
All addresses and control inputs except data, data strobes and data masks latched on the rising
edges of the clock
Programmable CAS latency 3, 4, 5 and 6 supported
Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
Programmable burst length 4/8 with both nibble sequential and interleave mode
Internal eight bank operations with single pulsed RAS
Auto refresh and self refresh supported
tRAS lockout supported
8K refresh cycles /64ms
JEDEC standard 68ball FBGA(x4/x8)
Full strength driver option controlled by EMRS
On Die Termination supported
Off Chip Driver Impedance Adjustment supported
Read Data Strobe suupported (x8 only)
Self-Refresh High Temperature Entry
Operating Frequency
Ordering Information
Part No.
HY5PS1G431(L)F-X*
HY5PS1G831(L)F-X*
Configuration Package
256Mx4
68Ball
128Mx8
Note: -X* is the speed bin, refer to the Operation
Frequency table for complete Part No.
Rev. 1.2 / Dec 2006
Grade
tCK(ns)
CL
tRCD
tRP
Unit
-E3
5
3
3
3
Clk
-E4
5
4
4
4
Clk
-C4
3.75
4
4
4
Clk
-C5
3.75
5
5
5
Clk
-Y5
3
5
5
5
Clk
-Y6
3
6
6
6
Clk
4
1HY5PS1G431(L)F
1HY5PS1G831(L)F
1.2 Pin Configuration & Address Table
256Mx4 DDR2 Pin Configuration
1
2
NC
NC
7
3
A
8
9
NC
NC
B
C
D
VDD
NC
VSS
E
VSSQ
DQS
VDDQ
NC
VSSQ
DM
F
DQS
VSSQ
NC
VDDQ
DQ1
VDDQ
G
VDDQ
DQ0
VDDQ
NC
VSSQ
DQ3
H
DQ2
VSSQ
NC
VDDL
VREF
VSS
J
VSSDL
CK
VDD
CKE
WE
K
RAS
CK
ODT
BA0
BA1
L
CAS
CS
A10
A1
M
A2
A0
A3
A5
N
A6
A4
A7
A9
P
A11
A8
A12
NC
R
NC
A13
BA2
VSS
VDD
VDD
VSS
T
U
V
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
Rev. 1.2 / Dec 2006
ITEMS
256Mx4
# of Bank
8
Bank Address
BA0,BA1,BA2
Auto Precharge Flag
A10/AP
Row Address
A0 - A13
Column Address
A0-A9, A11
Page size
1 KB
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1HY5PS1G831(L)F
128Mx8 DDR2 PIN CONFIGURATION
1
2
NC
NC
7
3
A
8
9
NC
NC
B
C
D
VDD
NU/RDQS
VSS
E
VSSQ
DQS
VDDQ
DQ6
VSSQ
DM/RDQS
F
DQS
VSSQ
DQ7
VDDQ
DQ1
VDDQ
G
VDDQ
DQ0
VDDQ
DQ4
VSSQ
DQ3
H
DQ2
VSSQ
DQ5
VDDL
VREF
VSS
J
VSSDL
CK
VDD
CKE
WE
K
RAS
CK
ODT
BA0
BA1
L
CAS
CS
A10
A1
M
A2
A0
A3
A5
N
A6
A4
A7
A9
P
A11
A8
A12
NC
R
NC
A13
BA2
VSS
VDD
VDD
VSS
T
U
V
NC
NC
W
NC
NC
ROW AND COLUMN ADDRESS TABLE
Rev. 1.2 / Dec 2006
ITEMS
128Mx8
# of Bank
8
Bank Address
BA0, BA1, BA2
Auto Precharge Flag
A10/AP
Row Address
A0 - A13
Column Address
A0-A9
Page size
1 KB
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1HY5PS1G831(L)F
1.3 PIN DESCRIPTION
PIN
TYPE
DESCRIPTION
CK, CK
Input
Clock: CK and CK are differential clock inputs. All address and control input signals are sampled on
the crossing of the positive edge of CK and negative edge of CK. Output (read) data is referenced
to the crossings of CK and CK (both directions of crossing).
CKE
Input
Clock Enable: CKE HIGH activates, and CKE LOW deactivates internal clock signals, and device
input buffers and output drivers. Taking CKE LOW provides PRECHARGE POWER DOWN and SELF
REFRESH operation (all banks idle), or ACTIVE POWER DOWN (row ACTIVE in any bank). CKE is
synchronous for POWER DOWN entry and exit, and for SELF REFRESH entry. CKE is asynchronous
for SELF REFRESH exit. After VREF has become stable during the power on and initialization
sequence, it must be maintained for proper operation of the CKE receiver. For proper self-refresh
entry and exit, VREF must be maintained to this input. CKE must be maintained high throughout
READ and WRITE accesses. Input buffers, excluding CK, CK and CKE are disabled during POWER
DOWN. Input buffers, excluding CKE are disabled during SELF REFRESH.
CS
Input
Chip Select : All commands are masked when CS is registered HIGH. CS provides for external bank
selection on systems with multiple banks. CS is considered part of the command code.
ODT
Input
On Die Termination Control : ODT(registered HIGH) enables on die termination resistance internal
to the DDR2 SDRAM. When enabled, ODT is only applied to DQ, DQS, DQS, RDQS, RDQS, and DM
signal for x4,x8 configurations. For x16 configuration ODT is applied to each DQ,
UDQS/UDQS.LDQS/LDQS, UDM and LDM signal. The ODT pin will be ignored if the Extended Mode
Register(EMRS(1)) is programmed to disable ODT.
RAS, CAS, WE
Input
Command Inputs: RAS, CAS and WE (along with CS) define the command being entered.
Input
Input Data Mask : DM is an input mask signal for write data. Input Data is masked when DM is
sampled High coincident with that input data during a WRITE access. DM is sampled on both
edges of DQS, Although DM pins are input only, the DM loading matches the DQ and DQS loading.
For x8 device, the function of DM or RDQS/ RDQS is enabled by EMRS command.
Input
Bank Address Inputs: BA0 - BA2 define to which bank an ACTIVE, Read, Write or PRECHARGE
command is being applied(For 256Mb and 512Mb, BA2 is not applied). Bank address also determines if the mode register or extended mode register is to be accessed during a MRS or EMRS
cycle.
A0 -A15
Input
Address Inputs: Provide the row address for ACTIVE commands, and the column address and
AUTO PRECHARGE bit for READ/WRITE commands to select one location out of the memory array
in the respective bank. A10 is sampled during a precharge command to determine whether the
PRECHARGE applies to one bank (A10 LOW) or all banks (A10 HIGH). If only one bank is to be
precharged, the bank is selected by BA0-BA2. The address inputs also provide the op code during
MODE REGISTER SET commands.
DQ
Input/Output
DM
(LDM, UDM)
BA0 - BA2
Rev. 1.2 / Dec 2006
Data input / output : Bi-directional data bus
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1HY5PS1G831(L)F
-Continue-
PIN
TYPE
DESCRIPTION
Data Strobe : Output with read data, input with write data. Edge aligned with read data, centered in write data. For the x16, LDQS correspond to the data on DQ0~DQ7; UDQS corresponds to the data on DQ8~DQ15. For the x8, an RDQS option using DM pin can be enabled
via the EMRS(1) to simplify read timing. The data strobes DQS, LDQS, UDQS, and RDQS may
be used in single ended mode or paired with optional complementary signals DQS,
LDQS,UDQS and RDQS to provide differential pair signaling to the system during both reads
and wirtes. An EMRS(1) control bit enables or disables all complementary data strobe signals.
DQS, (DQS)
(UDQS),(UDQS)
(LDQS),(LDQS)
(RDQS),(RDQS)
Input/Output
In this data sheet, "differential DQS signals" refers to any of the following with A10 = 0 of
EMRS(1)
x4 DQS/DQS
x8 DQS/DQS
if EMRS(1)[A11] = 0
if EMRS(1)[A11] = 1
x8 DQS/DQS, RDQS/RDQS,
x16 LDQS/LDQS and UDQS/UDQS
"single-ended DQS signals" refers to any of the following with A10 = 1 of
EMRS(1)
x4 DQS
x8 DQS
if EMRS(1)[A11] = 0
x8 DQS, RDQS,
if EMRS(1)[A11] = 1
x16 LDQS and UDQS
No Connect : No internal electrical connection is present.
NC
VDDQ
Supply
DQ Ground
VSSQ
Supply
DQ Power Supply : 1.8V +/- 0.1V
VDDL
Supply
DLL Power Supply : 1.8V +/- 0.1V
VSSDL
Supply
DLL Ground
VDD
Supply
Power Supply : 1.8V +/- 0.1V
VSS
Supply
Ground
VREF
Supply
Reference voltage for inputs for SSTL interface.
Rev. 1.2 / Dec 2006
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1HY5PS1G831(L)F
2. Maximum DC Ratings
2.1 Absolute Maximum DC Ratings
Symbol
Rating
Units
Notes
Voltage on VDD pin relative to Vss
- 1.0 V ~ 2.3 V
V
1
VDDQ
Voltage on VDDQ pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
VDDL
Voltage on VDDL pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
Voltage on any pin relative to Vss
- 0.5 V ~ 2.3 V
V
1
-55 to +100
°C
1, 2
VDD
VIN, VOUT
TSTG
Parameter
Storage Temperature
1. . Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
2. Storage Temperature is the case surface temperature on the denter/top side of the DRAM. For the measurement conditions.
Please refer to JESD51-2 standard.
2.2 Operating Temperature Condition
Symbol
Toper
Parameter
Operating Temperature
Rating
Units
Notes
0 to 85
°C
1,2
1. Operating Temperature is the case surface temperature on the center/top side of the DRAM. For the measurement conditions,
please refer to JESD51-2 standard.
2. The operatin temperature range are the temperature where all DRAM specification will be supported. Outside of this temperature
rang, even it is still within the limit of stress condition, some deviation on portion of operation specification may be required. During
operation, the DRAM case temperature must be maintained between 0 ~ 85°C under all other specification parameters. However,
in some applications, it is desirable to operate the DRAM up to 95°C case temperature. Therefore 2 spec options may exist.
1) Supporting 0 - 85°C with full JEDEC AC & DC specifications. This is the minimum requirements for all oprating temperature
options.
2) Supporting 0 - 85°C and being able to extend to 95°C with doubling auto-refresh commands in frequency to a 32 ms
period(tRFI=3.9us).
Note; Currently the periodic Self-Refresh interval is hard coded within the DRAM to a specificic value.
There is a migration plan to support higher temperature Self-Refresh entry via the control of EMRS(2) bit A7. However, since
Self-Refresh control function is a migrated process. For our DDR2 module user, it is imperative to check SPD Byte 49 Bit 0
to ensure the DRAM parts support higer than 85°C case temperature Self-Refresh entry.
1) if SPD Byte 49 Bit 0 is a “0” means DRAM does not support Self-Refresh at higher than 85°C, then system have to ensure
the DRAM is at or below 85°C case temperature before initiating Self-Refresh operation.
2) if SPD Byte 49 Bit 0 is a “1” means DRAM supports Self-Refresh at higher than 85°C case temperature, then system can
use register bit A7 at EMRS(2) control DRAM to operate at proper Self-Refresh rate for higher temperature. Please also
refer to EMRS(2) register definition section and DDR2 DIMM SPD definition for details.
Rev. 1.2 / Dec 2006
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1HY5PS1G831(L)F
3. AC & DC Operating Conditons
3.1 DC Operating Conditions
3.1.1 Recommended DC Operating Conditions (SSTL_1.8)
Rating
Symbol
Parameter
Units
Min.
Typ.
Max.
Notes
VDD
Supply Voltage
1.7
1.8
1.9
V
VDDL
Supply Voltage for DLL
1.7
1.8
1.9
V
4
VDDQ
Supply Voltage for Output
1.7
1.8
1.9
V
4
VREF
Input Reference Voltage
0.49*VDDQ
0.50*VDDQ
0.51*VDDQ
mV
1, 2
Termination Voltage
VREF-0.04
VREF
VREF+0.04
V
3
VTT
There is no specific device VDD supply voltage requirement for SSTL-1.8 compliance. However under all conditions VDDQ must
be less than or equal to VDD.
1. The value of VREF may be selected by the user to provide optimum noise margin in the system. Typically the value of VREF is
expected to be about 0.5 x VDDQ of the transmitting device and VREF is expected to track variations in VDDQ.
2. Peak to peak ac noise on VREF may not exceed +/-2% VREF (dc).
3. VTT of transmitting device must track VREF of receiving device.
4. VDDQ tracks with VDD, VDDL tracks with VDD. AC parameters are measured with VDD, VDDQ and VDDDL tied together
3.1.2 ODT DC electrical characteristics
PARAMETER/CONDITION
Rtt effective impedance value for EMRS(A6,A2)=0,1; 75 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,0; 150 ohm
Rtt effective impedance value for EMRS(A6,A2)=1,1; 50 ohm
Deviation of VM with respect to VDDQ/2
SYMBOL
MIN
NOM
MAX
UNITS NOTES
Rtt1(eff)
Rtt2(eff)
Rtt2(eff)
delta VM
60
120
40
-6
75
150
50
90
180
60
+6
ohm
ohm
ohm
%
1
1
1
1
Note 1: Test condition for Rtt measurements
Measurement Definition for Rtt(eff): Apply VIH (ac) and VIL (ac) to test pin separately, then measure current I(VIH
(ac)) and I( VIL (ac)) respectively. VIH (ac), VIL (ac), and VDDQ values defined in SSTL_18
Rtt(eff) =
VIH (ac) - VIL (ac)
I(VIH (ac)) - I(VIL (ac))
Measurement Definition for VM : Measurement Voltage at test pin(mid point) with no load.
2 x Vm
delta VM =
Rev. 1.2 / Dec 2006
VDDQ
-1
x 100%
10
1HY5PS1G431(L)F
1HY5PS1G831(L)F
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
VIH(dc)
dc input logic high
VREF + 0.125
VDDQ + 0.3
V
VIL(dc)
dc input logic low
- 0.3
VREF - 0.125
V
Notes
3.2.2 Input AC Logic Level
Symbol
VIH (ac)
VIL (ac)
Parameter
Min.
Max.
Units
ac input logic high
VREF + 0.250
-
V
ac input logic low
-
VREF - 0.250
V
Notes
3.2.3 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
Input reference voltage
0.5 * VDDQ
V
1
VSWING(MAX)
Input signal maximum peak to peak swing
1.0
V
1
SLEW
Input signal minimum slew rate
1.0
V/ns
2, 3
Notes:
1.
2.
3.
Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device under test.
The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising edges and the range
from VREF to VIL(ac) max for falling edges as shown in the below figure.
AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions and VIH(ac) to
VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VIL(dc) max
VIL(ac) max
VSS
VSWING(MAX)
delta TF
Falling Slew =
delta TR
VREF - VIL(ac) max
delta TF
Rising Slew =
VIH(ac)min - VREF
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 1.2 / Dec 2006
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1HY5PS1G831(L)F
3.2.4 Differential Input AC logic Level
Symbol
Parameter
VID (ac)
ac differential input voltage
VIX (ac)
ac differential cross point voltage
Min.
Max.
Units
Notes
0.5
VDDQ + 0.6
V
1
0.5 * VDDQ - 0.175
0.5 * VDDQ + 0.175
V
2
1. VIN(DC) specifies the allowable DC execution of each input of differential pair such as CK, CK, DQS, DQS, LDQS, LDQS, UDQS and
UDQS.
2. VID(DC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input (such as CK, DQS, LDQS
or UDQS) level and VCP is the complementary input (such as CK, DQS, LDQS or UDQS) level. The minimum value is equal to VIH(DC) - V
IL(DC).
VDDQ
VTR
Crossing point
VID
VIX or VOX
VCP
VSSQ
< Differential signal levels >
Notes:
1. VID(AC) specifies the input differential voltage |VTR -VCP | required for switching, where VTR is the true input signal (such as CK, DQS,
LDQS or UDQS) and VCP is the complementary input signal (such as CK, DQS, LDQS or UDQS). The minimum value is equal to V IH(AC)
- V IL(AC).
2. The typical value of VIX(AC) is expected to be about 0.5 * VDDQ of the transmitting device and VIX(AC) is expected to track variations in
VDDQ . VIX(AC) indicates the voltage at which differential input signals must cross.
3.2.5 Differential AC output parameters
Symbol
VOX (ac)
Parameter
ac differential cross point voltage
Min.
Max.
Units
Notes
0.5 * VDDQ - 0.125
0.5 * VDDQ + 0.125
V
1
Notes:
1. The typical value of VOX(AC) is expected to be about 0.5 * V DDQ of the transmitting device and VOX(AC) is expected to track variations
in VDDQ . VOX(AC) indicates the voltage at whitch differential output signals must cross.
Rev. 1.2 / Dec 2006
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3.3 Output Buffer Characteristics
3.3.1 Output AC Test Conditions
Symbol
VOTR
Parameter
SSTL_18 Class II
Units
Notes
0.5 * VDDQ
V
1
SSTl_18
Units
Notes
- 13.4
mA
1, 3, 4
13.4
mA
2, 3, 4
Output Timing Measurement Reference Level
1. The VDDQ of the device under test is referenced.
3.3.2 Output DC Current Drive
Symbol
1.
2.
3.
4.
Parameter
IOH(dc)
Output Minimum Source DC Current
IOL(dc)
Output Minimum Sink DC Current
VDDQ = 1.7 V; VOUT = 1420 mV. (VOUT - VDDQ)/IOH must be less than 21 ohm for values of VOUT between VDDQ and VDDQ - 280
mV.
VDDQ = 1.7 V; VOUT = 280 mV. VOUT/IOL must be less than 21 ohm for values of VOUT between 0 V and 280 mV.
The dc value of VREF applied to the receiving device is set to VTT
The values of IOH(dc) and IOL(dc) are based on the conditions given in Notes 1 and 2. They are used to test device drive current
capability to ensure VIH min plus a noise margin and VIL max minus a noise margin are delivered to an SSTL_18 receiver. The
actual current values are derived by shifting the desired driver operating point (see Section 3.3) along a 21 ohm load line to define
a convenient driver current for measurement.
3.3.3 OCD defalut characteristics
Description
Parameter
Output impedance
Output impedance step size for OCD calibration
Nom
18
0
Pull-up and pull-down mismatch
Output slew rate
Min
12.6
0
Sout
1.5
-
Max
Unit
Notes
23.4
ohms
1,2
1.5
ohms
6
4
ohms
1,2,3
5
V/ns
1,4,5,6,7,8
Note 1: Absolute Specifications (0°C ≤ TCASE ≤ +tbd°C; VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V)
Note 2: Impedance measurement condition for output source dc current: VDDQ = 1.7V; VOUT = 1420mV;
(VOUT-VDDQ)/Ioh must be less than 23.4 ohms for values of VOUT between VDDQ and VDDQ-280mV.
Impedance measurement condition for output sink dc current: VDDQ = 1.7V; VOUT = 280mV; VOUT/Iol must be less
than 23.4 ohms for values of VOUT between 0V and 280mV.
Note 3: Mismatch is absolute value between pull-up and pull-dn, both are measured at same temperature and voltage.
Note 4: Slew rate measured from vil(ac) to vih(ac).
Rev. 1.2 / Dec 2006
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Note 5: The absolute value of the slew rate as measured from DC to DC is equal to or greater than the slew rate as
measured from AC to AC. This is guaranteed by design and characterization.
Note 6: This represents the step size when the OCD is near 18 ohms at nominal conditions across all process corners/variations and represents only the DRAM uncertainty. A 0 ohm value(no calibration) can only be achieved if the
OCD impedance is 18 ohms +/- 0.75 ohms under nominal conditions.
Output Slew rate load:
VTT
25 ohms
Output
(Vout)
Reference
point
Note 7: DRAM output slew rate specification applies to 400MT/s & 533MT/s speed bins.
Note 8: Timing skew due to DRAM output slew rate mis-match between DQS / DQS and associated DQs is included in
tDQSQ and tQHS specification.
Rev. 1.2 / Dec 2006
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3.4 IDD Specifications & Test Conditions
IDD Specifications(max)
DDR2 400
DDR2 533
DDR2 667
x4/x8
x4/x8
x4/x8
IDD0
100
110
120
mA
IDD1
110
120
130
mA
IDD2P
6
6
7
mA
IDD2Q
40
50
60
mA
IDD2N
45
55
65
mA
F
25
30
35
mA
S
7
8
9
mA
IDD3N
60
70
80
mA
IDD4W
160
190
240
mA
IDD4R
130
170
230
mA
IDD5
270
270
270
mA
Normal
8
8
8
mA
Low power
5
5
5
mA
280
320
340
mA
Symbol
Units
IDD3P
IDD6
IDD7
Rev. 1.2 / Dec 2006
15
1HY5PS1G431(L)F
1HY5PS1G831(L)F
IDD Test Conditions
(IDD values are for full operating range of Voltage and Temperature, Notes 1-5)
Symbol
Conditions
Units
IDD0
Operating one bank active-precharge current; tCK = tCK(IDD), tRC = tRC(IDD), tRAS = tRAS min(IDD) ;
CKE is HIGH, CS is HIGH between valid commands;Address bus inputs are SWITCHING;Data bus inputs are
SWITCHING
mA
IDD1
Operating one bank active-read-precharge curren ; IOUT = 0mA;BL = 4, CL = CL(IDD), AL = 0;
tCK = tCK(IDD), tRC = tRC (IDD), tRAS = tRASmin(IDD), tRCD = tRCD(IDD) ; CKE is HIGH, CS is HIGH
between valid commands ; Address bus inputs are SWITCHING ; Data pattern is same as IDD4W
mA
IDD2P
Precharge power-down current ; All banks idle ; tCK = tCK(IDD) ; CKE is LOW ; Other control and address
bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2Q
Precharge quiet standby current;All banks idle; tCK = tCK(IDD);CKE is HIGH, CS is HIGH; Other control and
address bus inputs are STABLE; Data bus inputs are FLOATING
mA
IDD2N
Precharge standby current; All banks idle; tCK = tCK(IDD); CKE is HIGH, CS is HIGH; Other control and
address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD3P
Active power-down current; All banks open; tCK = tCK(IDD); CKE is
LOW; Other control and address bus inputs are STABLE; Data bus inputs
are FLOATING
Fast PDN Exit MRS(12) = 0
mA
Slow PDN Exit MRS(12) = 1
mA
IDD3N
Active standby current; All banks open; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP =tRP(IDD); CKE is
HIGH, CS is HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus
inputs are SWITCHING
mA
IDD4W
Operating burst write current; All banks open, Continuous burst writes; BL = 4, CL = CL(IDD), AL = 0; tCK =
tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands;
Address bus inputs are SWITCHING; Data bus inputs are SWITCHING
mA
IDD4R
Operating burst read current; All banks open, Continuous burst reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL
= 0; tCK = tCK(IDD), tRAS = tRASmax(IDD), tRP = tRP(IDD); CKE is HIGH, CS is HIGH between valid commands; Address bus inputs are SWITCHING;; Data pattern is same as IDD4W
mA
IDD5B
Burst refresh current; tCK = tCK(IDD); Refresh command at every tRFC(IDD) interval; CKE is HIGH, CS is
HIGH between valid commands; Other control and address bus inputs are SWITCHING; Data bus inputs are
SWITCHING
mA
IDD6
Self refresh current; CK and CK at 0V; CKE ≤ 0.2V; Other control and address bus inputs are FLOATING; Data
bus inputs are FLOATING
mA
IDD7
Operating bank interleave read current; All bank interleaving reads, IOUT = 0mA; BL = 4, CL = CL(IDD), AL =
tRCD(IDD)-1*tCK(IDD); tCK = tCK(IDD), tRC = tRC(IDD), tRRD = tRRD(IDD), tRCD = 1*tCK(IDD); CKE is
HIGH, CS is HIGH between valid commands; Address bus inputs are STABLE during DESELECTs; Data pattern is same as IDD4R; - Refer to the following page for detailed timing conditions
mA
Note:
1. IDD specifications are tested after the device is properly initialized
2. Input slew rate is specified by AC Parametric Test Condition
3. IDD parameters are specified with ODT disabled.
4. Data bus consists of DQ, DM, DQS, DQS, RDQS, RDQS, LDQS, LDQS, UDQS, and UDQS. IDD values must be met with all combinations of EMRS bits 10 and 11.
5. Definitions for IDD
LOW is defined as Vin ≤ VILAC(max)
HIGH is defined as Vin ≥ VIHAC(min)
STABLE is defined as inputs stable at a HIGH or LOW level
FLOATING is defined as inputs at VREF = VDDQ/2
SWITCHING is defined as:
inputs changing between HIGH and LOW every other clock cycle (once per two clocks) for address and control signals, and
inputs changing between HIGH and LOW every other data transfer (once per clock) for DQ signals not including masks or strobes.
Rev. 1.2 / Dec 2006
16
1HY5PS1G431(L)F
1HY5PS1G831(L)F
For purposes of IDD testing, the following parameters are to be utilized
DDR2-667
DDR2-533
DDR2-400
Parameter
5-5-5
4-4-4
3-3-3
Units
CL(IDD)
5
4
3
tCK
tRCD(IDD)
15
15
15
ns
tRC(IDD)
60
60
55
ns
tRRD(IDD)-x4/x8
7.5
7.5
7.5
ns
tRRD(IDD)-x16
9
10
10
ns
tCK(IDD)
3
3.75
5
ns
tRASmin(IDD)
45
45
40
ns
tRASmax(IDD)
70000
70000
70000
ns
tRP(IDD)
15
15
15
ns
tRFC(IDD)-256Mb
75
75
75
ns
tRFC(IDD)-512Mb
105
105
105
ns
tRFC(IDD)-1Gb
127.5
127.5
127.5
ns
tRFC(IDD)-2Gb
197.5
197.5
197.5
ns
Detailed IDD7
The detailed timings are shown below for IDD7. Changes will be required if timing parameter changes are made to the specification.
Legend: A = Active; RA = Read with Autoprecharge; D = Deselect
IDD7: Operating Current: All Bank Interleave Read operation
All banks are being interleaved at minimum tRC(IDD) without violating tRRD(IDD) using a burst length of 4. Control and address bus
inputs are STABLE during DESELECTs. IOUT = 0mA
Timing Patterns for 4 bank devices x4/ x8/ x16
-DDR2-400 4/4/4: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D D
-DDR2-400 3/3/3: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D D D
-DDR2-533 5/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
-DDR2-533 4/4/4: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D D D
Timing Patterns for 8 bank devices x4/8
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 A4 RA4 A5 RA5 A6 RA6 A7 RA7
-DDR2-533 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
Timing Patterns for 8 bank devices x16
-DDR2-400 all bins: A0 RA0 A1 RA1 A2 RA2 A3 RA3 D D A4 RA4 A5 RA5 A6 RA6 A7 RA7 D D
-DDR2-533 all bins: A0 RA0 D A1 RA1 D A2 RA2 D A3 RA3 D D D A4 RA4 D A5 D A6 RA6 D A7 RA7 D D D
Rev. 1.2 / Dec 2006
17
1HY5PS1G431(L)F
1HY5PS1G831(L)F
3.5. Input/Output Capacitance
Parameter
DDR2 400
DDR2 533
Symbol
DDR2 667
DDR2 800
Units
Min
Max
Min
Max
1.0
2.0
1.0
2.0
pF
x
0.25
x
0.25
pF
1.0
2.0
1.0
2.0
pF
Input capacitance, CK and CK
CCK
Input capacitance delta, CK and CK
CDCK
Input capacitance, all other input-only pins
CI
Input capacitance delta, all other input-only pins
CDI
x
0.25
x
0.25
pF
Input/output capacitance, DQ, DM, DQS, DQS
CIO
2.5
4.0
2.5
3.5
pF
Input/output capacitance delta, DQ, DM, DQS, DQS
CDIO
x
0.5
x
0.5
pF
4. Electrical Characteristics & AC Timing Specification
( 0 ℃ ≤ TCASE ≤ 95℃; VDDQ = 1.8 V +/- 0.1V; VDD = 1.8V +/- 0.1V)
Refresh Parameters by Device Density
Parameter
Symbol
Refresh to Active/Refresh command
time
tRFC
Average periodic refresh interval
256Mb 512Mb
1Gb
2Gb
4Gb
Units
75
105
127.5
195
327.5
ns
0 ℃≤ TCASE ≤ 95℃
7.8
7.8
7.8
7.8
7.8
ns
85℃＜ TCASE ≤ 95℃
3.9
3.9
3.9
3.9
3.9
ns
tREFI
DDR2 SDRAM speed bins and tRCD, tRP and tRC for corresponding bin
Speed
DDR2-667
DDR2-533
DDR2-400
Units
Bin(CL-tRCD-tRP)
5-5-5
4-4-4
3-3-3
Parameter
min
min
min
CAS Latency
5
4
3
tCK
tRCD
15
15
15
ns
tRPNote1
15
15
15
ns
tRAS
45
45
40
ns
tRC
60
60
55
ns
Note 1: 8 bank device Precharge All Allowance : tRP for a Precharge All command for and 8 Bank device
will equal to tRP+1*tCK, where tRP are the values for a single bank prechrarge, which are shown in the
above table.
Rev. 1.2 / Dec 2006
18
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Timing Parameters by Speed Grade
DDR2-400
Parameter
DDR2-533
Symbol
Unit
min
max
min
max
Note
DQ output access time from CK/CK
tAC
-600
+600
-500
+500
ps
DQS output access time from CK/CK
tDQSCK
-500
+500
-450
+450
ps
CK high-level width
tCH
0.45
0.55
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
0.45
0.55
tCK
tHP
min(tCL,
tCH)
-
min(tCL,
tCH)
-
ps
11,12
Clock cycle time, CL=x
tCK
5000
8000
3750
8000
ps
15
DQ and DM input setup time
tDS
150
-
100
-
ps
6,7,8,20
DQ and DM input hold time
tDH
275
-
225
-
ps
6,7,8,21
Control & Address input pulse width for each input
tIPW
0.6
-
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
-
tAC max
ps
18
DQS low-impedance time from CK/CK
tLZ
(DQS)
tAC min
tAC max
tAC min
tAC max
ps
18
DQ low-impedance time from CK/CK
tLZ
(DQ)
2*tAC min
tAC max
2*tAC min
tAC max
ps
18
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
350
-
300
ps
13
DQ hold skew factor
tQHS
-
450
-
400
ps
12
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
tHP - tQHS
-
ps
Write command to first DQS latching transition
tDQSS
WL - 0.25
WL + 0.25
WL - 0.25
WL + 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
2
-
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
-
0.35
-
tCK
Address and control input setup time
tIS
350
-
250
-
ps
5,7,9,23
Address and control input hold time
tIH
475
-
375
-
ps
5,7,9,23
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command period for 1KB page size
products
tRRD
7.5
-
7.5
-
ns
4
Active to active command period for 2KB page size
products
tRRD
10
-
10
-
ns
4
Four Active Window for 1KB page size products
tFAW
37.5
-
37.5
-
ns
CK half period
Rev. 1.2 / Dec 2006
10
19
1HY5PS1G431(L)F
1HY5PS1G831(L)F
-Continued
DDR2-400
Parameter
DDR2-533
Symbol
Unit
min
max
min
max
-
50
-
Note
Four Active Window for 2KB page size products
tFAW
50
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
15
-
ns
Auto precharge write recovery + precharge time
tDAL
WR+tRP*
-
WR+tRP*
-
tCK
14
Internal write to read command delay
tWTR
10
-
7.5
-
ns
24
Internal read to precharge command delay
tRTP
7.5
7.5
ns
3
Exit self refresh to a non-read command
tXSNR
tRFC + 10
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
200
-
tCK
Exit precharge power down to any non-read
command
tXP
2
-
2
-
tCK
Exit active power down to read command
tXARD
2
2
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
6 - AL
tCK
1, 2
t
CKE
3
3
tCK
AOND
2
CKE minimum pulse width
(high and low pulse width)
t
ODT turn-on delay
2
2
tCK
ns
tAON
tAC(min)
tAC(max)+1
tAC(min)
tAONPD
tAC(min)+2
2tCK+tAC(
max)
+1
tAC(min)+2
2tCK+tAC(
max)+1
ns
tAOFD
2.5
2.5
2.5
2.5
tCK
tAOF
tAC(min)
tAC(max)+
0.6
tAC(min)
tAC(max)+
0.6
ns
AOFPD
tAC(min)+2
2.5tCK+tAC
(max)+1
tAC(min)+2
2.5tCK+tA
C(max)+1
ns
ODT turn-off delay
ODT turn-off
ODT turn-off (Power-Down mode)
2
tCK
tAC(max)+
1
ODT turn-on
ODT turn-on(Power-Down mode)
2
t
ODT to power down entry latency
tANPD
3
3
tCK
ODT power down exit latency
tAXPD
8
8
tCK
OCD drive mode output delay
tOIT
0
tDelay
tIS+tCK+tIH
Minimum time clocks remains ON after CKE
asynchronously drops LOW
Rev. 1.2 / Dec 2006
12
0
tIS+tCK+tIH
12
16
17
ns
ns
15
20
1HY5PS1G431(L)F
1HY5PS1G831(L)F
DDR2-667
Parameter
Symbol
Unit
min
max
Note
DQ output access time from CK/CK
tAC
-450
+450
ps
DQS output access time from CK/CK
tDQSCK
-400
+400
ps
CK high-level width
tCH
0.45
0.55
tCK
CK low-level width
tCL
0.45
0.55
tCK
CK half period
tHP
min(tCL,
tCH)
-
ps
11,12
Clock cycle time, CL=x
tCK
3000
8000
ps
15
DQ and DM input setup time
tDS
50
-
ps
6,7,8,20
DQ and DM input hold time
tDH
175
-
ps
6,7,8,21
Control & Address input pulse width for each input
tIPW
0.6
-
tCK
DQ and DM input pulse width for each input
tDIPW
0.35
-
tCK
Data-out high-impedance time from CK/CK
tHZ
-
tAC max
ps
18
DQS low-impedance time from CK/CK
tLZ
(DQS)
tAC min
tAC max
ps
18
DQ low-impedance time from CK/CK
tLZ
(DQ)
2*tAC min
tAC max
ps
18
DQS-DQ skew for DQS and associated DQ signals
tDQSQ
-
240
ps
13
DQ hold skew factor
tQHS
-
340
ps
12
DQ/DQS output hold time from DQS
tQH
tHP - tQHS
-
ps
Write command to first DQS latching transition
tDQSS
WL - 0.25
WL + 0.25
tCK
DQS input high pulse width
tDQSH
0.35
-
tCK
DQS input low pulse width
tDQSL
0.35
-
tCK
DQS falling edge to CK setup time
tDSS
0.2
-
tCK
DQS falling edge hold time from CK
tDSH
0.2
-
tCK
Mode register set command cycle time
tMRD
2
-
tCK
Write postamble
tWPST
0.4
0.6
tCK
-
tCK
preamble , tRC(min) specification for DDR2-400 4-4-4
tWPRE
0.35
* Write
: tRAS(min)
is 45ns, 60ns respectively.
10
Address and control input setup time
tIS
150
-
ps
5,7,9,22
Address and control input hold time
tIH
275
-
ps
5,7,9,23
Read preamble
tRPRE
0.9
1.1
tCK
19
Read postamble
tRPST
0.4
0.6
tCK
19
Activate to precharge command
tRAS
45
70000
ns
3
Active to active command period for 1KB page size products
tRRD
7.5
-
ns
4
Active to active command period for 2KB page size products
tRRD
10
-
ns
4
Four Active Window for 1KB page size products
tFAW
37.5
-
ns
Rev. 1.2 / Dec 2006
21
1HY5PS1G431(L)F
1HY5PS1G831(L)F
-Continued
DDR2-667
Symbol
Parameter
Unit
min
max
-
Note
Four Active Window for 2KB page size products
tFAW
50
CAS to CAS command delay
tCCD
2
Write recovery time
tWR
15
-
ns
Auto precharge write recovery + precharge time
tDAL
WR+tRP
-
tCK
Internal write to read command delay
tWTR
7.5
-
ns
Internal read to precharge command delay
tRTP
7.5
ns
Exit self refresh to a non-read command
tXSNR
tRFC + 10
ns
Exit self refresh to a read command
tXSRD
200
-
tCK
Exit precharge power down to any non-read command
tXP
2
-
tCK
Exit active power down to read command
tXARD
2
tCK
1
Exit active power down to read command
(Slow exit, Lower power)
tXARDS
6 - AL
tCK
1, 2
CKE minimum pulse width
(high and low pulse width)
t
CKE
3
ODT turn-on delay
tAOND
2
2
tCK
ODT turn-on
tAON
tAC(min)
tAC(max)+0.7
ns
ODT turn-on(Power-Down mode)
t
AONPD
tAC(min)+2
2tCK+tAC(max)
+1
ns
ODT turn-off delay
t
AOFD
2.5
2.5
tCK
ODT turn-off
t
AOF
tAC(min)
tAC(max)+ 0.6
ns
ODT turn-off (Power-Down mode)
tAOFPD
tAC(min)+2
2.5tCK+tAC(ma
x)+1
ns
ODT to power down entry latency
tANPD
3
tCK
ODT power down exit latency
tAXPD
8
tCK
OCD drive mode output delay
tOIT
0
Minimum time clocks remains ON after CKE asynchronously
drops LOW
tDelay
Rev. 1.2 / Dec 2006
tIS+tCK+tIH
ns
tCK
14
3
tCK
12
6,16
17
ns
ns
15
22
1HY5PS1G431(L)F
1HY5PS1G831(L)F
General notes, which may apply for all AC parameters
1. Slew Rate Measurement Levels
a. Output slew rate for falling and rising edges is measured between VTT - 250 mV and VTT + 250 mV for
single ended signals. For differential signals (e.g. DQS - DQS) output slew rate is measured between
DQS - DQS = -500 mV and DQS - DQS = +500mV. Output slew rate is guaranteed by design, but is not
necessarily tested on each device.
b. Input slew rate for single ended signals is measured from dc-level to ac-level: from VREF - 125 mV to
VREF + 250 mV for rising edges and from VREF + 125 mV and VREF - 250 mV for falling edges.
For differential signals (e.g. CK - CK) slew rate for rising edges is measured from CK - CK = -250 mV to
(250mV to -500 mV for falling egdes).
CK - CK = +500 mV
c. VID is the magnitude of the difference between the input voltage on CK and the input voltage on CK, or
between DQS and DQS for differential strobe.
2. DDR2 SDRAM AC timing reference load
The following figure represents the timing reference load used in defining the relevant timing parameters of
the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation
tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics).
VDDQ
DUT
DQ
DQS
DQS
RDQS
RDQS
Output
Timing
reference
point
VTT = VDDQ/2
25Ω
AC Timing Reference Load
The output timing reference voltage level for single ended signals is the crosspoint with VTT. The output timing reference voltage level for differential signals is the crosspoint of the true (e.g. DQS) and the complement
(e.g. DQS) signal.
3. DDR2 SDRAM output slew rate test load
Output slew rate is characterized under the test conditions as shown below.
VDDQ
DUT
DQ
DQS, DQS
RDQS, RDQS
Output
Test point
VTT = VDDQ/2
25Ω
Slew Rate Test Load
4. Differential data strobe
DDR2 SDRAM pin timings are specified for either single ended mode or differential mode depending on the
setting of the EMRS “Enable DQS” mode bit; timing advantages of differential mode are realized in system
design. The method by which the DDR2 SDRAM pin timings are measured is mode dependent. In single
Rev. 1.2 / Dec 2006
23
1HY5PS1G431(L)F
1HY5PS1G831(L)F
VREF. In differential mode, these timing relationships are measured relative to the crosspoint of DQS and
its complement, DQS. This distinction in timing methods is guaranteed by design and characterization.
Note that when differential data strobe mode is disabled via the EMRS, the complementary pin, DQS, must
be tied externally to VSS through a 20 ohm to 10 K ohm resistor to insure proper operation.
tDQSH
DQS
DQS/
DQS
tDQSL
DQS
tWPRE
tWPST
VIH(dc)
VIH(ac)
DQ
D
D
VIL(ac)
VIL(dc)
tDS
VIH(ac)
tDS
DM
D
D
DMin
DMin
tDH
DMin
tDH
VIH(dc)
DMin
VIL(ac)
VIL(dc)
Figure -- Data input (write) timing
tCH
tCL
CK
CK/CK
CK
DQS
DQS/DQS
DQS
tRPRE
tRPST
DQ
Q
Q
tDQSQmax
Q
Q
tDQSQmax
tQH
tQH
Figure -- Data output (read) timing
5. AC timings are for linear signal transitions. See System Derating for other signal transitions.
6. These parameters guarantee device behavior, but they are not necessarily tested on each device. They
may be guaranteed by device design or tester correlation.
7. All voltages referenced to VSS.
8. Tests for AC timing, IDD, and electrical (AC and DC) characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full
voltage range specified.
Rev. 1.2 / Dec 2006
24
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Specific Notes for dedicated AC parameters
1. User can choose which active power down exit timing to use via MRS(bit 12). tXARD is expected to be
used for fast active power down exit timing. tXARDS is expected to be used for slow active power down
exit timing where a lower power value is defined by each vendor data sheet.
2. AL = Additive Latency
3. This is a minimum requirement. Minimum read to precharge timing is AL + BL/2 providing the tRTP and
tRAS(min) have been satisfied.
4. A minimum of two clocks (2 * tCK) is required irrespective of operating frequency
5. Timings are guaranteed with command/address input slew rate of 1.0 V/ns. See System Derating for
other slew rate values.
6. Timings are guaranteed with data, mask, and (DQS/RDQS in singled ended mode) input slew rate of 1.0
V/ns. See System Derating for other slew rate values.
7. Timings are guaranteed with CK/CK differential slew rate of 2.0 V/ns. Timings are guaranteed for DQS
signals with a differential slew rate of 2.0 V/ns in differential strobe mode and a slew rate of 1V/ns in single
ended mode. See System Derating for other slew rate values.
8. tDS and tDH derating
tDS, tDH Derating Values(ALL units in 'ps', Note 1 applies to entire Table)
DQS, DQS Differential Slew Rate
4.0 V/ns
2.0
DQ
Slew
rate
V/ns
3.0 V/ns
2.0 V/ns
1.8 V/ns
1.6 V/ns
1.4 V/ns
1.2 V/ns
1.0 V/ns
0.8 V/ns
△tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD △tD
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
S
H
125 45 125 45 +125 +45
-
1.5
83
21
83
21
1.0
0
0
0
0
0.9
-
-
-11
-14
0.8
-
-
-
-
0.7
-
-
-
-
0.6
-
-
-
0.5
-
-
-
0.4
-
-
-
+83
+21
95
33
-
-
-
-
-
-
-
-
-
-
0
0
12
12
24
24
-
-
-
-
-
-
-
-
-11
-14
1
-2
13
10
25
22
-
-
-
-
-
-
-25
-31
-13
-19
-1
-7
11
5
23
17
-
-
-
-
-43
-54
-31
-42
-42
-19
-7
-8
5
-6
17
6
-
-
-
-67
-83
-
-
-43
-59
-31
-47
-19
-35
-7
-23
5
-11
-
-110 -125
-
-
-
-
-74
-89
-62
-77
-50
-65
-38
-53
-
-175 -188
-
-
-
-
-
-
-127 -140 -115 -128 -103 -116
1) For all input signals the total tDS(setup time) and tDH(hold time) required is calculated by adding the datasheet value to the derating
value listed in Table x.
Setup(tDS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of VREF(dc) and the first crossing
of Vih(ac)min. Setup(tDS) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of VREF(dc) and
the first crossing of Vil(ac)max. If the actual signal is always earlier than the nominal slew rate line between shaded ‘ VREF(dc) to ac
region’, use nominal slew rate for derating value(see Fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac level to dc level is used for
derating value(see Fig b.)
Hold(tDH) nominal slew rate for a rising signal is defined as the slew rate rate between the last crossing of Vil(dc) max and the first
crossing of VREF(dc). Hold (tDH) nominal slew rate for a falling signal is defined as the slew rate between the last crossing of Vih(dc)
min and the first crossing of VREF(dc). If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is used for derating value(see
Fig d.)
Although for slow slew rates the total setup time might be negative(i.e. a valid input signal will not have reached VIH/IL(ac) at the time
of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rate in between the values listed in table x, the derating valued may obtained by linear interpolation.
Rev. 1.2 / Dec 2006
25
1HY5PS1G431(L)F
1HY5PS1G831(L)F
These values are typically not subject to production test. They are verified by design and characterization.
Fig. a Illustration of nominal slew rate for tIS,tDS
CK,DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
nominal
slew rate
VREF(dc)
nominal
slew rate
VIL(dc)max
VREF to ac
region
VIL(ac)max
Vss
Delta TF
Setup Slew Rate
=
Falling Signal
Rev. 1.2 / Dec 2006
VREF(dc)-VIL(ac)max
Delta TF
Delta TR
Setup Slew Rate
=
Rising Signal
VIH(ac)min-VREF(dc)
Delta TR
26
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Fig. -b Illustration of tangent line for tIS,tDS
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
nominal
line
VIH(ac)min
VIH(dc)min
tangent
line
VREF(dc)
Tangent
line
VIL(dc)max
VREF to ac
region
VIL(ac)max
Nomial
line
Vss
Delta TR
Delta TF
Setup Slew Rate Tangent line[VIH(ac)min-VREF(dc)]
=
Rising Signal
Delta TR
Setup Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Falling Signal
Delta TF
Rev. 1.2 / Dec 2006
27
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Fig. -c Illustration of nominal line for tIH, tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
VIH(dc)min
dc to VREF
region
VREF(dc)
nominal
slew rate
nominal
slew rate
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Hold Slew Rate
=
Rising Signal
Rev. 1.2 / Dec 2006
VREF(dc)-VIL(dc)max
Delta TR
Delta TF
VIH(dc)min - VREF(dc)
Hold Slew Rate
=
Falling Signal
Delta TF
28
1HY5PS1G431(L)F
1HY5PS1G831(L)F
Fig. -d Illustration of tangent line for tIH , tDH
CK, DQS
CK, DQS
tIS,
tDS
tIH,
tDH
tIS,
tDS
tIH,
tDH
VDDQ
VIH(ac)min
nominal
line
VIH(dc)min
tangent
line
VREF(dc)
dc to VREF
region
Tangent
line
nominal
line
VIL(dc)max
VIL(ac)max
Vss
Delta TR
Delta TF
Hold Slew Rate Tangent line[VREF(dc)-VIL(ac)max]
=
Rising Signal
Delta TR
Tangent line[VIH(ac)min-VREF(dc)]
Hold Slew Rate
=
Falling Signal
Delta TF
Rev. 1.2 / Dec 2006
29
1HY5PS1G431(L)F
1HY5PS1G831(L)F
9. tIS and tIH (input setup and hold) derating
tIS, tIH Derating Values
CK, CK Differential Slew Rate
1.5 V/ns
2.0 V/ns
1.0 V/ns
△ tIS
△tIH
△tIS
△tIH
△tIS
△ tIH
Units
Notes
4.0
+187
+94
TBD
TBD
TBD
TBD
ps
1
3.5
+179
+89
TBD
TBD
TBD
TBD
ps
1
3.0
+167
+83
TBD
TBD
TBD
TBD
ps
1
2.5
+150
+75
TBD
TBD
TBD
TBD
ps
1
2.0
+125
+45
TBD
TBD
TBD
TBD
ps
1
1.5
+83
+21
TBD
TBD
TBD
TBD
ps
1
1.0
+0
0
TBD
TBD
TBD
TBD
ps
1
0.9
-11
-14
TBD
TBD
TBD
TBD
ps
1
-25
-31
TBD
TBD
TBD
TBD
ps
1
-43
-54
TBD
TBD
TBD
TBD
ps
1
-67
-83
TBD
TBD
TBD
TBD
ps
1
0.5
-100
-125
TBD
TBD
TBD
TBD
ps
1
0.4
-150
-188
TBD
TBD
TBD
TBD
ps
1
Command /
0.8
Address
Slew
0.7
rate(V/ns) 0.6
0.3
-223
-292
TBD
TBD
TBD
TBD
ps
1
0.25
-250
-375
TBD
TBD
TBD
TBD
ps
1
0.2
-500
-500
TBD
TBD
TBD
TBD
ps
1
0.15
-750
-708
TBD
TBD
TBD
TBD
ps
1
0.1
-1250
-1125
TBD
TBD
TBD
TBD
ps
1
1) For all input signals the total tIS(setup time) and tIH(hold) time) required is calculated by adding the
datasheet value to the derating value listed in above Table.
Setup(tIS) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VREF(dc) and the first crossing of VIH(ac)min. Setup(tIS) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc) and the first crossing of VIL(ac)max. If the actual signal
is always earlier than the nominal slew rate for line between shaded ‘VREF(dc) to ac region’, use nominal
slew rate for derating value(see fig a.) If the actual signal is later than the nominal slew rate line anywhere
between shaded ‘VREF(dc) to ac region’, the slew rate of a tangent line to the actual signal from the ac
level to dc level is used for derating value(see Fig b.)
Hold(tIH) nominal slew rate for a rising signal is defined as the slew rate between the last crossing of
VIL(dc)max and the first crossing of VREF(dc). Hold(tIH) nominal slew rate for a falling signal is defined as
the slew rate between the last crossing of VREF(dc). If the actual signal signal is always later than the nominal slew rate line between shaded ‘dc to VREF(dc) region’, use nominal slew rate for derating value(see
Fig.c) If the actual signal is earlier than the nominal slew rate line anywhere between shaded ‘dc to
VREF(dc) region’, the slew rate of a tangent line to the actual signal from the dc level to VREF(dc) level is
used for derating value(see Fig d.)
Although for slow rates the total setup time might be negative(i.e. a valid input signal will not have reached
VIH/IL(ac) at the time of the rising clock transition) a valid input signal is still required to complete the transition and reach VIH/IL(ac).
For slew rates in between the values listed in table, the derating values may obtained by linear interpolation.
Rev. 1.2 / Dec 2006
30
1HY5PS1G431(L)F
1HY5PS1G831(L)F
These values are typically not subject to production test. They are verified by design and characterization.
10. The maximum limit for this parameter is not a device limit. The device will operate with a greater value
for this parameter, but system performance (bus turnaround) will degrade accordingly.
11. MIN ( t CL, t CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for t CL and t CH).
For example, t CL and t CH are = 50% of the period, less the half period jitter ( t JIT(HP)) of the clock
source, and less the half period jitter due to crosstalk ( t JIT(crosstalk)) into the clock traces.
12. t QH = t HP – t QHS, where:
tHP = minimum half clock period for any given cycle and is defined by clock high or clock low ( tCH,
tCL).
tQHS accounts for:
1) The pulse duration distortion of on-chip clock circuits; and
2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the
next transition, both of which are, separately, due to data pin skew and output pattern effects, and
pchannel to n-channel variation of the output drivers.
13. tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of
the output drivers as well as output slew rate mismatch between DQS/ DQS and associated DQ in any
given cycle.
14. t DAL = (nWR) + ( tRP/tCK):
For each of the terms above, if not already an integer, round to the next highest integer. tCK refers to the
application clock period. nWR refers to the t WR parameter stored in the MRS.
Example: For DDR533 at t CK = 3.75 ns with t WR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns)
clocks =4 +(4)clocks=8clocks.
15. The clock frequency is allowed to change during self–refresh mode or precharge power-down mode. In
case of clock frequency change during precharge power-down, a specific procedure is required as
described in section 2.9.
16. ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn
on.
ODT turn on time max is when the ODT resistance is fully on. Both are measured from tAOND.
17. ODT turn off time min is when the device starts to turn off ODT resistance.
ODT turn off time max is when the bus is in high impedance. Both are measured from tAOFD.
18. tHZ and tLZ transitions occur in the same access time as valid data transitions. Thesed parameters are
referenced to a specific voltage level which specifies when the device output is no longer driving(tHZ), or
begins driving (tLZ). Below figure shows a method to calculate the point when device is no longer driving
(tHZ), or begins driving (tLZ) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the calculation is consistenet.
19. tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when
the device output is no longer driving (tRPST), or begins driving (tRPRE). Below figure shows a method to
calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE). Below FigRev. 1.2 / Dec 2006
31
1HY5PS1G431(L)F
1HY5PS1G831(L)F
ure shows a method to calculate these points when the device is no longer driving (tRPST), or begins driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are
not critical as long as the calculation is consistent.
VOH + xmV
VTT + 2xmV
VOH + 2xmV
VTT + xmV
tHZ
tRPST end point
tHZ
tRPRE begin point
VOL + 1xmV
VTT -xmV
VOL + 2xmV
VTT - 2xmV
tHZ , tRPST end point = 2*T1-T2
tLZ , tRPRE begin point = 2*T1-T2
20. Input waveform timing with differential data strobe enabled MR[bit10] =0, is referenced from the input
signal crossing at the VIH(ac) level to the differential data strobe crosspoint for a rising signal, and from the
input signal crossing at the VIL(ac) level to the differential data strobe crosspoint for a falling signal applied
to the device under test.
21. Input waveform timing with differential data strobe enabled MR[bit10]=0, is referenced from the input
signal crossing at the VIH(dc) level to the differential data strobe crosspoint for a rising signal and VIL(dc) to
the differential data strobe crosspoint for a falling signal applied to the device under test.
Differential Input waveform timing
DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(ac)min
VIH(dc)min
VREF(dc)
VIL(dc)max
VIL(ac)max
VSS
22. Input waveform timing is referenced from the input signal crossing at the VIH(ac) level for a rising signal
and VIL(ac) for a falling signal applied to the device under test.
23. Input waveform timing is referenced from the input signal crossing at the VIL(dc) level for a rising signal
and VIH(dc) for a falling signal applied to the device under test.
Rev. 1.2 / Dec 2006
32
1HY5PS1G431(L)F
1HY5PS1G831(L)F
5. Package Dimensions
Package Dimension(x4,x8)
68Ball Fine Pitch Ball Grid Array Outline
11.9 +/- 0.10
20.9 +/-0.10
A1 Ball Mark
< Top View>
1.20 Max.
N P
L M
A B C D E F
G H
J K
0.80
0.80 X 18 = 14.40
R T
U
V W
0.34 +/- 0.10
A1 Ball Mark
1 2 3
7 8 9
0.80
84 - Φ.50
0.80 X 8 = 6.40
< Bottom View>
Rev. 1.2 / Dec 2006
Note: All dimensions are in Millimeters.
33