INNOVASIC IA88C00


Innovasic Semiconductor
IA88C00
Microcontroller
Data Sheet
Copyright  2005
IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Data Sheet Contents
Please Note.....................................................................................................................................................4
Features ..........................................................................................................................................................4
General Description .......................................................................................................................................4
Architecture..................................................................................................................................................13
Pin Descriptions ...........................................................................................................................................13
Registers.......................................................................................................................................................14
Working Register Window ......................................................................................................................15
Register List .............................................................................................................................................17
Mode and Control Registers ........................................................................................................................20
Instruction Summary....................................................................................................................................45
Opcode Map .................................................................................................................................................52
Instructions...................................................................................................................................................53
Interrupts ......................................................................................................................................................56
Interrupt Programming Model .................................................................................................................58
Functional Overview................................................................................................................................58
Stack Operation............................................................................................................................................58
Counter/Timers ............................................................................................................................................59
WDT.............................................................................................................................................................59
Stop Mode ....................................................................................................................................................59
Halt Mode ....................................................................................................................................................60
I/O Ports .......................................................................................................................................................61
Port 0 ........................................................................................................................................................61
Port 1 ........................................................................................................................................................61
Port 2 and 3 ..............................................................................................................................................62
Port 4 ........................................................................................................................................................62
UART...........................................................................................................................................................62
Pins...........................................................................................................................................................63
Transmitter ...............................................................................................................................................63
Receiver....................................................................................................................................................63
Address Space ..........................................................................................................................................64
CPU Program Memory ............................................................................................................................64
CPU Data Memory...................................................................................................................................64
Absolute Maximum Ratings ........................................................................................................................66
Standard Test Conditions .............................................................................................................................66
Figure 63. Standard Test Load .............................................................................................................................66
DC Characteristics .......................................................................................................................................67
Input Handshake.......................................................................................................................................73
Output Handshake....................................................................................................................................74
EPROM Read Cycle ................................................................................................................................75
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Wait Timing .................................................................................................................................................75
De-Multiplexed Bus Timing .......................................................................................................................76
Package Information ....................................................................................................................................77
Ordering Information ...................................................................................................................................80
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Please Note
Included under Ordering Information on page 68 are enhanced RoHS-compliant versions of the IA88C00.
However, standard packaged or non RoHS-compliant versions of the IA88C00 microcontroller are still
available.
Features
•
•
•
•
•
•
•
•
•
•
Fully Form, Fit and Function Compatible with the Super8 (Z88C00)
Available in 48-, and 68-pin packages
Fully Compatible with the Super8 Instruction Set
Rich Program Register Set
128 Kbytes external program address space
Built-in Direct Memory Access (DMA)
Two Programmable 16-bit counter/timers with 8-bit prescalers
Up to 32 General Purpose I/O Lines including special handshake funtionality
Robust Interrupt structure
Watch-Dog Timer
General Description
The IA88COO is a form, fit and function replacement for the original Zilog Z88C00 microcontroller.
Innovasic Semiconductor produces replacement ICs using its MILESTM, or Managed IC Lifetime
Extension System, cloning technology. This technology produces replacement ICs far more complex than
"emulation" while ensuring they are compatible with the original IC. MILESTM captures the design of a
clone so it can be produced even as silicon technology advances. MILESTM also verifies the clone against
the original IC so that even the "undocumented features" are duplicated.
This Data Sheet documents all necessary engineering information about the IA88COO including
functional and I/O descriptions, electrical characteristics, and applicable timing.
The function block diagram of the IA88C00 is shown in Figure 1. The device is available in a 48-pin DIP
(Figure 2) and a 68-pin PLCC package (Figure 3). The pin functions of the IA88COO are outlined in
Figure 6. Pin Functions.
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IA88C00
Microcontroller
DEMUX
R//W
/RESET
/AS
/DS
I/O
(BIT PROGRAMMABLE)
XTAL2
XTAL1
Data Sheet
As of Production Version -01
MACHINE
TIMING
PORT 4
CPU
INSTRUCTION
DECODE
UART
COUNTERS/
TIMERS (2)
SYSTEM
REGISTERS
(PC)
(INSTRUCTION
POINTER)
WATCHDOG
TIMER
REGISTER FILE
ALU
CONTROL
REGISTERS
DMA
INTERRUPT
CONTROL
PORT 3
PORT 2
PORT 0
PORT 1
8
I/O (BIT PROGRAMMABLE)
OR CONTROL (IRQ, TIMER, UART)
ADDRESS OR
I/O (BIT PROGRAMMABLE)
ADDRESS OR
I/O (BYTE PROGRAMMABLE)
Figure 1. Functional Block Diagram
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
P10
P11
P12
P13
P14
P15
P16
P17
P24
P25
+5V
XTAL2
XTAL1
P44
P45
P46
P47
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
IA88C00
DIP
48
47
46
45
44
43
P00
P01
P02
P03
P04
P05
42
41
40
39
38
37
36
35
34
33
32
P06
P07
P34
P35
/AS
/DS
P40
P41
GND
P42
P43
R/W
P22
P32
18
19
31
30
P33
P23
P20
P21
20
21
22
23
29
28
27
26
P31
24
25
/RESET
P36
P37
P27
P26
P30
Figure 2. 48-Lead DIP Package
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Figure 3. 48-Lead DIP Pin Assignments
Pin #
1-8
9-10
11
12
13
14-17
18
19-20
21-23
24-25
26-27
28-29
30
31
32-33
34
35-36
37
38
39-40
41-48
Symbol
P10-17
P24-25
Vcc
XTAL2
XTAL1
P44-47
P22
P32-21
P23-21
P31-30
P26-27
P37-36
/RESET
R/W
P43-42
GND
P41-40
/DS
/AS
P35-34
P07-00
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Function
Port 1, pins 0,1,3,4,5,6,7
Port 2, pins 4,5
Power Supply
Crystal Oscillator
Crystal Oscillator
Port 4, pins 4,5,6,7
Port 2, pin 2
Port 2, pins 2,3
Port 2, pins 3,0,1
Port 3, pins 1,0
Port 2, pins 6,7
Port 3, pins 7,6
RESET
READ/WRITE
Port 4, pins 3,2
Ground
Port 4, pins 1,0
Data Strobe
Address Strobe
Port 3, pins 5,4
Port 0, pins 7,6,5,4,3,2,1,0
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Direction
In/Output
In/Output
Input
Output
Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
Input/Output
In/Output
Input
Output
In/Output
Input
In/Output
Output
Output
In/Output
In/Output
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IA88C00
Microcontroller
NC
NC
P15
P14
P13
P12
P11
P10
NC
GND
P00
P01
P02
P03
P04
P05
NC
Data Sheet
As of Production Version -01
9
1
01
8
7 6
5
4
3
2
1
6
8
6
7
6
6
6
5
6
4
6
3
6
2
6
1
6
05
11
12
95
58
31
41
75
65
51
16
55
54
IA88C00
(Top View)
71
18
35
52
92
02
15
04
21
22
49
84
32
42
74
64
2
7
2
8
2 3
9 0
3
1
3
2
3
3
3
4
3
5
3
6
3
7
3
8
3
9
4
0
4
1
4
2
54
4 4
3
NC
NC
VCC
P06
P07
P34
P35
/AS
/DS
P40
P41
GND
GND
P42
P43
R/W
NC
P30
P26
P27
P37
P36
RESET
NC
52
6
NC
P22
NC
P32
P33
P23
P20
P21
P31
NC
NC
VCC
De-MUX
P16
P17
P24
P25
VCC
GND
VCC
XTAL2
VTAL1
P44
P45
P46
P47
NC
Figure 4. 68-Lead PLCC Package
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Figure 5. 68-Lead PLCC-Pin Assignments
Pin #
1
2-7
8-10
11
12
13-14
15-16
17
18
19
20
21
22-25
26-27
28
29
30-31
32-34
35
36
37
38-39
40-41
42
43-44
45
46-47
48-49
50-51
52
53
54-55
56-57
58
59-61
62-65
66
Symbol
NC
P10-15
NC
Vcc
De-Mux
P16-17
P24-25
Vcc
GND
Vcc
XTAL2
XTAL1
P44-47
NC
P22
NC
P32-33
P23-21
P31
NC
P30
P26-27
P37-36
/RESET
NC
R//W
P43-42
GND
P41-40
/DS
/AS
P43-42
P07-06
Vcc
NC
P05-02
GND
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Function
Note Connected
Port 1, pins 0,1,2,3,4,5
Not Connected
Power Supply
De-multiplex Pin
Port 1, pins 6,7
Port 2, pins 4,5
Power Supply
Ground
Power Supply
Crystal Oscillator
Crystal Oscillator
Port 4, points 4,5,6,7
Not Connected
Port 2, pin 2
Not Connected
Port 3, pins 2,3
Port 2, pins 3,0,1
Port 3, pin 1
Not Connected
Port 3, pin 0
Port 2, pins 6,7
Port 3, pins 7,6
RESET
Not Connected
READ/WRITE
Port 4, pins 3,2
Ground
Port 4, pins 1,0
Data Strobe
Address Strobe
Port 3, pins 5,4,3,2
Port 0, pins 7,6
Power Supply
Not Connected
Port 0, pins 5,4,3,2
Ground
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Direction
In/Output
Input
Input
In/Output
In/Output
Input
Input
Input
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
In/Output
Input
Output
In/Output
Input
In/Output
Output
Output
In/Output
In/Output
Input
In/Output
Input
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IA88C00
Microcontroller
67
68
NC
GND
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Data Sheet
As of Production Version -01
Not Connected
Ground
Input/Output
Input
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
30
Timing
and
Control
31
37
38
48
47
46
Port 0
45
44
43
42
41
1
2
3
4
5
Port 1
6
7
8
36
35
Port 4
(1/2)
33
32
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/RESET
+5V
11
34
R//W
/DS
/AS
GND
13
XTAL1
XTAL2 12
P00
P20
P01
P21
P02
P22
P03
P23
P04
P24
P05
P25
P06
P26
P07
P27
P10
P30
P11
P31
P12
P32
P13
P33
Clock
22
22
23
18
21
IA88C00
Power
Port 2
9
10
26
27
25
24
19
20
P14
P34
P15
P35
Port 3
40
39
P16
P36
29
P17
P37
P14
P44
P15
P45
P16
P46
P17
P47
28
14
16
17
Port 4
(1/2)
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Figure 6. Pin Functions
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Architecture
IA88C00 maintains program model compatibility with the Super8 architecture, including 268 general
purpose registers and 57 registers for control and mode functions.
The instruction set, is also fully binary compatible supporting all instructions, including multiply and
divide instructions and provisions for BCD operations.
The peripheral set maintains register/ program model compatibility. Robust serial communications are
provided by an on-board UART. Counter/timers are provided for time-sensitive/control loop
applications. A watchdog timer is provided for processor sanity.
Pin Descriptions
/AS Address Strobe
(output, active Low)
The rising edge of this output indicates that address, R/W, and DM (when
appropriate) are valid.
/DS Data Strobe
(output, active Low
The leading edge of this signal indicates that data is valid during a write cycle.
The trailing edge of this signal is used to latch data into the IA88C00 during a
read cycle.
P00-P07, P10-P17,
P20-P27, P30-P37,
P40-P47, Port I/O
Lines (input/output)
Input/Output Ports configured under program control. Specific functions include:
Port 1 serves as the multiplexed address/data port. It serves as the data bus
de-multiplexed mode, and Port 0 pins can be used as additional address
lines or general purpose I/O.
Ports 2 and 3 provide support for interrupts, the UART and the timers.
Alternatively, they can be programmed as general purpose I/O.
Port 4 is used for general I/O or as the lower address byte in de-mux mode.
/RESET (input,
active Low)
R/W Read/Write
(output)
Reset input. Reset vector is address 0020H.
When high, the current bus operation is a read. When low, the current bus
operation is a write.
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IA88C00
Microcontroller
XTAL1, XTAL2
(Crystal oscillator
input)
Data Sheet
As of Production Version -01
Crystal inputs for the internal oscillator.
All port pins are configured as inputs (high impedance) during RESET, except for Port 1 and Port 0. Port
1 is configured as a multiplexed address/ data bus. Port 0 pins P00-P04 are configured as address out. And
pins P05-P07 are configured as inputs.
Registers
The IA88C00 supports a 256-byte register address space. Addresses 00H-BFH contain two sets of
registers. Set one contains control registers that are only accessible by register direct commands. Set two
contains data registers that are only available via register indirect, indexed, stack and DMA commands,
Note that address space E0H to FFH in Set one is further divided into two banks. The state of bank select
bit in the Flag register determines which bank is accessed.
The register space is shown in Figure 7.
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Set One
Set Two
FFH
FFH
Bank 1
Mode and Control Registers
(Register Addressing Only)
EOH
DFH
DOH
CFH
COH
Bank 0
Data Registers
(Indirect Register, Indexed,
STACK or DMA Access Only)
System Register:
STACK, FLAGS, PORTS, etc.
(Register Addressing Only)
Working Register
(Working Register
Addressing Only)
COH
256 Bytes
CFH
Data Registers
(All Addressing Modes)
192 Bytes
OOH
Figure 7. IA88C00Registers
Working Register Window
Working registers are those registers found within a moveable 8-register section of the register space.
These moveable 8-register sections are defined by register pointers RP0 and RP1, which are control
registers R214 and R215.
Short 4-bit addresses are used to access working registers. The process of accessing working registers,
shown in a section of Figure 7, occurs as follows:
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IA88C00
Microcontroller
1.
2.
3.
Data Sheet
As of Production Version -01
High order bit of the 4-bit address selects one of the two register pointers (0 selects RP0; 1 selects RP1).
Live high order bits in the register pointer select an 8-register (contiguous) slice of the register space.
Three low order bits of the 4-bit address select one of the eight registers in the slice.
The process results in linking together the five bits from the register pointer to the three bits from the
address to form an 8-bit address. The three bits from the address will always point to an address within
the same eight registers, as long as the address in the register pointer remains unchanged.
Changing the five high bits in control registers R214 for RP9 and R215 for RP1 allows the register
pointers to be moved.
Using full 8-bit addressing allows the working registers to be accessed. The lower nibble is used similarly
to the 4-bit addressing described above when an 8-bit logical address in the range 192 to 207 (C0 to CF)
is specified. This is shown in section b. of Figure 8.
Selects RP0
or RP1
Address
RP0 (R214)
RP0 (R214)
RP1 (R215)
RP1 (R215)
Selects RP0
or RP1
Opcode
Address
8-Bit
Logical
Address
4-Bit Address Provides Three Low-Order Bits
Three LowOrder Bits
Register Pointer Provides
Five High-Order Bits
Register Pointer Provides
Five High-Order Bits
1
Together They Create 8-Bit Register Address
1
0
0
8-Bit Physical Address
b. 8-Bit Addressing
a. 4-Bit Addressing
Figure 8. Working Register Window
Physical registers 192 to 207 can be accessed only when selected by a register pointer. This is because
any direct access to logical addresses 192 to 207 involves the register pointers. After a reset, RP0 points
to R192 and RP1 points to R200.
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Register List
Figure 9 displays the IA88C00registers. For more details, see the registers presented under Mode and
Control Registers.
Figure 9. IA88C00Registers
Address
Decimal
General Purpose Registers
00-192
192-207
192-255
Mode and Control Registers
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
Hexadecimal
Mnemonic
00-BF
00-CF
C0-FF
-
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
P0
P1
P2
P3
P4
FLAGS
RP0
RP1
SPH
SPL
IPH
IPL
IRQ
IMR
SYM
HMR
COCT
COM
C1CT
C1M
COCH
COTCH
COCL
COTCL
C1CH
C1TCH
C1CL
C1TCL
CTPRS
WDTSMR
UTC
225
E1
226
E2
227
E3
228
E4
229
E5
230
230
235
E6
E6
EB
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Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Function
General purpose (all address modes)
Working Register (direct only)
General purpose (indirect only)
Port 0 I/O bits
Port 1 (I/O only)
Port 2
Port 3
Port 4
System Flags Register
Register Pointer 0
Register Pointer 1
Stack Pointer Low Byte
Stack Pointer High Byte
Instruction Pointer High Byte
Instruction Pointer Low Byte
Interrupt Request
Interrupt Mask Register
System Mode Register
Hall Mode Register
CTR 0 Control
CTR 0 Mode
CTR 1 Control
CTR 1 Mode
CTR 0 Capture Register, bits 8-15
CTR 0 Timer Constant, bits 8-15
CTR 0 Capture Register, bits 0-7
CTR 0 Time Constant, bits 0-7
CTR 1 Capture Register, bits 8-15
CTR 1 Time Constant, bits 8-15
CTR 1 Capture Register, bits 0-7
CTR 1 Time Constant, bits 0-7
Counter Prescaler
Watch-Dog/Stop Mode Register
UART Transmit Control
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
236
237
238
239
240
EC
ED
EE
EF
F0
241
F1
244
245
246
247
248
F4
F5
F6
F7
F8
249
F9
250
FA
251
FB
252
253
254
FC
FD
FE
255
FF
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Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 1
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 1
Bank 0
Bank 0
Bank 0
Bank 1
Bank 0
Bank 0
URC
UIE
UTI
UIO
POM
DCH
PM
DCL
H0C
H1C
P4D
P4OD
P2AM
UBGH
P2BM
UBGL
P2CM
UMA
P2DM
UMB
P2AIP
P2BIP
EMT
WUMCH
IPR
WUMSK
UART Receive Control
UART Interrupt Enable
Transmit Interrupt Register
UART Data
Port 0 Mode
DMA Count, bits 8-15
Port Mode Register
DMA Count, bits 0-7
Handshake Channel 0 Control
Handshake Channel 1 Control
Port 4 Direction
Port 4 Open Drain
Port 2/3 A Mode
UART Baud Rate Generator, bits 8-15
Port 2/3 B Mode
UART Baud Rate Generator, bits 0-7
Port 2/3 C Mode
UART Mode A
Port 2/3 D Mode
UART Mode B
Port 2/3 A Interrupt Pending
Port 2/3 B Interrupt Pending
External Memory Timing
Wake-up Match Register
Interrupt Priority Register
Wake-up Mask Register
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Microcontroller
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Data Sheet
As of Production Version -01
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Mode and Control Registers
Figure 10. R213 (D5) Flags System Flags Register
Bit
Initial Value
Read/Write
7
6
5
4
Carry
Zero
Sign
Overflow
?
R
?
R
?
R
?
R
3
Decimal
Adjust
?
R
2
HalfCarry
?
R
1
Fast
Interrupt
?
R
0
Bank
?
R/W
The flag register contains eight bits that describe the current status of the processor. Four of these bits can
be tested and used with conditional jump instructions. Two others are used for BCD arithmetic. Also
contained in the flag register are the Bank Address bit and the Fast Interrupt Status bit.
Bit 7: Carry Flag - This is set to 1 if the result from an arithmetic operation generates carry out of, or
borrow into, bit 7.
Bit 6: Zero Flag - For arithmetic and logical operations, this flag is set to 1 if the result of the operation is
0. For operations that test bits in a register, the 0 bit is set to 1 if the result is 0. For rotate and shift
operations, this bit is set to 1 if the result is 0.
Bit 5: Sign Flag - Following arithmetic, logical, rotate or shift operations, this bit identifies the state of
the MSB of the result. A 0 indicates a positive number and a 1 indicates a negative number.
Bit 4: Overflow Flag - This flag is set to 1 when the result of a two's-complement operation was greater
than 127 or less than -128. It is also cleared to 0 during logical operations.
Bit 3: Decimal Adjust - This bit is used to specify what type of instruction was executed last during BCD
operations, so a subsequent decimal adjust operation can function correctly. This bit is not usually
accessible to programmers and cannot be used as a test condition.
Bit 2: Half-Carry Flag - This bit is set to 1 whenever an addition generates a carry out of bit 3, or when a
subtraction borrows out of bit 4. This bit is used by the Decimal Adjust (DA) instruction to convert the
binary result of a previous addition or subtraction into the correct decimal (BCD) result. This flag and the
Decimal Adjust flag are not usually accessed by users.
Bit 1: Fast Interrupt Status - This bit is set during a fast interrupt cycle and reset during the IRET
following interrupt servicing. When set, this bit inhibits all interrupts and causes the fast interrupt return
to be executed when the IRET instruction is fetched.
Bit 0: Bank Address - This bit is used to select one of the register banks (0 or 1) between (decimal)
addresses 224 and 255. It is cleared by the SB0 instruction and set by the SB1 instruction.
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Figure 11. R214 (D6) RP0 Register Pointer 0
Bit
Initial Value
Read/Write
7
6
5
4
3
RP7
RP6
RP5
RP4
RP3
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
2
Not
Used
-
1
Not
Used
-
0
Not
Used
-
Register Pointer 0 (RP0) defines a moveable, 8-register section of the register space. The registers within
these spaces are called working registers. RP0 is used in addressing modes where the register operand is
expressed as a 4-bit address.
At reset, RP0 points to R192.
Figure 12. R215 (O7) RP1 Register Pointer 1
Bit
Initial Value
Read/Write
7
6
5
4
3
RP7
RP6
RP5
RP4
RP3
?
R/W
?
R/W
?
R/W
?
R/W
?
R/W
2
Not
Used
?
R/W
1
Not
Used
?
R/W
0
Not
Used
?
R/W
Register Pointer 1 (RP1) defines a moveable, 8-register section of the register space. The registers within
these spaces are called working registers. RP1 is used in addressing modes where the register operand is
expressed as a 4-bit address.
At reset, RP0 points to R200.
Figure 13. R216 (D8) SPH Stack Pointer
Bit
Initial Value
Read/Write
7
SP15
6
SP14
5
SP13
4
SP12
3
SP11
2
SP10
1
SP9
0
SP8
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stack operations are supported in the register file or in data memory. Bit 1 in the external Memory Timing
register (R254B0) selects between the two.
Register pair R216-R217 forms the Stack Pointer used for all stack operations. R216 is the MSB and
R217 is the LSB.
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The Stack Pointer always points to data stored on the tip of the stack. The address is decremented prior to
a PUSH and incremented after a POP.
The stack is also used as a return stack for CALLS and interrupts. During a CALL, the contents of the PC
are saved on the stack to be restored later. Interrupts cause the contents of the PC and FLAGS to be saved
on the stack for recovery by IRET when the interrupt is finished.
When configured for internal stack (using the register file), R217 contains the Stack Pointer. R216 can be
used as a general purpose register. However, its contents will be changed if an overflow or underflow
occurs as the result of incrementing or decrementing the stack address during normal stack operations.
A user-defined stack can be implemented in both the register file and program or data memory. These can
be made to increment or decrement on a push by the choice of opcodes. For example, to implement a
stack that goes from Low addresses to High addresses in the register file, use PUSHUI and POPUD. For a
stack that goes from High address to Low addresses in data memory, use LDEI for POP and LDEPD for
PUSH.
Figure 14. R217 (D9) SPL Stack Pointer
Bit
Initial Value
Read/Write
7
SP7
6
SP6
5
SP5
4
SP4
3
SP3
2
SP2
1
SP1
0
SP0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Stack operations are supported in the register file or in data memory. Bit 1 in the external Memory Timing
register (R254B0) selects between the two.
Register pair R216-R217 forms the Stack Pointer used for all stack operations. R216 is the MSB and
R217 is the LSB.
The Stack Pointer always points to data stored on the tip of the stack. The address is decremented prior to
a PUSH and incrementd after a POP.
The Stack is also used as a return stack for CALLS and interrupts. During a CALL, the contents of the PC
are saved on the stack to be restored later. Interrupts cause the contents of the PC and FLAGS to be saved
on the stack for recovery by IRET when the interrupt is finished.
When configured for internal stack (using the register file), R217 contains the Stack Pointer. R216 can be
used as a general purpose register. However, its contents will be changed if an overflow or underflow
occurs as the result of incrementing or decrementing the stack address during normal stack operations.
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A user-defined stack can be implemented in both the register file and program or data memory. These can
be made to increment or decrement on a push by the choice of opcodes. For example, to implement a
stack that goes from Low addresses to High addresses in the register file, use PUSHUI and POPUD. For a
stack that goes from High address to Low addresses in data memory, use LDEI for POP and LDEPD for
PUSH.
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Figure 15. Instruction Pointer High (IPH), R218
Bit
Initial Value
Read/Write
7
IP15
?
R/W
6
IP14
?
R/W
5
IP13
?
R/W
4
IP12
?
R/W
3
IP11
?
R/W
2
IP10
?
R/W
1
IP9
?
R/W
0
IPO8
?
R/W
A special register called the Instruction Pointer (IP) provides hardware support for threaded-code
languages. It consists of register-pair R218-R219 and contains memory addresses. The MSB is R218.
Threaded-code languages deal with an imaginary higher-level machine within the existing hardware
machine. The IP acts like the PC for that machine. The command NEXT passes control to or from the
hardware machine to the imaginary machine. And the commands ENTER and EXIT are imaginary
machine equivalents of real machine CALLS and RETURNS.
If the commands NEXT, ENTER and EXIT are not used, the IP can be used by the fast interrupt
processing, as described in the interrupts section.
Figure 16. Instruction Pointer Low (IPL), R219
Bit
Initial Value
Read/Write
7
IP7
?
R/W
6
IP6
?
R/W
5
IP5
?
R/W
4
IP4
?
R/W
3
IP3
?
R/W
2
IP2
?
R/W
1
IP1
?
R/W
0
IP0
?
R/W
A special register called the Instruction Pointer (IP) provides hardware support for threaded-code
languages. This register consists of register pair R218-R219 and contains memory addresses. The MSB is
R218. Threaded-code languages deal with an imaginary higher-level machine within the existing
hardware machine. The IP acts like the PC for that machine. The command NEXT passes control to or
from the hardware machine to the imaginary machine. And the commands ENTER and EXIT are
imaginary machine equivalents of real machine CALLS and RETURNS.
The IP can be used by the fast interrupt processing, as described in the interrupts section, if the commands
NEXT, ENTER and EXIT are not used.
Figure 17. Interrupt Mask (IRM), R221
Bit
Initial Value
Read/Write
7
Level 7
?
R
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Level 7
?
R
5
Level 7
?
R
4
Level 7
?
R
3
Level 7
?
R
2
Level 7
?
R
1
Level 7
?
R
0
Level 7
?
R
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When an interrupt in one of the 8 levels occurs and the corresponding mask bit is not set, the level bit of
the interrupt is set to 1. The interrupt structure contains 8 levels of interrupt, 16 vectors and 27 sources.
Interrupt priority is assigned by level and controlled by the Interrupt Priority Register (IPR)
ControlRegR255B0. Each level is masked (or enabled) according to the bits in the Interrupt Mask
Register (IMR) SystemRegR221. Each bit of the Interrupt Mask register corresponds to one of the 8
levels of interrupts, IRQ register (SystemRegR220). When the corresponding bit in the Interrupt Mask
register is set to one, that level interrupt is disabled.
Figure 18. System Mode Register (SYM), R222
Bit
Initial Value
Read/Write
7
Not
Used
?
R/W
6
Not
Used
?
R/W
5
Not
Used
?
R/W
4
3
2
1
0
FIS2
FSI1
FSI0
FSE
GIE
?
R/W
?
R/W
?
R/W
?
R/W
?
R/W
The Fast Interrupt Select (FSI) selects which level interrupt can be treated as a fast interrupt. Fast
Interrupt Enable (FSE), when set to 1, enables the selected level for fast interrupt. Global Interrupt Enable
(GIE), when set to 1, enables interrupts in general.
Figure 19. Halt Mode Register (HMR), R223
Bit
Initial Value
Read/Write
7
Not
Used
?
R/W
6
Not
Used
?
R/W
5
Not
Used
?
R/W
4
Not
Used
?
R/W
3
2
1
0
D3
D2
D1
D0
1
R/W
1
R/W
1
R/W
1
R/W
D3 - CPU HALT mode - Writing a zero to this bit will invoke the HALT mode upon the execution of the
WFI instruction. The UART and counters can be halted only if D3 is 0. During HALT the internal CPU
clock is disabled, and no address strobe is generated. A hardware reset sets this bit to a 1.
D2 - Disable UART - Writing a zero to the bit will disable the UART. No interrupt request will be
generated. A 1 will make the UART and its interrupt logic remain active in HALT mode. A hardware
reset forces this bit to a 1.
D1 - Disable CT1 - Similar to CT0. When the counters are cascaded, the HALT mode 32-bit counter is
determined by the logical state of D1. A hardware reset forces this bit to a 1.
D0 - Disable CT0 - Writing a zero to this bit will disable the CT0 in HALT mode. No interrupt request
will be generated in this case. A 1 will keep the CT0 active. A hardware reset forces this bit to a 1.
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Figure 20. Counter 0 Control Register (C0CT), R224 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
0
R/W
0
D0
0
R/W
D0 - When this bit is set to 1, the counter/timer is enabled. Operation begins on the rising edge of the first
processor clock period following the setting of this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the operation of the counter/timer. When this bit is
cleared to 0, the counter/timer performs no operation during the next (and subsequent) processor clock
periods. A hardware reset forces this bit to 0.
Both counters are clocked by the rising edge of the incoming signal on P26 or p36 after the counter is
enabled. The maximum frequency of the external clock signal applied to P36 (or P26) equals the
maximum Xtal frequency divided by 4. The maximum gauaranteed Xtal frequency is 20 MHz, which
implies a maximum counter frequency of 5 MHz.
D1 - Reset/End of Count Status - This bit is set to 1 each time the counter reaches 0. Writing a 1 to this
bit resets it, while writing a 0 has no effect.
D2 - Zero Count Interrupt Enable - When this bit is set to 1, the counter/timer generates an interrupt
request when it counts to 0. A hardware reset forces this bit to 0.
D3 - Software Capture - When this bit is set to 1, the current counter value is loaded into the capture
register. This bit is automatically cleared following the capture.
D4 - Software Trigger - This bit is effectively "ORed" with the external rising-edge trigger input and can
be used by the software to force a trigger signal. This bit produces a trigger signal regardless of the setting
of the Input Pin Assignment field of the Mode register. This bit is automatically cleared following the
trigger.
D5 - Load Counter - The contents of the Time Constant register are transferred to the Counter prescaler
one clock period after this bit is set. This operation alone does not start the counter. This bit is
automatically cleared following the load.
D6 - Count Up/Down - This bit determines the count direction if internal up/down control is specified in
the Mode register. 1 indicates up; 0 indicates down.
D7 - Continuous/Single Cycle - When this bit is set to 1, the counter is reloaded with the time-constant
value when the counter reaches the end of the terminal count. The terminal count for down counting is
0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
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Figure 21. Counter 0 Mode, R224
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
0
R/W
0
D0
0
R/W
D0 - When this bit is set to 1, the counter/timer is enabled. Operation begins on the rising edge of the first
processor clock period following the setting of this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the operation of the counter/timer. When this bit is
cleared to 0, the counter/timer performs no operation during the next (and subsequent) processor clock
periods. A hardware reset forces this bit to 0.
Both counters are clocked by the rising edge of the incoming signal on P26 or p36 after the counter is
enabled. The maximum frequency of the external clock signal applied to P36 (or P26) equals the
maximum Xtal frequency divided by 4. The maximum gauaranteed Xtal frequency is 20 MHz, which
implies a maximum counter frequency of 5 MHz.
D1 - Reset/End of Count Status - This bit is set to 1 each time the counter reaches 0. Writing a 1 to this
bit resets it, while writing a 0 has no effect.
D2 - Zero Count Interrupt Enable - When this bit is set to 1, the counter/timer generates an interrupt
request when it counts to 0. A hardware reset forces this bit to 0.
D3 - Software Capture - When this bit is set to 1, the current counter value is loaded into the capture
register. This bit is automatically cleared following the capture.
D4 - Software Trigger - This bit is effectively "ORed" with the external rising-edge trigger input and can
be used by the software to force a trigger signal. This bit produces a trigger signal regardless of the setting
of the Input Pin Assignment field of the Mode register. This bit is automatically cleared following the
trigger.
D5 - Load Counter - The contents of the Time Constant register are transferred to the Counter prescaler
one clock period after this bit is set. This operation alone does not start the counter. This bit is
automatically cleared following the load.
D6 - Count Up/Down - This bit determines the count direction if internal up/down control is specified in
the Mode register. 1 indicates up; 0 indicates down.
D7 - Continuous/Single Cycle - When this bit is set to 1, the counter is reloaded with the time-constant
value when the counter reaches the end of the terminal count. The terminal count for down counting is
0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
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Figure 22. Counter 0 Mode, R225
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
0
R/W
0
D0
0
R/W
D0 - When this bit is set to 1, the counter/timer is enabled. Operation begins on the rising edge of the first
processor clock period following the setting of this bit from a previously cleared value. Writing a 1 in this
field when the previous value was 1 has no effect on the operation of the counter/timer. When this bit is
cleared to 0, the counter/timer performs no operation during the next (and subsequent) processor clock
periods. A hardware reset forces this bit to 0.
Both counters are clocked by the rising edge of the incoming signal on P26 or p36 after the counter is
enabled. The maximum frequency of the external clock signal applied to P36(or P26) equals the
maximum Xtal frequency divided by 4. The maximum gauaranteed Xtal frequency is 20 MHz, which
implies a maximum counter frequency of 5 MHz.
D1 - Reset/End of Count Status - This bit is set to 1 each time the counter reaches 0. Writing a 1 to this
bit resets it, while writing a 0 has no effect.
D2 - Zero Count Interrupt Enable - When this bit is set to 1, the counter/timer generates an interrupt
request when it counts to 0. A hardware reset forces this bit to 0.
D3 - Software Capture - When this bit is set to 1, the current counter value is loaded into the capture
register. This bit is automatically cleared following the capture.
D4 - Software Trigger - This bit is effectively "ORed" with the external rising-edge trigger input and can
be used by the software to force a trigger signal. This bit produces a trigger signal regardless of the setting
of the Input Pin Assignment field of the Mode register. This bit is automatically cleared following the
trigger.
D5 - Load Counter - The contents of the Time Constant register are transferred to the Counter prescaler
one clock period after this bit is set. This operation alone does not start the Counter. This bit is
automatically cleared following the load.
D6 - Count Up/Down - This bit determines the count direction if internal up/down control is specified in
the Mode register. 1 indicates up; 0 indicates down.
D7 - Continuous/Single Cycle - When this bit is set to 1 the counter is reloaded with the time-constant
value when the counter reaches the end of the terminal count. The terminal count for down counting is
0000, while the one for up counting is FFFF. When this bit is cleared to 0, no reloading occurs.
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Figure 23. Counter 0 Capture Register (High Byte) (C0CH), R226 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
X
R/W
4
D4
X
R/W
3
D3
X
R/W
2
D2
X
R/W
1
D1
X
R/W
0
D0
X
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 24. Counter 0 Capture Register (Low Byte) (C0CL), R227 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
X
R/W
4
D4
X
R/W
3
D3
X
R/W
2
D2
X
R/W
1
D1
X
R/W
0
D0
X
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 25. Counter 1 Time Constant Register (High Byte) (C1CTH), R228 Bank 1
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
X
R/W
4
D4
X
R/W
3
D3
X
R/W
2
D2
X
R/W
1
D1
X
R/W
0
D0
X
R/W
This 16-bit register pair holds the value that is automatically loaded into the counter/timer (1) when the
counter/timer is enabled, (2) when the count reaches zero in continuous mode or (3) when the trigger is
asserted in re-trigger mode. If capture on both edges is enabled, this register captures the contents of the
counter on the falling edge of the I/O pin.
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Figure 26. Counter 1 Capture Register (Low Byte) (C1CL), R229 Bank 0
Bit
7
D7
6
D6
5
D5
Initial Value
Read/Write
X
R/W
X
R/W
X
R/W
4
3
D4
D3
C1C7 – C1C0
X
X
R/W
R/W
2
D2
1
D1
0
D0
X
R/W
X
R/W
X
R/W
This 16-bit register pair is used to hold the counter value saved when using the "capture on external
event" function. This register will capture at the rising edge of the I/O pin or when software capture is
asserted. When the bi-value mode of operation is enabled, this register is used as a second Time Constant
register and the counter is alternately loaded from each.
Figure 27a. Counter 0 Prescaler (CTPRS), R230 Bank 0
Bit
7
D7
Initial Value
Read/Write
0
R/W
6
D6
CT1
0
R/W
5
D5
1
R/W
4
3
D4
D3
Not Used
0
0
R/W
R/W
2
D2
0
R/W
1
D1
CT0
0
R/W
0
D0
1
R/W
This register controls the source of the timer signal when in internal mode. An 8-bit prescaler for each
counter is implemented. The control bit operate as follows:
CT0/CT1
000
001
010
011
100
101
110
111
Prescale
XTAL/2
XTAL/4
XTAL/8
XTAL/16
XTAL/32
XTAL/64
XTAL/128
XTAL/256
Only the prescaler of CT1 is activated when the counters are cascaded.
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Figure 28b. Watch Dog Timer and Stop Mode Recovery Register (WDT/SMR) R230 Bank0
Bit
7
D7
6
D6
WDT time-out
Initial Value
Read/Write
0
R/W
0
R/W
5
D5
WDT
Enable
0
R/W
4
D4
WDT in
Stop
0
R/W
3
D3
WDT
Source
0
R/W
2
D2
SMR
On
0
R/W
1
D1
0
D0
SMR Source
0
R/W
0
R/W
This register controls the Watchdog Timer time-out and Stop recovery mode.
D1, D0 Stop Mode Recovery source select.
Bit D0 and D1 determine the Stop Mode Recovery source.
D1
0
0
1
1
D0
0
1
0
1
Recovery from RESET only
Recovery from P22 and RESET
Recovery from P32 and RESET
Recovery from any input for Port 4 and RESET
A hardware reset forces D0 and D1 to zero.
D2 Stop Recovery Edge
A 1 in this position indicates that a rising edge on any one of the recovery sources wakes the IA88C00
from Stop mode. A 0 indicates falling edge recovery. The reset value is 0.
D3 XTAL1/RC Select for WDT
When a zero is written to D3, the clock of the WDT is driven by the on-board RC oscillator. If D3 is set to
1, the WDT is driven by XTAL1. D3 has a zero reset value.
D4 WDT Enable During STOP or HALT
When this bit is set, WDT is enabled during STOP or HALT. In this case, recovery from STOP or HALT
should be performed before the selected time-out. A 0 in this bit location disables the WDT while the
IA88C00 is stopped or halted. A hardware reset forces this bit to a zero.
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D5 WDT
The Watch-Dog Timer is initially enabled by writing a 1 to D5 and retriggered on subsequent writings to
the same bit. Reset value = 0. Writing a 0 to this bit has no effect. Once a 1 is written to D5, it persists
until a hardware reset occurs.
D6, D7 WDT Time-Out
Two sets of four different time-out values can be selected, depending on the logical state of these bits.
A normal reset signal must be active low during 5 XTAL clock periods. Using the reset signal input to
recover from STOP mode requires 10 XTAL clock periods. This is so that XTAL oscillation starts up and
stabilizes, generating a good oscillator output level.
The reset pin is held low in source during WDT timer time-out to accomplish a system reset with other
peripherals of the Super8. When the reset pin is held low, the capability of sink current via the reset pin
should be considered. (See DC Characteristics.)
Figure 29. UART Transmit Control (UTC), R235 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
1
R/W
0
D0
0
R/W
This register cont ains the status and command bits needed to control the transmit sections of the UART.
0 - TDMAENB - Transmit DMA Enable - When this bit is set to 1, the DMA function for the UART
transmit section is enabled. If this bit is set and the Transmit Buffer Empty signal becomes true, a DMA
request is made. When the DMA channel gains control of the bus, it transfers bytes from the external
memory or the register file to the UART transmit section. A hardware reset forces this bit to 0.
D1 - TBE - Transmit Buffer Empty - This status bit is set to 1 whenever the transmit buffer is empty. It
is cleared to 0 when a data byte is written in the transmit buffer. A hardware reset forces this bit to 1.
D2 - ZC - Zero Count - This status bit is set to 1 and latched when the counter in the baud-rate generator
reaches the count of 0. This bit can be cleared to 0 by writing a 1 to this bit position. A hardware reset
forces this bit to 0.
D3 - TENB - Transmit Enable - Data is not transmitted until this bit is set to 1. When cleared to 0, the
Transmit Data pin continuously outputs 1s unless Auto-Echo mode is selected. This bit should be cleared
only after the desired transmission of data in the buffer is completed. A hardware reset forces this bit to 0.
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D4 - WUEB - Wake-up Enable - If this bit is set to 1, wake-up mode is enabled for both the transmitter
and the receiver. The transmitter adds a bit beyond those specified by the bits/character and the parity.
This added bit has the value specified in the Transmit Wake-up Value (TWUVAL) in the UMA register
(ControlRegR250B0). The reveiver expects a Wake-Up bit value in the incoming data stream after the
parity bit and compares this value with that specified in the Received Wake-Up value (RWVAL) bit in the
UMA register. The resulting action depends on the configuration of the Wake-up feature.
D5 - STPBTS - Stop Bits - This bit determines the number of stop bits added to each character
transmitted from the UART transmit section. If this bit is a 0, one stop bit is added. If this bit is a 1, two
stop bits are added. The receiver always checks for at least one stop bit. A hardware reset forces this bit to
0.
D6 - SENBRK - Send Break - When set to 1, this bit forces the transmit section to continuously output
0s, beginning with the following transmit clock, regardless of any data being transmitted at the time. This
bit functions whether or not the transmitter is enabled. When this bit is cleared to 0, the transmit section
continues to send the contents of the Transmit Data Register. A hardware reset forces this bit to 0.
D7 - TXDTSEL - Transmit Data Select - This bit has an effect only if port pin P31 is configured as an
output. If this bit is set to 1, the serial data coming out of the transmit section is reflected on the P31 pin.
If this bit is set to 0, P31 acts as a normal port and P31 data is reflected on the P31 pin. A hardware reset
forces this bit to 0.
Figure 30. UART Receive Control (URC), R236 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
0
R/W
0
D0
0
R
D0 - RCA - Receive Character Available - This is a status bit that is set to a 1 when data is available in
the receive buffer (UIOR). When the CPU reads the receive buffer, it automatically clears this bit to 0. A
write to this possition has not effect. A hardware reset forces this bit to 0.
D1 - RENB - Receive Enable - When this bit is set to 1, the receive operation begins. This bit should be
set only after all other receive parameters are established and the reciver is completely initialized. A
hardware reset clears this bit to 0.
D2 - PERR - Parity Error - This is a status bit. When parity is enabled, this bit is set to 1 and buffered
with the character whose parity does not match the programmed parity (even/odd). This bit is latched so
that once an error occurs, it remains set until it is cleared to 0 by writing a 1 to this bit position.
D3 - OVERR - Overrun Error - This status bit indicates that the receive buffer has not been read and
another character has been received. Only the character that has been written over is flagged with this
error. Once set, this bit remains set until cleared to 0 by writing a 1 to this bit position.
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D4 - FERR - Framing Error - This is a status bit. If a framing error occurs (no stop bit where expected),
this bit is set for the receive character in which the framing error occurred. This bit remains set until
cleared to 0 by writing a 1 to this bit position.
D5 - BRKD - Break Detect - This is a status bit that is set at the beginning and the end of a break
sequence in the receive data stream. It stays set to 1 until cleared to 0 by writing a 1 to this bit position.
A break signal is a sequence of 0s. When all the required bits, parity bit, wake-up bit, and stop bits are 0x,
the receiver immediately recognizes a break condition (not a framing error) and causes Break Detect
(BRKD) to be set and an interrupt request. At the end of the break signal, a zero character is loaded into
the Receive Data Register (UIOR) and Break Detect is set again, along with another interrupt request.
D6 - CCD - Control Character Detect - This status bit is set any time an ASCII control character is
received in the receive data stream. It stays set until cleared to 0 by writing a 1 to this bit position. (An
ASCII control character is any character that has bits 5 and 6 set to 0.)
D7 - WUD - Wake-Up Detect - This status bit is set any time a valid wake-up condition is detected at the
receiver. It stays set until cleared to 0 by writing a 1 to this bit position. The wake-up condition can be
satisfied in many possible ways by the Wake-up bit, Wake-up Match register, and Wake-Up Mask
register.
Figure 31. UART Interrupt Enable (UIE), R237 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
0
R/W
0
D0
0
R/W
D0 - RCAIE - Receive Character Available Interrupt Enable - If this bit is set to 1, a Receive
Character Available status in the URC register will cause an interrupt request. In a DMA receive
operation, if this bit is set to 1, an interrupt request will be issued only if an End-of-Process (EOP) of the
DMA counter is also set. If it is not set, a Receive Character Available status causes no interrupt.
D1 - RDMAENB - Receive DMA Enable - When this bit is set to 1, the DMA function is enabled for the
UART receiver. Whenever a Receive Character Available signal in the URC register is true, a DMA
request will be made. When the DMA channel claims control of the bus, it transfers the received data to
the register file or the external memory.
D2 - TIE - Tranmit Interrupt Enable - If this bit is set to 1, a Transmit Buffer Empty signal in the UTC
register will cause an interrupt request. In a DMA transmit operation, if this bit is set to 1, an interrupt
request will be issued only if an End-of-Process (EOP) of the DMA counter is also set. If it is not set, a
Transmit Buffer Empty signal causes no interrupt.
D3 - ZCIE - Zero Count Interrupt Enable - If this bit is set to 1, a baud-rate generator Zero Count
status in the UTC register will cause an interrupt request.
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D4 - REIE - Receive Error Interrupt Enable - If this bit is set to 1, any receiver error condition will
cause an interrupt request. Possible receive error conditions include parity error, overrun error and
framing error.
D5 - BRKIE - Break Interrupt Enable - If this bit is set to 1, a transition in either direction on the break
signal will cause an interrupt request.
D6 - CCIE - Control Character Interrupt Enable - If this bit is set to 1, an ASCII Control Character
Detect signal in the URC register will cause an interrupt.
D7 - WUIE - Wake-Up Interrupt Enable - If this bit is set to 1, any of the wake-up conditions that set
the Wake-Up Detect bit (WUD) in the URC register will cause an interrupt request.
Figure 32. UART Transmit Interrupt Register, UTI R238 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
1
R/O
0
D0
0
R/W
The timing for the transmit buffer empty interrupt is software programmable. There are two different
interrupt timings selectable with 1 bit.
Option 1: Interrupt is activated at the moment the contents of the TUIO register are transferred to the Tx
FIFO.
Option 2: Interrupt is activated at the moment the last stop bit in the Tx FIFO is sent.
After loading the transmit shift register, UART control generates a buffer empty flag to indicate that
TUIO is ready to be filled with new data.
A new flag will indicate when the transmit shift register is empty.
D0 - If this bit is zero, a high value of D2 in the UIE register will cause an interrupt on Transmit UIO
empty. If this bit is set, a high value of D2 in the UIE register will cause an interrupt on transmit shift
register empty. That is when the last stop bit is transmitted. This bit should be programmed prior to
writing to the UIO register.
D1 - This flag is set when the transmit shift register is empty and is reset when a new value is loaded into
the UIO. This flag will not be set during a send break.
Figure 33. Uart Data Register (UIO), R239 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
R/W
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6
D6
X
R/W
5
D5
X
R/W
4
D4
X
R/W
3
D3
X
R/W
2
D2
X
R/W
1
D1
X
R/O
0
D0
X
R/W
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Writing to this register automatically writes the data in the Transmit Data register (UIOT). A read from
this register gets the data from the UART Receive Data register (UIOR).
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Figure 34. Port 0 Mode Control Register (P0M), R240 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
1
R/W
3
D3
1
R/W
2
D2
1
R/W
1
D1
1
R/W
0
D0
1
R/W
The Port 0 Mode register programs each bit of Port 0 as an address output (part of an external memory
interface) or as an I/O bit. When a bit of this register is 1, the corresponding bit of Port 0 is defined as an
address output. When 0, the corresponding bit of Port 0 is defined as an I/O bit. D0-D7 - P00-P07 Mode,
0 = I/O, 1 = Address.
Figure 35. Port Mode Register (pm), R241 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
?
6
D6
X
?
5
D5
1
?
4
D4
0
?
3
D3
0
?
2
D2
0
?
1
D1
0
?
0
D0
1
?
The Port Mode register provides some additional mode control for Ports 0 and 1.
D0 - Port 0 Direction - If this bit is a 1, all bits of Port 0 configured as I/O will be inputs. If this bit is a 0,
the I/O lines will be outputs.
D1 - Open-Drain Port 0 - If this bit is a 1, all bits of Port 0 configured as outputs will be open-drain
outputs. If 0, they will be push-pull outputs. This bit has no effect on those bits not configured as outputs.
D2 - Open-Drain Port 1 - If Port 1 is configured as an output port and this bit is a 1, all of the port will
be open-drain outputs. If this bit is a 0, they will be push-pull outputs. This bit has no effect if Port 1 is
not configured as an output port or A/D 0-7.
D3 - Enable /DM - If this bit is a 1, Port 35 is configured as Data Memory output line /DM.
D4-D5 - This field selects the configuration of Port 1 as an output port, input port, or address/data port as
part of the external memory interface.
Figure 36. Handshake 0 Control (H0C), R244 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
W/O
6
D6
X
W/O
5
D5
X
W/O
4
D4
X
W/O
3
D3
X
W/O
This register controls Handshake Channel 0.
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2
D2
0
W/O
1
D1
X
W/O
0
D0
0
W/O
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D0 - Handshake Enable - When this bit is set to 1, the handshake function is enabled.
D1 - Port Select - This bit selects which port is controlled by Handshake Channel 0. When it is set to 1,
Port 1 is selected and when it is cleared to 0, Port 4 is selected.
D2 - DMA Enable - When this bit is set to 1, the DMA function is enabled for Handshake Channel 0.
When it is cleared to 0, the DMA function is not used by the handshake channel and may be used by the
UART.
D3 - Mode - When this bit is set to 1, the "fully interlocked" mode is enabled. When it is cleared to 0, the
"strobed" mode is enabled.
D4-D7 - Deskew Counter - This 4-bit field is used to select a count value from 1 to 16 (0000-1111). This
value is the number of processor clocks used to generate the set-up and strobe when using the "strobed"
mode, or the set-up when using the "fully-interlocked" mode.
Figure 37. Handshake 1 Control (H1C), R245 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
W/O
6
D6
X
W/O
5
D5
X
W/O
4
D4
X
W/O
3
D3
X
W/O
2
D2
X
W/O
1
D1
X
W/O
0
D0
0
W/O
This register controls Handshake Channel 1.
D0 - Handshake Enable - When this bit is set to 1, the handshake function is enabled.
D1 - Not Used.
D2 - Not Used.
D3 - Mode - When this bit is set to 1, the "fully interlocked" mode is enabled. When it is cleared to 0, the
"strobed" mode is enabled.
D4-D7 - Deskew Counter - This 4-bit field is used to select a count value from 1 to 16 (0000-1111). This
value is the number of processor clocks used to generate the set-up and strobe when using the "strobed"
mode, or the set-up when using the "fully-interlocked" mode.
Figure 38. Port 4 Direction Control Register (P4D), R246 Bank 0
Bit
Initial Value
Read/Write
7
D7
1
R/W
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6
D6
1
R/W
5
D5
1
R/W
4
D4
1
R/W
3
D3
1
R/W
2
D2
1
R/W
1
D1
1
R/W
0
D0
1
R/W
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The Port 4 Direction register defines the I/O direction of Port 4 on a bit basis. If a bit of this register is a 1,
the corresponding bit of Port 4 is configured as and input line. If the bit is a 0, the corresponding bit of
Port 4 is configured as and output line.
D0-D7 - P40-P47 Mode, 0 = Output, 1 = Input.
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Figure 39. Port 4 Open-Drain (P4OD), R247 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
?
6
D6
0
?
5
D5
0
?
4
D4
0
?
3
D3
0
?
2
D2
0
?
1
D1
0
?
0
D0
0
?
The Port 4 Open-Drain register defines the output driver type for Port 4. If a bit of Port 4 has been
configured as an output and the corresponding bit in the Port 4 Open-Drain register is a 1, the Port 4 bit
will have an open-drain output driver. If it is a 0, the Port 4 bit will have a push-pull output driver. If the
bit of Port 4 has been configured as an input, the corresponding bit is the Port 4 Open-Drain register has
no effect.
Figure 40. Port 4 Open-Drain (P4OD), R247 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
W/O
6
D6
0
W/O
5
D5
0
W/O
4
D4
0
W/O
3
D3
0
W/O
2
D2
0
W/O
1
D1
0
W/O
0
D0
0
W/O
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C Mode and Port 2/3 D Mode registers control the
modes of Ports 2 and 3. A separate 2-bit field for each of the bits of Ports 2 and 3 configures the bit as
input or output. The field also controls whether the bit is enabled as an external interrupt source and
selects the oputpus as open-drain or push-pull.
Figure 41. Port 2/3 A Mode Register, R248 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
W/O
6
D6
0
W/O
5
D5
0
W/O
4
D4
0
W/O
3
D3
0
W/O
2
D2
0
W/O
1
D1
0
W/O
0
D0
0
W/O
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C Mode and Port 2/3 D Mode registers control the
modes of Ports 2 and 3. A separate 2-bit field for each of the bits of Ports 2 and 3 configures the bit as
input or output. The field also controls whether the bit is enabled as an external interrupt source and
selects the oputpus as open-drain or push-pull.
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Figure 42. Port 2/3 B Mode Register, R249 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
W/O
6
D6
0
W/O
5
D5
0
W/O
4
D4
0
W/O
3
D3
0
W/O
2
D2
0
W/O
1
D1
0
W/O
0
D0
0
W/O
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C Mode and Port 2/3 D Mode registers control the
modes of Ports 2 and 3. A separate 2-bit field for each of the bits of Ports 2 and 3 configures the bit as
input or output. The field also controls whether the bit is enabled as an external interrupt source and
selects the oputpus as open-drain or push-pull.
Figure 43. Port 2/3 C Mode Register, R250 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
W/O
6
D6
0
W/O
5
D5
0
W/O
4
D4
0
W/O
3
D3
0
W/O
2
D2
0
W/O
1
D1
0
W/O
0
D0
0
W/O
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C Mode and Port 2/3 D Mode registers control the
modes of Ports 2 and 3. A separate 2-bit field for each of the bits of Ports 2 and 3 configures the bit as
input or output. The field also controls whether the bit is enabled as an external interrupt source and
selects the oputpus as open-drain or push-pull.
Figure 44. Port 2/3 D Mode Register, R251 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
W/O
6
D6
0
W/O
5
D5
0
W/O
4
D4
0
W/O
3
D3
0
W/O
2
D2
0
W/O
1
D1
0
W/O
0
D0
0
W/O
The Port 2/3 A Mode, Port 2/3 B Mode, Port 2/3 C Mode and Port 2/3 D Mode registers control the
modes of Ports 2 and 3. A separate 2-bit field for each of the bits of Ports 2 and 3 configures the bit as
input or output. The field also controls whether the bit is enabled as an external interrupt source and
selects the oputpus as open-drain or push-pull.
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Figure 45. Port 2/3 A Interrupt Pending Register (P2AIP), R252 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
?
6
D6
0
?
5
D5
0
?
4
D4
0
?
3
D3
0
?
2
D2
0
?
1
D1
0
?
0
D0
0
?
Read Only (writeable for reset puposes)
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of
these registers corresponds to an interrupt generated by an external source. When one of these registers is
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0
causes no action.
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as
they are processed. Figure 45 shows the pin relationship.
Figure 46. Port 2/3 B Interrupt Pending Register (P2BIP), R253 Bank 0
Bit
Initial Value
Read/Write
7
D7
0
?
6
D6
0
?
5
D5
0
?
4
D4
0
?
3
D3
0
?
2
D2
0
?
1
D1
0
?
0
D0
0
?
Read Only (writeable for reset puposes)
The Port 2/3 A Interrupt Pending and Port 2/3 B Interrupt Pending registers represent the software
interface to the negative edge-triggered flip-flops associated with external interrupt inputs. Each bit of
these registers corresponds to an interrupt generated by an external source. When one of these registers is
read, the value of each bit represents the state of the corresponding interrupt. When one of these registers
is written to, a 1 in a bit position causes the corresponding edge-triggered flip-flop to be reset to 0. A 0
causes no action.
The software interfaces with these registers to poll the interrupts and also to reset pending interrupts as
they are processed. Figure 46 shows the pin relationship.
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Data Sheet
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Figure 47. External Memory Timing Register, R254 Bank 0
Bit
Initial Value
Read/Write
7
D7
1
R/W
6
D6
0
R/W
5
D5
0
R/W
4
D4
0
R/W
3
D3
0
R/W
2
D2
0
R/W
1
D1
1
R/W
0
D0
1
R/W
This register controls all the extended bus timing features.
D0 - DMA Select - If 0, DMA uses register file space. If 1, it uses Data Memory.
D1 - Stack Select - If 0, stack is located in register file space. If 1, it is located in Data Memory.
Figure 48. Interrupt Priority Register (IPR), R255 Bank 0
Bit
Initial Value
Read/Write
7
D7
X
R/W
6
D6
X
R/W
5
D5
X
R/W
4
D4
X
R/W
3
D3
X
R/W
2
D2
X
R/W
1
D1
X
R/W
0
D0
X
R/W
The Interrupt Priority register defines the priority order of the interrupt levels. Interrupts should be
globally disabled before writing to this register.
D0 - Group A - 0=IRQ0 > IRQ1; 1=IRQ1 > IRQ0.
D2 - Group B - 0=IRQ2>(IRQ3,IRQ4); 1=(IRQ3,IRQ4) > IRQ2.
D3 - Subgroup B - 0=IRQ3>IRQ4; 1=IRQ4>IRQ3.
D5 - Group C - 0=IRQ5>(IRQ6,IRQ7); 1=(IRQ6,IRQ7)>IRQ5.
D6 - Subgroup C - 0=IRQ6>IRQ7; 1=IRQ7>IRQ6.
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IA88C00
Microcontroller
Data Sheet
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Instruction Summary
This section provides a summary of the IA88C00 instructions.
NOTE
Assignment of a value is indicated by the symbol “←”.
For example:
Dst ← dst + src
indicates that the source data is added to the destination data and the result is stored in the destination
location.
The notation “addr (n) ” is used to refer to bit (n) of a given operand location.
For example:
dst (7)
refers to bit 7 of the destination operand.
Figure 49. Instruction Summary
Instruction
and Operation
ADC dst, src
dst←dst + src + C
ADD dst, src
dst←dst + src
ADD dst, src
dst←dst AND src
BAND dst, src
dst←dst AND src
BCP dst, src
dst - src
BITC dst
dst←NOT dst
BITR dst
dst←0
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Address
Mode
dst scr
†
1[ ]
Flags
Affected
C
Z
*
*
S
*
V
-
D
0
H
*
†
0[ ]
*
*
*
*
0
*
†
5[ ]
-
*
*
0
-
-
67
67
17
-
*
0
U
-
-
-
*
0
U
-
-
57
-
*
0
U
-
-
-
-
-
-
-
-
-
r0
Rb
r0
Rb
r0
Rb
rb
rb
77
Opcode
Byte (Hex)
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Instruction
and Operation
BITS dst
dst←0
dst←1
Instruction
and Operation
BOR dst, src
dst←0 OR src
BTJRF
dst←0
if src=0, PC=PC+dst
BTJRT
IF SRC=0, PC=PC+dst
BXOR dst, src
dst←dst XOR src
CALL dst
SP←SP - 2
@SP←PC,
PC←dst
CCF
C←NOT C
CLR dst
dst←0
COM dst
dst←NOT dst
CP dst, src
Dst - src
CPIJE
if dst - src=0, then
PC←PC+RA
Ir←Ir + 1
CPIJNE
if dst - src=0, then
PC←PC+RA
Ir←Ir + 1
DA dst
dst←DA dst
DEC dst
dst←dst - 1
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Data Sheet
As of Production Version -01
Address
Mode
dst scr
rb
77
Opcode
Byte (Hex)
-
Address
Mode
dst scr
r0
rB
RA
S
-
V
-
D
-
H
-
07
Flags
Affected
C
Z
*
S
0
V
U
D
-
H
-
Rb
37
-
-
-
-
-
-
RA
rb
37
-
-
-
-
-
-
r0
Rb
27
-
*
0
U
-
-
F6
F4
D4
-
-
-
-
-
-
EF
*
-
-
-
-
-
B0
B1
60
61
A[ ]
-
-
-
-
-
-
-
*
*
0
-
-
*
*
*
*
-
-
DA
IRR
IA
R
IR
R
IR
†
Opcode
Byte (Hex)
Flags
Affected
C
Z
-
R
Ir
C2
-
-
-
-
-
-
r
Ir
D2
-
-
-
-
-
-
40
41
00
01
*
*
*
U
-
-
-
*
*
*
-
-
R
IR
R
IR
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DECW dst
dst←dst - 1
DI
SMR(0)←0
DIV dst, src
dst÷src
dst (Upper)←
Quotient
dst (Lower)←
Remainder
RR
IR
Instruction
and Operation
Address
Mode
dst scr
RA
r
DJNZ r, dst
r←r - 1
If r = 0
PC←PC + dst
El
SMR(0)
ENTER
SP←SP - 2
@ SP←IP
IP←PC
PC←@ IP
IP←IP + 2
EXIT
IP←@SP
SP←SP + 2
PC←@ IP
IP←IP + 2
INC dst
dst←dst + 1
INCW dst
dst←dst + 1
IRET (Fast)
PC↔IP
FLAG←FLAG
FIS←0
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80
81
8F
RR
RR
R
IR
94
95
RR
IM
96
r
R
IR
RR
IR
Opcode
Byte (Hex)
rA
(r=0 IoF)
-
*
*
*
-
-
-
-
-
-
-
-
*
*
*
*
-
-
Flags
Affected
C
Z
-
S
-
V
-
D
-
H
-
9F
-
-
-
-
-
-
1F
-
-
-
-
-
-
2F
-
-
-
-
-
-
rE
r=0-F
20
21
A0
A1
-
*
*
*
-
-
-
*
*
*
-
-
BF
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Restored to
before
interrupt
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IRET (Normal)
FLAGS←@SP;
SP←SP + 1;
PC←@ SP
SP←SP + 2;
SMR(0) ←1
JP cc, dst
if cc is true
PC←dst
JR cc, dst
if cc is true,
PC←PC + d
LD dst, src
dst←src
Instruction
and Operation
LDB dst, src
dst←src
LDC/LDE
dst←src
LDCD/LDED dst, src
dst←src
rr←rr-1
LDEI/LDCI dst, src
dst←src
rr←rr+1
LDCPD/LDCI dst, src
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BF
DA
IRR
RA
r
r
R
IM
R
Restored to
before
interrupt
ccD
C = 0 to F
30
ccB
cc = 0 to F
-
-
-
-
-
-
-
-
-
-
-
-
rC
r8
r9
r = 0 to F
Opcode
Byte (Hex)
-
-
-
-
-
-
Flags
Affected
C
Z
S
V
D
H
Address
Mode
dst scr
r
IR
IR
r
R
R
R
IR
R
IM
IR
IM
IR
R
r
x
x
r
r0
Rb
Rb
r0
r
lrr
lrr
r
r
xs
xs
r
r
x1
x1
r
r
DA
DA
R
r
lrr
C7
D7
E4
E5
E6
D6
F6
87
97
47
47
C3
D3
E7
F7
A7
B7
A7
B7
E2
r
lrr
r
lrr
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
E3
-
-
-
-
-
-
E3
-
-
-
-
-
-
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dst←src
rr←rr+1
LDCPI/LDEPI dst, src
dst←src
rr←rr+1
LDW dst, src
MULT dst, src
NEXT
PC←@ IP
IP←IP + 2
NOP
OR dst, src
dst←dst OR src
POP dst
dst←@SP;
SP←SP + 1
POPUD dst, src
dst←src
IR←IR - 1
POPUI dst, src
dst←src
IR←IR + 1
Instruction
and Operation
PUSH scr
SP←SP - 1;
@SP←src
PUSHUD dst, src
IR←IR - 1
dst←src
PUSHUI dst, src
IR←IR + 1
dst←src
RCF
C←0
RET
PC←@SP;SP←SP+2
RL dst
C←dst(7)
dst(0)←dst(7)
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r
lrr
E3
-
-
-
-
-
-
RR
RR
RR
RR
IR
IMM
C4
C5
C6
-
-
-
-
-
-
RR
RR
RR
R
IR
IM
84
85
86
0F
*
0
*
*
-
-
-
-
-
-
-
-
FF
4[ ]
-
*
*
0
-
-
R
IR
50
51
-
-
-
-
-
-
R
IR
92
-
-
-
-
-
-
R
IR
93
-
-
-
-
-
-
†
Address
Mode
dst scr
R
IR
70
71
IR
R
IR
R
R
IR
Opcode
Byte (Hex)
Flags
Affected
C
Z
-
S
-
V
-
D
-
H
-
82
-
-
-
-
-
-
83
-
-
-
-
-
-
CF
0
-
-
-
-
-
AF
-
-
-
-
-
-
90
91
*
*
*
*
-
-
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Microcontroller
dst(N+1)←dst(N)
N=0 to 6
RLC dst
dst(0)←C
C←dst(7)
dst(N)←dst(N+1)
N=0 to 6
RR dst
C←dst(0)
dst(7)←C
dst(N)←dst(N+1)
N=0 to 6
SB0
BANK←0
SB1
BANK←1
SBC dst, src
dst←dst - src - C
SCF
C←1
SRA dst
dst(7)←dst(7)
C←dst(0)
dst(N)←dst(N+1)
N=0 to 6
SRP src
RP0←IM
RP1←IM+8
SRP0
RP0←IM
SRP1
RP1←IM
STOP
SUB dst, src
dst←dst - src
SWAP dst
Dst(0-3)↔dst(4-7)
TCM dst, src
(NOT dst) AND src
TM dst, src
dst AMD src
TSW dst, src
WFI
XOR dst, src
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Data Sheet
As of Production Version -01
R
IR
10
11
*
*
*
*
-
-
R
IR
C0
C1
*
*
*
*
-
-
4F
-
-
-
-
-
-
3[ ]
*
*
*
*
1
*
DF
1
-
-
-
-
-
D0
*
*
*
0
-
-
IM
31
-
-
-
-
-
-
IM
31
-
-
-
-
-
-
IM
31
-
-
-
-
-
-
†
6F
2[ ]
*
*
*
*
1
*
R
IR
†
F0
F1
6[ ]
-
*
*
U
-
-
-
*
*
0
-
-
†
7[ ]
-
*
*
0
-
-
7F
3F
B[ ]
U
-
*
*
*
*
0
0
U
-
U
-
5F
†
R
R
†
R
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dst←dst
XOR src
† These instructions have an identical set of addressing modes, which are encoded for brevity. The first opcode nibble is found in the
instruction set table above. The second nibble is expressed symbolically by a ‘[ ]’ in this table. Its value is found in the following table to the
left of the applicable addressing mode pair.
For example, the opcode of an ADC instruction using the addressing modes r (destination) and ir (source) is 13.
Address dst
r
r
R
R
R
Mode src
r
Ir
R
IR
IM
Lower Opcode Nibble
[2]
[3]
[4]
[5]
[6]
Notes:
0 = Cleared to Zero
1 = Set to One
– = Unaffected
* = Set or reset, depending on result of operation.
U = Undefined
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Data Sheet
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Opcode Map
Figure 50. Opcode Map
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
6
DEC
R1
6
RLC
R1
6
INC
R1
10
JP
IRR1
6
DA
R1
10
POP
R1
6
COM
R1
10/12
PUSH
R2
10
DECW
RR1
6
RL
R1
10
INCW
RR1
6
CLR
R1
6
RRC
R1
6
SRA
R1
6
RR
R1
8
SWAP
R1
1
6
DEC
R2
6
RLC
IR1
6
INC
IR1
NOTE
C
6
DA
IR1
6
POP
IR1
6
COM
IR1
10/14
PUSH
IR2
10
DECW
IR1
6
RL
IR1
10
INCW
IR1
6
CLR
IR1
6
RRC
IR1
6
SRA
IR1
2
6
ADD
r 1r 2
6
ADC
r 1r 2
6
SUB
r 1r 2
6
SBC
r 1r 2
6
OR
r 1r 2
6
AND
r 1r 2
6
TCM
r 1r 2
6
TM
r 1r 2
10
PUSHUD
IR1R2
10
POPUD
IR2R1
6
CP
r 1r 2
6
XOR
r 1r 2
16/18
CPIJE
Irr2RA
16
CPIJNE
Ir1r2RA
3
6
ADD
r1Ir2
6
ADC
r1Ir2
6
SUB
r1Ir2
6
SBC
r1Ir2
6
OR
r1Ir2
6
AND
r1Ir2
6
TCM
r1Ir2
6
TM
r1Ir2
10
PUSHUI
IR1R2
10
POPUI
IR1R2
6
CP
r1Ir2
6
XOR
r1Ir2
12
LDC*
r2Irr1
12
LDC*
r2Irr1
4
10
ADD
R 2R 1
10
ADC
R 2R 1
10
SUB
R 2R 1
10
SBC
R 2R 1
10
OR
R 2R 1
10
AND
R 2R 1
10
TCM
R 2R 1
10
TM
R 2R 1
24
MULT
R2RR1
28/12
DIV
R2RR1
10
CP
R 2R 1
10
XOR
R 2R 1
10
LDW
RR2RR1
20
CALL
IA1
5
10
ADD
IR2R1
10
ADC
IR2R1
10
SUB
IR2R1
10
SBC
IR2R1
10
OR
R 2R 1
10
AND
IR2R1
10
TCM
IR2R1
10
TM
IR2R1
24
MULT
IR2RR1
28/12
DIV
iR2RR1
10
CP
IR2R1
10
XOR
IR2R1
10
LDW
IR2RR1
6
RR
IR1
8
SWAP
IR1
16
LDCD*
r1Irr2
16
LDCPD*
r2Irr1
16
LDCD*
r1Irr2
16
LDCPI*
r2Irr1
10
LD
R 2R 1
18
CALL
IRR1
10
LD
IR2R1
10
LD
R2IR1
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6
10
ADD
R1IM
10
ADC
R1IM
10
SUB
R1IM
10
SBC
R1IM
10
OR
R1IM
10
AND
R1IM
10
TCM
R1IM
10
TM
R1IM
24
MULT
IM2RR1
28/12
DIV
IMRR1
10
CP
R1IM
10
XOR
R1IM
12
LDW
RR1IML
10
LD
IR1IM
10
LD
R1IM
18
CALL
DA1
7
10
BOR
r 0R b
10
BCP
R 1b R 2
10
BXOR*
r 0R b
NOTE
A
8
6
LD
r 1R 2
9
6
LD
R 2R 1
A
12/10
DJNZ
r1RA
B
12/10
JR
CcRA
C
6
LD
r1IM
D
12/10
JP
CcDA
E
6
INC
r1
F
14
NEXT
20
NEXT
22
EXIT
6
WFI
10
LDB*
r 0R b
8
BITC
r 1b
10
BAND*
r 0R b
NOTE
B
6
SBO
6
SBI
6
STOP
10
TSW
RR
6
DI
10
LD
r1xr2
10
LD
r1xr1
NOTE
D
6
EI
14
RET
NOTE
E
16/6
IRET
6
LD
r1Ir2
6
LD
Ir1r2
6
RCF
18
LDC*
r1Irr2xs
18
LDC*
r2Irr1xs
6
CCF
ENG21 1 030617-04
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SCF
6
NOP
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Microcontroller
NOTE A
16/18
BTJRF
r2bRA
16/18
BTJRF
r2bRA
NOTE D
Data Sheet
As of Production Version -01
NOTE B
8
BITS
r1 b
8
BITS
r1 b
NOTE C
6
SRP
IM
20
LDC
r1Irr2xL
20
LDC
r1DA2
NOTE E
20
LDC
r2Irr2xL
20
LDC
r2DA1
6
SRP0
IM
6
SRP1
IM
Legend:
R = 4-bit address
R = 8-bit address
B = bit number
R1 or r1 = dst address
R2 or r2 = src address
Examples:
BOR r0R2
is BOR r1tR1
or BOR r2bR1
LDC r1Irr2
is LDC r1Irr2 = program
or LDE r1Irr2 = date
Sequence:
Opcode, first, second, third operands
NOTE: The blank areas are not defined.
Instructions
Figure 51. Load Instructions
Mnemonic
CLR
LD
LDB
LDC
LDE
LDCD
LDED
LDCI
LDEI
LDCPD
LDEPD
LDCPI
LDEPI
LDW
POP
POPUD
POPUI
PUSH
PUSHUD
PUSHUI
Operands
dst
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
dst, src
dst, src
src
dst, src
dst, src
Instructions
Clear
Load
Load bit
Load program memory
Load data memory
Load program memory and decrement
Load data memory and decrement
Load program memory and increment
Load data memory and increment
Load program memory with pre-decrement
Load data memory with pre-decrement
Load program memory with pre-increment
Load data memory with pre-increment
Load word
Pop stack
Pop user stack (decrement)
Pop user stack (increment)
Push stack
Push user stack (decrement)
Push user stack (increment)
Operands
dst, src
dst, src
dst, src
dst
dst
dst
dst, src
dst
Instructions
Add with carry
Add
Compare
Decimal adjust
Decrement
Decrement word
Divide
Increment
Figure 52. Arithmetic Instructions
Mnemonic
ADC
ADD
CP
DA
DEC
DECW
DIV
INC
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INCW
MULT
SBC
SUB
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Data Sheet
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dst
dst, src
dst, src
dst, src
Increment word
Multiply
Subtract with carry
Subtract
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Data Sheet
As of Production Version -01
Figure 53. Logical Instructions
Mnemonic
AND
COM
OR
XOR
Operands
dst, src
dst
dst, src
dst, src
Instructions
Logical AND
Complement
Logical OR
Logical exclusive
Figure 54. Program Control Instructions
Mnemonic
BTJRT
BTJRF
CALL
CPIJE
CPIJNE
DJNE
ENTER
EXIT
IRET
JP
JP
JR
JR
NEXT
RET
WFI
Operands
dst, src
dst, src
dst
dst, src
dst, src
r, dst
cc, dst
dst
cc, dst
dst
Instructions
Bit test jump relative on True
Bit test jump relative on False
Call procedure
Compare, increment and jump on equal
Compare, increment and jump on non-equal
Decrement and jump on non-zero
Enter
Exit
Return from interrupt
Jump on condition code
Jump unconditional
Jump relative on condition code
Jump relative unconditional
Next
Return
Wait for interrupt
Figure 55. Bit Manipulation Instructions
Mnemonic
BAND
BCP
BITC
BITR
BITS
BOR
BXOR
TCM
TM
TSW
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Operands
dst, src
dst, src
dst
dst
dst
dst, src
dst, src
dst, src
dst, src
src1, src2
Instructions
Bit AND
Bit compare
Bit complement
Bit reset
Bit set
Bit OR
Bit exclusive OR
Test complement under mask
Test under mask
Test Word
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IA88C00
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Data Sheet
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Figure 56. Rotate and Shift Instructions
Mnemonic
RL
RLC
RR
RRC
SWAP
Operands
dst
dst
dst
dst
dst
Instructions
Rotate left
Rotate left through carry
Rotate right
Rotate right through carry
Swap nibbles
Operands
Instructions
Complement carry flag
Disable interrupts
Enable interrupts
Do nothing
Reset carry flag
Set bank flag
Set bank 1
Set carry flag
Set register pointers
Set register pointer zero
Set register pointer one
Enable STOP Mode
Figure 57. CPU Control Instructions
Mnemonic
CCF
DI
EI
NOP
RCF
SBO
SB1
SCF
SRP
SRP0
SRP1
STOP
src
src
src
Interrupts
The IA88C00 supports as many as 27 interrupt sources. Interrupt sources are sorted into 8 different
priority levels. These levels are controlled by the interrupt Priority Register (IPR). Enabling and masking
of individual interrupts is controlled by the System Mode Register (R222).
The various sources, vectors and levels of the interrupt structure are depicted in Figure 58 in this section.
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IA88C00
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INTERRUPT SOURCES
COUNTER 0 ZERO COUNT
EXTERNAL INTERRUPT (P26)
EXTERNAL INTERRUPT (P27)
Data Sheet
As of Production Version -01
POLLING
VECTORS
LEVELS
12
IRQ2
COUNTER 1 ZERO COUNT
EXTERNAL INTERRUPT (P36)
EXTERNAL INTERRUPT (P37)
14
IRQ5
HANDSHAKE CHANNEL 0
EXTERNAL INTERRUPT (P24)
EXTERNAL INTERRUPT (P25)
28
IRQ4
HANDSHAKE CHANNEL 1
EXTERNAL INTERRUPT (P34)
EXTERNAL INTERRUPT (P35)
30
IRQ7
0
RESERVED
2
RESERVED
IRQ3
4
EXTERNAL INTERRUPT (P32)
6
EXTERNAL INTERRUPT (P22)
8
EXTERNAL INTERRUPT (P32)
IRQ0
10
EXTERNAL INTERRUPT (P22)
UART RECEIVE OVERRUN
UART FRAMING ERROR
UART PARITY ERROR
UART WAKEUP DETECT
UART BREAK DETECT
UART CONTROL CHAR DETECT
16
UART RECEIVE DATA
EXTERNAL INTERRUPT (P30)
20
18
IRQ6
22
EXTERNAL INTERRUPT (P20)
24
UART ZERO COUNT
EXTERNAL INTERRUPT (P21)
UART TRANSMIT DATA
EXTERNAL INTERRUPT (P31)
IRQ1
26
Figure 58. Interrupt Levels and Vectors
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Interrupt Programming Model
The IA88C00 maintains program compatibility with the Super8. Enabling or disabling of interrupts are
controlled via the following registers:
Interrupt enable/disable. See the System Mode register (R222).
Level enable. See the interrupt Mask register (R221).
Level priority. See the Interrupt Priority register (R255, Bank 0).
Source enable/disable. Interrupt sources are enabled or disabled in the individual source’s Mode and
Control register.
Functional Overview
For an interrupt to be serviced, it’s source must be enabled. The corresponding interrupt and level must
likewise be enabled. Each interrupt input is conditioned with edge-triggered devices to convert all
interrupt inputs to “levels”. The eliminates the requirement for external hardware to maintain the interrupt
input prior to servicing.
When an interrupt source is received the processor is “vectored” to the vector address associated with the
interrupt. In the fact of multiple interrupts, the enabled interrupt whose level has the highest priority is
serviced first. For interrupts within the same level, the priority of the individual interrupt takes
precedence.
Upon servicing the interrupt, the processor clears the Interrupt Enable bit in the System Mode register to
prevent a high priority interrupt from disrupting the service routine. The program counter and status flags
are pushed onto the stack and the program counter is loaded with the appropriate interrupt vector and the
interrupt service routine (ISR) begins to the execute. Upon completion, the ISR executes an RET
instruction. The flags and program counter are popped off the stack and the Interrupt Enable bit in the
System Mode register is set.
The IA88C00 supports a special mode of “fast” interrupt processing. Utilization of this mode requires
program intervention. The vector address of the ISR must be loaded into the instruction pointer and the
Fast Interrupt enable bit in the System Mode Register must be set. Upon receipt of the interrupt source,
the ISR vector is loaded into the program counter while the old value of the program counter is saved in
the Instruction Pointer. Status flags are saved in the FLAGs register and the Fast interrupt Status Bit in
FLAGS is set. Upon completion of the ISR, the process is reversed.
Stack Operation
The IA88C00 maintains program model compatibility on all Stack operations. The stack may be
maintained in either the register file or in data memory space. For programming model details see
registers R216/R217 (the stack pointer) and register R254 (Memory Timing register)
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Data Sheet
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The IA88C00 also supports user-defined stacks. These stacks are accessed via the PUSHUI, POPUD,
LDEI and LDEPD instructions.
Counter/Timers
The IA88C00 provides two identical 16 bit timer/counters with an 8-bit prescaler. The counters are driven
from a divide-by-4 clock derived from the oscillator. Each count provides robust functionality including:
• Up or down count
• Single or continuous count
• Output pulse train with variable duty cycle
• Input capture
• External gating/triggering
For longer events, the counters may be cascaded to form a 32-bit counter. For program model details see
registers R224 through R230.
DMA
The IA88C00 supports high speed data transfer support for the UART and handshake channel 0 via
Direct Memory Access (DMA). Data can be transferred between these peripherals and contiguous
locations in either the register file or external data memory. For details on the programming model see
registers R235 (UART transmit control) R236 (UART receive control), R244 (Handshake Channel 0
Control) and R240/241, Bank 1 (DMA Count).
WDT
The IA88C00 provides a “Watchdog” (WDT) timer to provide sanity checks on the processor. Should
program execution hang, the WDT timeout will expire and the RESET pin will be held active for 5 ms.
The WDT is prevented from timing out by periodically writing a “1” to bit D5 in the WDT/SMR register.
The WDT clock is derived from either an internal ring oscillator or from the crystal oscillator input. It
should be noted that the frequency of the internal oscillator and associated WDT time-out can vary widely
(as much as 3 times) with voltage and temperature. For details on the WDT programming model see
register R230 (WDT/SMR register).
Stop Mode
When a STOP instruction is executed, the process enter Stop Mode. During Stop mode, the system clock
and external oscillator are disabled. Stop Mode is exited via a hard reset, or by applying an edge to a predefined bit of either Port 2, 3, or 4. For details on the Stop Mode programming model see register R230
(WDT/SMR register).
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Data Sheet
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Halt Mode
When the IA88C00 execute the Wait for Interrupt (WFI) instruction and bit 3 of R223 (Halt Mode
register) is cleared, the processor enters HALT mode. The internal CPU clock is disabled, however, the
oscillator remains active. Use of the UART, timers and DMA remains under user control. The Halt mode
is exited via an interrupt or DMA request. The programming model for Halt Mode is detailed in R223
(Halt Mode register)
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I/O Ports
The IA88C00 contains 40 I/O lines arranged into five 8-bit ports. Each line is TTL-compatible and can be
configured as a address/data line. Each port includes an input register, an output register and a register
address. The input register stores data coming into the port. The output register stores data to be written to
a port. Reading a port’s register address returns the value in the input register. Writing a port’s register
address loads the value in the output register. If the port is configured for an output, this value will appear
on the external pins.
When the CPU reads the bits configured as outputs, the data on the external pins is returned. Under
normal output loading, this has the same effect as reading the output register, unless the bits are
configured as open-drain outputs.
The ports can be configured as shown in Figure 59.
Figure 59. Port Configuration
Port
0
1
2&3
4
Configuration Choices
High address and/or 0
Multiplexed Low address/data or data only
Control I/O for UART, handshake channels, counter/timers,
general I/O and external interrupts
Low address or general I/O
Port 0
Port 0 can be assigned on a bit-by-bit basis as either general I/O or as address bits for external memory.
The bits configured as I/O can be either all inputs or all outputs, they cannot be mixed. If configured for
outputs, they can be either push-pull or open-drain types. I/O direction is controlled by mode control
register R241. Push-pull or open-drain selection is controlled by mode control register R241.
Port 0 can be placed under handshake control handshake channel 1.
Any bits configured as I/O can be accessed via R208.
Port 0 bits configured as address outputs cannot be accessed via the register, and initially the four lower
bits are configured as addresses eight through twelve.
Port 1
Port 1 is bi-directional. Port 1 is configured as either a byte wide Mux'ed Address(low byte)/Data bus or
as Data bus only. This control is via the demux pin. The port address for Port 1 is R209. Port 1 drive
characteristics can be selected to be either Push/Pull or Open Drain. This control is via the mode/control
register R241 Bank0, ControlRegR241B0
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Data Sheet
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Port 2 and 3
Ports 2 and 3 provide external control inputs and outputs for the UART, handshake channels and
counter/timers. The pin assignments appear in Figure 60. Bits not used for control I/O can be configured
as general purpose I/O lines and/or external interrupt inputs.
Those bits configured for general I/O can be configured individually for input for output. Those
configured for output can be individually configured for (1) input or output and (2) open drain or push
pull output.
Figure 60. Pin Assignments for Port 2 and 3
Port 2
Bit Function
0 UART receive clock
1 UART transmit
2 Reserved
3 Reserved
4 Handshake 0 input
5 Handshake 0 output
6 Counter 0 input
7 Counter 0 I/O
Port 3
Bit Function
0 UART receive clock
1 UART transmit
2 Reserved
3 Reserved
4 Handshake 1 input/WAIT
5 Handshake 1 output/DM
6 Counter 1 input
7 Counter 1 I/O
Port 4
Port 4 can be assigned as general I/O or as the lower address byte in de-mux mode. As general I/O, each
bit can be configured individually as input or output, with either push-pull or open-drain outputs. I/O
directions is controlled by mode control reg R246. Push-pull or open_drain selection is controlled by
mode control reg R247. All Port 4 inputs are Schmitt-triggered. Port 4 can be placed under handshake
control handshake channel 0. Port 4 register address is R212.
UART
The UART is a full-duplex asynchronous channel. It transmits and receives independently at 5 to 8 bits
per character and contains options for even- or odd-bit parity and a wake-up feature.
Data can be read into or out of the UART via R239, Bank 0. This single address is able to serve a fullduplex channel because it contains two complete 8-bit registers, one for the transmitter and the other for
the receiver. The programming model for the UART is outlined in R235 (UART Transmit Control),
R236 (UART Receive Control), R237 (UART Interrupt Enable), R238 (Transmit Interrupt Register)
R248/249 bank 1 (UART Baud Rate Generator), R250/251 bank 1 (UART Mode A/B Registers).
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IA88C00
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Data Sheet
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Pins
The UART uses the following Port 2 and 3 pins:
Figure 61. Port 2 and 3 Pins
Port/Pin
2/0
3/0
2/1
3/1
UART Function
Receive Clock
Receive Data
Transmit Clock
Transmit Data
Transmitter
Data is output on the UART when the UART’s register is specified as the destination (dst) of an
operation. This automatically adds the start bit, the programmed parity bit and the programmed number of
stop bits. It can also add a wake-up bit if that option is selected.
The extra bits in R239 are ignored if the UART is programmed to a 5-, 6-, or 7-bit character.
Depending on the programmed data rate, serial data is transmitted at a rate equal to 1, 1\16, 1\32 or 1\64
of the transmitter clock rate. All data is sent out on the falling edge of the clock input.
When the UART has no data to send, it holds the output marking (High). It can be programmed with the
Send Break command to hold the output marking Low (Spacing). This output marking continues until the
command is cleared.
Receiver
The UART begins receive operation when Receive Enable (URC, bit 0) is set to High. After this, a Low
on the receive input pin for longer than half a bit time is interpreted as a start bit. The UART samples the
data on the input pin in the middle of each clock cycle until a complete byte is assembled. This completed
byte is placed in the Receive Data register.
If the 1X clock mode is selected, external bit synchronization must be provided, and the input data is
sampled on the rising edge of the clock.
For character lengths of less than eight bits, the UART inserts 1s into the unused bits. And if parity is
enabled, the parity bit is not stripped. The data bits, extra 1s and the parity bits are placed in the UART
Data register (UIO).
While the UART is assembling a byte in its input shift register, the CPU has time to service an interrupt
and manipulate the data character in UIO.
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Once the complete character is assembled, the UART checks it and performs the following actions:
1. Sets the Control Character status bit, if it is an ASCII control character.
2. Checks the wake-up settings and completes any indicated action.
3. Checks to see if the calculated parity matches the programmed parity bit, if parity is enabled. If they
do not match, it sets the parity Error bit in URC (R236, Bank 0), which remains set until reset by
software.
4. Resets the Framing Error bit (URC, bit 4), if the character is assembled without any stop bits. This bit
remains set until cleared by software.
Overrun errors occur when characters are received faster than they are read. That is, when the UART has
assembled a complete character before the CPU has read current character, the UART sets the Overrun
Error bit (URC, bit 3), and the character currently in the receive buffer is lost.
The overrun bit remains set until cleared by software.
Address Space
The IA88C00 can access 64 Kbytes of program memory and 64 Kbytes of data memory. These spaces can
be either combined or separate. If separate, they are controlled by the DM line (Port P35), which selects
data memory when Low and program memory when High.
CPU Program Memory
Program memory occupies address 0 to 64K. External program memory is accessed by configuring Ports
0 and/or 1 and/or 4 as the memory interface.
The address/data lines are controlled by AS, DS and R/W.
The first 32 program memory bytes are reserved for interrupt vectors. The lowest address available for
user programs is 32 (decimal). This value is automatically loaded into the program counter after a
hardware reset. Port 0 can be configured to provide from 0 to 8 additional address lines. Port 1 is used as
an 8-bit multiplexed address/data port or as a data port when in de-mux mode.
CPU Data Memory
If separated from program memory by the DM optional output, the external CPU data memory space can
be mapped anywhere from 0 to 64K (full 16-bit address space). Data memory uses the same address/data
bit (Port 1) and additional address (chosen from Port 0) as program memory. The DM pin (P35) is mainly
what distinguishes data memory from program memory. It is also distinguished by the fact that data
memory can begin at address 0000H.
Figure 62 shows the system memory space.
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Data Sheet
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65535
65535
External
Data
Memory
External
Program
Memory
32
0
Interrupt Vectors
0
Program Memory
Data Memory
Figure 62. Program and Data Memory Address Space
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Data Sheet
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Absolute Maximum Ratings
Symbol
VDO
TSTG
TA
Description
Supply Voltage*
Storage Temp
Oper Ambient Temp
Min
-0.3
-65
†
Max
+7.0
+150
†
Unit
V
C
C
* Voltages on all pins with respect to GND
† See Ordering Information
CAUTION
Stress that exceeds that presented above may cause permanent damage to the device. This is a stress
rating only. Acceptable operation of the device at any condition above that which is indicated in the
operational sections of these specifications is not implied. Exposure to absolute maximum rating
conditions for an extended period may affect device reliability.
Standard Test Conditions
The following characteristics apply to standard test conditions as noted. All voltages are referenced to
VSS. Positive current flows into the referenced pin (Standard Test Load).
Standard conditions are:
4.5V < VCC < 5.5V
GND – OV
-40ºC < TA < + 85ºC
+5V
1k
From Output
Under Test
150 pF
400 µA
Figure 63. Standard Test Load
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Data Sheet
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DC Characteristics
Symbol
Parameter
VCH
VCL
VIH
VIL
VRH
VRL
VOH
VOL
VIL
IOL
IIR
ICC
ICC1
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
Reset Input High Voltage
Reset Input Low Voltage
Output High Voltage
Output Low Voltage
Input Leakage
Output Leakage
Reset Input Current
VCC Supply Current
Standby Current
ICC2
Standby Current
Min
3.5
-0.3
2.2
-0.3
3.8
-0.3
3.5
-10
-10
Max
Unit
VCC
1.5
VCC
0.8
VCC
0.8
V
V
V
V
V
V
V
V
µA
µA
µA
mA
mA
mA
µA
0.4
10
10
-50
90
5
10
20
Condition
Driven by External Clock Generator
Driven by External Clock Generator
IOH = -400 µA
IOL = +400 mA
[1]
@ 20 MHz [2]
@ 30 MHz [2]
[3]
NOTES
Following are estimated values:
1. In this case all outputs and I/O pins are floating.
2. Estimated Values, not tested. HALT mode is invoked with UART CT0 and CT1 deactivated with all input pins tied to VCC
or VSS.
3. Estimated Values, not tested. STOP mode is invoked with all input pins tied to VCC or VSS.
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AC Electrical Characteristics
Figure 64. External I/O or Memory Read and Write Timing
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
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Symbol
TdA(AS)
ThAS(A)
TdAS(DI)
TwAS
TdAZ (DSR)
TwDSR
TwDSW
TdDSR (DI)
ThDSR (DI)
TdDS (A)
TdDA (AS)
TdR/W (AS)
TdDS (R/W)
TdDO (DSW)
ThDSW (DO)
TdA (DI)
TdAS (DSR)
TsDI (DSR)
TdDM (AS)
TdDS (DM)
ThDS (A)
TwW
TdAS (W)
Parameter
Address valid to /AS Rise Delay
/AS Rise to Address Valid
/AS Rise to Data in Required Valid Delay
/AS Low Width
Address Float to /DS (Read)
/DS (Read) Low Width
/DS (Write) Low Width
/DS (Read) to Data
/DS Rise (Read) to Data in Hold Time
/DS Rise to Address Active Delay
/DS Rise to /AS Delay
R/W to AS Rise Delay
DS Rise to R/W Valid Delay
Data Out to /DS (Write) Delay
/DS Rise (Write) to Data Out Hold Time
Address to Data In Required Valid Delay
/AS Rise to D/S (Read) Delay
Data in Setup Time to DS Rise (Read)
/DM to /AS Rise Delay
/DS Rise to /DM Valid Delay
/DS Rise to Address Valid Hold Time
Wait Width (One Wait) Window
/AS Rise to Wait Delay
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Figure 65. 20 MHz Timing
No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TdA (AS)
ThAS (A)
TdAS (DI)
TwAS
TdAZ (DSR)
TwDSR
TwDSW
TdDSR (DI)
ThDSR (DI)
TdDS (A)
TdDS (AS)
TdR/W (AS)
TdDS (R/W)
TdDO (DSW)
ThDSW (DO)
TdA (DI)
TdAS (DSR)
TsDI (DSR)
TdDM (AS)
TdDS (DM)
ThDS (A)
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Normal
Min
Max
25
25
Extended
Min
70
70
180
35
0
140
85
375
85
0
285
185
115
0
25
20
25
20
30
20
260
0
25
65
70
65
70
65
205
25
25
20
20
20
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Max
445
70
65
65
65
65
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Figure 66. 12 MHz Timing
No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TdA (AS)
ThAS (A)
TdAS (DI)
TwAS
TdAZ (DSR)
TwDSR
TwDSW
TdDSR (DI)
ThDSR (DI)
TdDS (A)
TdDS (AS)
TdR/W (AS)
TdDS (R/W)
TdDO (DSW)
ThDSW (DO)
TdA (DI)
TdAS (DSR)
TsDI (DSR)
TdDM (AS)
TdDS (DM)
ThDS (A)
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Normal
Min
Max
55
55
Extended
Min
135
135
305
70
0
240
150
630
150
0
480
320
215
0
55
45
55
45
65
45
440
0
130
125
135
125
150
125
365
55
25
50
45
45
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Max
770
135
25
130
125
125
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Figure 67. 25 MHz Timing
No.
Symbol
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
TdA (AS)
ThAS (A)
TdAS (DI)
TwAS
TdAZ (DSR)
TwDSR
TwDSW
TdDSR (DI)
ThDSR (DI)
TdDS (A)
TdDS (AS)
TdR/W (AS)
TdDS (R/W)
TdDO (DSW)
ThDSW (DO)
TdA (DI)
TdAS (DSR)
TsDI (DSR)
TdDM (AS)
TdDS (DM)
ThDS (A)
Normal
Min
Max
15
15
Extended
Min
Max
50
50
140
26
0
110
65
280
65
0
220
142
85
0
20
15
15
15
20
15
195
0
55
50
50
50
50
50
155
15
25
10
15
15
330
50
25
45
50
50
Input Handshake Timing
DATA IN
1
5
3
DAV IN
6
4
RDY OUT
7
2
Figure 68. Fully Interlocked Mode (Input Handshake)
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Data Sheet
As of Production Version -01
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DATA IN
1
DAV IN
5
4
Figure 69. Strobed Mode (Input Handshake)
AC Electrical Characteristics
Input Handshake
No.
1
2
3
4
5
6
7
Symbol
TsDI(DAV)
TdDAVlf(RDY)
ThDI(RDY)
TwDAV
ThD(DAV)
TdDAV(RDY)
TdRDYf(DAV)
Parameter
Data In to Setup Time
/DAV Fall Input to RDY Fall Delay
Data In Hold Time from RDY Fall
/DAV In Width
Data In Hold Time from /DAV Fall
/DAV Rise Input to RDY Rise Delay
RDY Rise Output to /DAV Rise Delay
Min
0
Max
Notes*†
200
1
100
2
0
45
130
0
NOTES
1. Standard Test Load
2. This time assumes user program reads data before /DAV Input goes High. RDY will not go high before data is read.
* Times are given in nanoseconds.
† Times are preliminary and subject to change.
Output Handshake Timing
DATA OUT
1
5
DAV OUT
2
4
3
RDY IN
Figure 70. Fully Interlocked Mode (Output Handshake)
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DATA OUT
1
6
DAV OUT
Figure 71. Strobed Mode (Output Handshake)
AC Electrical Characteristics (12 MHz, 20 MHz)
Output Handshake
No.
1
2
3
4
5
6
Symbol
TdDO(DAV)
TdRDYr(DAV)
ThDAV(RDY)
TdRDY(DAV)
TdDAVOr(RDY)
TwDAVO
Parameter
Data Out to /DAV Fall Delay
RDY Rise Input to /DAV Fall Delay
/DAV Fall Output to RDY Fall Delay
/RDY Fall Input to /DAV Rise Delay
/DAV Rise Output to RDY Rise Delay
/DAV Output Width
Min
90
0
0
0
150
Max
110
Notes*†
1, 2
1
110
1
2
Notes:
1. Standard Test Load
2. Time given is for zero value in Deskew Counter. For non-zero value of n where n = 1,2, …15 add 2 x n x TpC to the given
time.
†
Times given are in nanoseconds.
*
Times are preliminary and subject to change.
ERPOM Read Timing
ADDRESS OUT
A0 A13
1
D0 DY IN
DATA IN
Figure 72. EPROM READ Timing
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Data Sheet
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AC Electrical Characteristics (20 MHz)
EPROM Read Cycle
No.
1
Symbol
TdA(DR)
Parameter
Address Valid to Read Data Required Valid
Min
Max Notes†*
170
1
NOTES
1. WAIT states add 167 ns to these times.
† All times are in nanoseconds and are for 12 MHz input frequency.
* Timings are preliminary and subject to change.
Wait Timing
T1
T2
TWAIT
T3
SCLK
a
b
Tc
Tc
/AS
c
e
d
/DS
F
G
/WAIT
Figure 73. Wait Timing
a
b
c
d
e
F
G
Description
Skew of T1 SCLK Rise to /AS Fall
Skew of T1 SCLK Rise to /AS Rise
Skew of T2 SCLK Rise to Read /DS Fall
Skew T2 SCLK Fall to Write /DS Fall
Skew T3 SCLK Fall to /DS Rise
/WAIT Fall Delay After T2 SCLK Fall to Generate at Least 1 WAIT State
/WAIT Fall Delay after T2 SCLK Fall to Prevent an Additional WAIT State
10.0
10.0
20.0
20.0
20.0
20.0
15.0
Max
Max
Max
Max
Max
Max
Max
NOTES
All figures are in nanoseconds.
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Data Sheet
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De-Multiplexed Bus Timing
Demixed A/D Bus
T1
T2
T3
CLK
P0
A8 - A15
P1
D0 - D7
P4
A0 - A7
/AS
/DS
R/W
/DM
NOTES
/AS, /DS, R/W, /DM Timing remains unchanged in demuxed A/D bus mode.
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Microcontroller
Data Sheet
As of Production Version -01
Package Information
24
1
D62R
.540
.560
25
48
2470
max
Figure 74. 48-Lead Aerial View
.060
.075
.145
.165
.125
min
.060
.090
.015
.021
.100
TYP
.015
min
.040
.060
Figure 75. 48-Lead Side View
600
.620
009
.015
610
.650
Figure 76. 48-Lead End View
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AERIAL VIEW
45 DEG x .045 max
PIN 1 I.D.
.026
.030
.950
.958
.985
1.000
050 +/-.001
TYP
Figure 77. 68-Lead Package Aerial View
Bottom View
10
26
9
27
1
68
61
43
60
44
Figure 78. 68-Lead Package Bottom View
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Data Sheet
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Side View
.045 x 45 DEG
.105
.115
.170
.180
.020
.026
.016
.020
.900
.980
.035R TYP
Dim. from Center to
Center of Radii
Figure 79. 68-Lead Package Side View
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IA88C00
Microcontroller
Data Sheet
As of Production Version -01
Ordering Information
Innovasic
Semiconductor
Part Number
IA88C00-PDW48C
(standard packaging)
IA88C00-PDW48I
(standard packaging)
Package
Type
Temperature
Grades
48-Pin Plastic Dual Inline Package (DIP)
IA88C00-PDW48C-R
(RoHS packaging)
IA88C00-PDW48I-R
(RoHS packaging)
IA88C00-PLC68C
(standard packaging)
IA88C00-PLC68I
(standard packaging)
IA88C00-PLC68C-R
(RoHS packaging)
IA88C00-PLC68I-R
(RoHS packaging)
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Commercial
Industrial
Commercial
Industrial
68-Pin Plastic Leaded
Chip Carrier (PLCC)
Commercial
Industrial
Commercial
Industrial
ENG21 1 030617-04
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