ICS426 Serial ATA/Fibre Channel Clock Synthesizer Description Features The ICS426 was developed for serial ATA (SATA) and fiber channel. It generates a high quality, high frequency clock output from a low cost frequency crystal or clock input. • • • • • • • Using Phase-Locked-Loop (PLL) techniques, the device runs from a standard fundamental mode, inexpensive crystal or clock input. Packaged in 16 pin TSSOP Input crystal or clock frequency of 25 MHz (typical) Supports serial ATA Generation 1 Supports Fiber Channel Duty cycle of 45/55 Operating voltage of 3.3V Advanced, low power, CMOS process Block Diagram VDD 4 S0:S1 25 MHz Crystal or Clock Input X1 PLL /Clock Synthesis Circuitry Crystal Oscillator X2 Capacitors may be required with a crystal input. CLK 6 OE GND 1 MDS 426 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com ICS426 Serial ATA/Fibre Channel Clock Synthesizer Pin Assignment Clock Output Select Table (MHz) X1/ICLK 1 16 X2 VDD 2 15 GND VDD 3 14 GND GND 4 13 OE GND 5 12 GND S1 6 11 S0 VDD 7 10 VDD CLK 8 9 GND S1 S0 Input CLK Output 0 0 25 75 0 1 25 150 1 0 25 106.25 1 1 25 156.25 16 pin 173 mil (0.65 mm) TSSOP Pin Descriptions Pin Number Pin Name Pin Type 1 X1/ICLK XI 2 VDD Power Connect to +3.3 V. 3 VDD Power Connect to +3.3 V. 4 GND Power Connect to ground. 5 GND Power Connect to ground. 6 S1 Input 7 VDD Power Connect to +3.3 V. 8 CLK Output Clock output. Tri-state output when OE is low. 9 GND Power Connect to ground. 10 VDD Power Connect to +3.3V. 11 S0 Input 12 GND Power 13 OE Input Output Enable. All outputs are tri-stated when low. Internal pull-up. 14 GND Power Connect to ground. 15 GND Power Connect to ground. 16 X2 XO Crystal connection. Connect to a 25 MHz fundamental mode crystal or clock input. Select pin 1 determines CLK output based on table above. Internal pull-up. Select pin 0 determines CLK output based on table above. Internal pull-up. Connect to ground. Crystal connection. Connect to a 25 MHz fundamental mode crystal or float for clock input. 2 MDS 426 B Integrated Circuit Systems, Inc. Pin Description ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com ICS426 Serial ATA/Fibre Channel Clock Synthesizer External Components The value (in pF) of these crystal caps should equal (CL -18pF)*2. In this equation, CL= crystal load capacitance in pF. Example: For a crystal with a 20 pF load capacitance, each crystal capacitor would be 4 pF [(20-18) x 2] = 20. Decoupling Capacitor As with any high performance mixed-signal IC, the ICS426 must be isolated from system power supply noise to perform optimally. PCB Layout Recommendations A decoupling capacitor of 0.01µF must be connected between each VDD and the PCB ground plane. Series Termination Resistor For optimum device performance and lowest output phase noise, the following guidelines should be observed. Clock output traces over one inch should use series termination. To series terminate a 50Ω trace (a commonly used trace impedance), place a 33Ω resistor in series with the clock line, as close to the clock output pin as possible. The nominal impedance of the clock output is 20Ω. 1) The 0.01µF decoupling capacitors should be mounted on the component side of the board as close to the VDD pins as possible. No vias should be used between the decoupling capacitors and VDD pins. The PCB trace to VDD pins should be kept as short as possible, as should the PCB trace to the ground via. Crystal Load Capacitors The device crystal connections should include pads for small capacitors from X1 to ground and from X2 to ground. These capacitors are used to adjust the stray capacitance of the board to match the nominally required crystal load capacitance. Because load capacitance can only be increased in this trimming process, it is important to keep stray capacitance to a minimum by using very short PCB traces (and no vias) between the crystal and device. Crystal capacitors, if needed, must be connected from each of the pins X1 and X2 to ground. 3) To minimize EMI the 33Ω series termination resistor, if needed, should be placed close to the clock output. 4) An optimum layout is one with all components on the same side of the board, minimizing vias through other signal layers. Other signal traces should be routed away from the ICS426. This includes signal traces just underneath the device, or on layers adjacent to the ground plane layer used by the device. 3 MDS 426 B Integrated Circuit Systems, Inc. 2) The external crystal should be mounted just next to the device with short traces. The X1 and X2 traces should not be routed next to each other with minimum spaces, instead they should be separated and away from other traces. ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com ICS426 Serial ATA/Fibre Channel Clock Synthesizer Phase Noise Graph 25 MHz crystal input, 106.25 MHz CLK output. Phase Noise 106.25 M Hz 0 -20 -40 L(f) dBc -60 -80 -100 -120 -140 1E+3 10E+3 100E+3 1E+6 10E+6 offset frequency Absolute Maximum Ratings Stresses above the ratings listed below can cause permanent damage to the ICS426. These ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended operating temperature range. Item Rating Supply Voltage, VDD 7V All Inputs and Outputs -0.5V to VDD+0.5V Ambient Operating Temperature 0 to +70°C Storage Temperature -65 to +150°C Junction Temperature 175°C Soldering Temperature 260°C 4 MDS 426 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com ICS426 Serial ATA/Fibre Channel Clock Synthesizer Recommended Operation Conditions Parameter Min. Ambient Operating Temperature Typ. Max. Units +70 °C +3.46 V 0 Power Supply Voltage (measured in respect to GND) +3.13 +3.3 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70°C Parameter Symbol Conditions Min. Typ. Max. Units 3.13 3.3 3.47 V Operating Voltage VDD Supply Current IDD No load Input High Voltage VIH OE, S0, S1 Input Low Voltage VIL OE, S0, S1 Output High Voltage VOH IOH = -4 mA VDD-0.4 V Output High Voltage VOH IOH = -12 mA 2.4 V Output Low Voltage VOL IOL = 12mA Short Circuit Current IOS CLK output ±50 mA On Chip Pull-up Resistor RPU OE, S0, S1 150 kΩ Input Capacitance CIN OE, S0, S1 5 pF 22 mA 2 V 0.8 0.4 V V AC Electrical Characteristics Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature 0 to +70° C Parameter Symbol Input Frequency FIN Output Clock Duty Cycle Conditions Min. Typ. 45 50 Crystal or clock input Max. 25 Measured at VDD/2, Note 1 Units MHz 55 % Output Rise Time tOR 0.8 to 2.0V, Note 1 1 ns Output Fall Time tOF 2.0 to 0.8V, Note 1 1 ns Short Term Jitter peak to peak, Note 1 ±70 ps Long Term Jitter Measured over 1000 cycles; peak to peak, Note 1 170 ps Phase Noise 106.25M CLK, relative to carrier, 100 Hz offset -90 dBc/Hz 106.25M CLK, relative to carrier, 1kHz offset -115 dBc/Hz 106.25M CLK, relative to carrier, 10 kHz offset -121 dBc/Hz 106.25M CLK, relative to carrier, 100 kHz offset -116 dBc/Hz Note 1: Measured with 15 pF load. 5 MDS 426 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com ICS426 Serial ATA/Fibre Channel Clock Synthesizer Package Outline and Package Dimensions (16 pin TSSOP, 173 Mil. Narrow Body) Package dimensions are kept current with JEDEC Publication No. 95 Millimeters 16 Symbol E1 A A1 A2 b C D E E1 e L α aaa E IN D E X AREA 1 2 D A 2 Min Inches Max -1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 4.90 5.1 6.40 BASIC 4.30 4.50 0.65 Basic 0.45 0.75 0° 8° -0.10 Min Max -0.047 0.002 0.006 0.032 0.041 0.007 0.012 0.0035 0.008 0.193 0.201 0.252 BASIC 0.169 0.177 0.0256 Basic 0.018 0.030 0° 8° -0.004 A A 1 c -C e S E A T IN G P LAN E b α L aaa C Ordering Information Part / Order Number Marking (both) Shipping packaging Package Temperature ICS426G ICS426GT ICS426G ICS426G Tubes Tape and Reel 16 pin TSSOP 16 pin TSSOP 0 to +70° C 0 to +70° C While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments. 6 MDS 426 B Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 Revision 091102 ● tel (408) 295-9800 ● www.icst.com