ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER GENERAL DESCRIPTION FEATURES The ICS83210 is a low skew, 1-to-10 HSTL Fanout ICS Buffer and a member of the HiPerClockS™ Family HiPerClockS™ of High Performance Clock Solutions from IDT. The class II HSTL outputs are balanced push-pull in design, capable of delivering 16mA into a 10pF load. This class allows both source series termination and symmetrically double parallel termination. • Ten single-ended HSTL outputs • One single-ended HSTL clock input • Maximum input frequency: 150MHz • Output skew: 110ps (maximum) • Part-to-part skew: 2ns (maximum) • 1.5V power supply • 0°C to 85°C ambient operating temperature • Available in both standard (RoHS 5) and lead-free (RoHS 6) packages BLOCK DIAGRAM PIN ASSIGNMENT GND Q2 Q1 VDD VDD Q0 GND GND Q0 32 31 30 29 28 27 26 25 Q1 IN Q8 Q9 nOE Pulldown VDD 1 24 GND GND 2 23 Q3 VDD 3 22 Q4 nOE 4 21 VDD GND 5 20 VDD ICS83210 IN 6 19 Q5 VDD 7 18 Q6 GND 8 17 GND 9 10 11 12 13 14 15 16 GND Q7 Q8 VDD VDD Q9 GND GND 32-Lead TQFP 7mm x 7mm x 1.0mm package body Y package Top View IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 1 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER TABLE 1. PIN DESCRIPTIONS Number 1, 3, 7, 12, 13, 20, 21, 28, 29 2, 5, 8, 9, 10, 16, 17, 24, 25, 31, 32 Name 4 Type Description VDD Power Power supply pins. GND Power Power supply ground. nO E Input Output enable/disable input pin. When LOW, outputs Qx outputs Pulldown are enabled. When HIGH, Qx outputs are disabled low. LVCMOS/LVTTL interface levels. Single-ended reference clock input. HSTL interface levels. 5 IN Input Q9, Q8, Q7, 11, 14, 15, Q6, Q5, Q4, Output Single-ended HSTL clock outputs. 18, 19, 22, 23, 26, 27, 30 Q3, Q2, Q1, Q0 NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol Parameter Test Conditions Minimum Typical Maximum Units CIN Input Capacitance 4 pF RPULLDOWN Input Pulldown Resistor 51 kΩ COUT Output Pin Capacitance 4.5 ROUT Output Impedance 20 IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 2 6 pF Ω ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD 4.6V NOTE: Stresses beyond those listed under Absolute Maximum Inputs, VI -0.5V to VDD + 0.5 V Ratings may cause permanent damage to the device. These rat- Outputs, VO -0.5V to VDD + 0.5V ings are stress specifications only. Functional operation of prod- Package Thermal Impedance, θJA 75.5°C/W (0 mps) uct at these conditions or any conditions beyond those listed in Storage Temperature, TSTG the DC Characteristics or AC Characteristics is not implied. -65°C to 150°C Exposure to absolute maximum rating conditions for extended periods may affect product reliability. TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 1.5V ± 8%, TA = 0°C TO 85°C Symbol Parameter Test Conditions VDD Power Supply Voltage IDD Power Supply Current IDDQ Quiescent Supply Current Minimum Typical Maximum Units 1.38 1.5 1.62 V 215 250 mA 1 mA Outputs Loaded @ 62.5MHz VIN = 0V, outputs disabled TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 1.5V ± 8%, TA = 0°C TO 85°C Symbol Parameter Maximum Units VIH Input High Voltage nOE Test Conditions Minimum 0.7*VDD Typical VDD + 0.3 V VIL Input Low Voltage nOE -0.3 0.3*VDD V IIH Input High Current nOE 150 µA IIL Input Low Current nOE -5 µA TABLE 3C. HSTL DC CHARACTERISTICS, VDD = 1.5V ± 8%, TA = 0°C TO 85°C Symbol Parameter Test Conditions VIH Input High Voltage IN IN VREF = 0.75V Minimum 0.85 Typical Maximum Units 1.8 V VIL Input Low Voltage -0.3 0.65 V VOH Output High Voltage; NOTE 1 IOH = -16mA 1.0 VDD + 0.3 V VOL Output Low Voltage; NOTE 1 IOL = 16mA -0.3 0.4 V NOTE 1: Outputs terminated with 50Ω to ground. IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 3 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER TABLE 4. AC CHARACTERISTICS, VDD = 1.5V ± 8%, TA = 0°C TO 85°C Symbol Parameter fIN tsk(o) Input Frequency Propagation Delay, Low-to-High; NOTE 1 Propagation Delay, High-to-Low NOTE 1 Output Skew; NOTE 2, 4 tsk(pp) Par t-to-Par t Skew; NOTE 3, 4 tPLH tPHL Test Conditions Minimum Typical Maximum Units 150 MHz 1.0 5. 5 ns 1.0 5.5 ns 110 ps 2 ns tEN Output Enable Time 7 ns tDIS Output Disable Time 7 ns t R / tF Output Rise/Fall Time 1.3 ns o dc Output Duty Cycle 52 % 55 % 20% to 80% 250 Fout ≤ 100MHz 48 Fout > 100MHz 45 NOTE 1: Measured from the VDD/2 of the input to VDD/2 of the output. NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the output differential cross points. NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load conditions at the same temperature. Using the same type of inputs on each device, the outputs are measured at the differential cross points. NOTE 4: This parameter is defined in accordance with JEDEC Standard 65. IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 4 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER PARAMETER MEASUREMENT INFORMATION 0.75V±8% PART 1 V SCOPE VDD DD Qx PART 2 Qx HSTL 2 V DD Qy 2 tsk(pp) GND -0.75V±8% 1.5V OUTPUT LOAD AC TEST CIRCUIT PART-TO-PART SKEW DD Qx VDD VDD V IN 2 2 2 VDD VDD Q0:Q9 V DD Qy 2 tsk(o) 2 2 tpLH tpHL PROPAGATION DELAY OUTPUT SKEW V DD 80% 2 Q0:Q9 80% t PW t Clock Outputs 20% 20% tR tF odc = PERIOD t PW x 100% t PERIOD OUTPUT RISE/FALL TIME IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD 5 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER APPLICATION INFORMATION RECOMMENDATIONS FOR UNUSED OUTPUT PINS OUTPUTS: HSTL OUTPUTS All unused HSTL outputs can be left floating. We recommend that there is no trace attached. RELIABILITY INFORMATION TABLE 5. θJAVS. AIR FLOW TABLE FOR 32 LEAD TQFP θ by Velocity (Meters per Second) JA Multi-Layer PCB, JEDEC Standard Test Boards 0 1 2.5 75.5°C/W 65.8°C/W 62.2°C/W TRANSISTOR COUNT The transistor count for ICS83210 is: 218 Pin compatible with CY2HH8110 IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 6 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD TQFP -HD VERSION HEAT SLUG DOWN TABLE 6. PACKAGE DIMENSIONS JEDEC VARIATION ALL DIMENSIONS IN MILLIMETERS ABA SYMBOL MINIMUM NOMINAL MAXIMUM 32 N A -- -- 1.20 A1 0.05 0.10 0.15 A2 0.95 1.0 1.05 b 0.30 0.35 0.40 c 0.09 -- 0.20 D 9.00 BASIC D1 7.00 BASIC D2 5.60 Ref. E 9.00 BASIC E1 7.00 BASIC E2 5.60 Ref. 0.80 BASIC e 0.60 0.75 L 0.45 θ 0° -- 7° ccc -- -- 0.10 Reference Document: JEDEC Publication 95, MS-026 IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 7 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER TABLE 7. ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS83210AY ICS83210AY 32 lead TQFP tray 0°C to 85°C ICS83210AYT ICS83210AY 32 lead TQFP 1000 tape & reel 0°C to 85°C ICS83210AYLF ICS83210AYLF 32 lead "Lead-Free" TQFP tray 0°C to 85°C ICS83210AYLFT ICS83210AYLF 32 lead "Lead-Free" TQFP 1000 tape & reel 0°C to 85°C NOTE: Par ts that are ordered with an "LF" suffix to the par t number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those requiring extended temperature ranges, high reliability or other extraordinary environmental requirements are not recommended without additional processing by IDT. IDT reserves the right to change any circuitry or specifications without notice. IDT does not authorize or warrant any IDT product for use in life support devices or critical medical instruments. IDT ™ / ICS™ LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER 8 ICS83210AY REV. A MAY 15, 2007 ICS83210 LOW SKEW, 1-TO-10 HSTL FANOUT BUFFER Innovate with IDT and accelerate your future networks. Contact: www.IDT.com For Sales For Tech Support 800-345-7015 408-284-8200 Fax: 408-284-2775 [email protected] 480-763-2056 Corporate Headquarters Asia Pacific and Japan Europe Integrated Device Technology, Inc. 6024 Silver Creek Valley Road San Jose, CA 95138 United States 800 345 7015 +408 284 8200 (outside U.S.) Integrated Device Technology Singapore (1997) Pte. Ltd. Reg. No. 199707558G 435 Orchard Road #20-03 Wisma Atria Singapore 238877 +65 6 887 5505 IDT Europe, Limited 321 Kingston Road Leatherhead, Surrey KT22 7TU England +44 (0) 1372 363 339 Fax: +44 (0) 1372 378851 © 2006 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be trademarks or registered trademarks used to identify products or services of their respective owners. Printed in USA