Integrated Circuit Systems, Inc. ICS9176C-03 Low Skew Output Buffer General Description The IC9176C-03 is designed specifically to support the tight timing requirements of high-performance microprocessors and chip sets. Because the jitter of the device is limited to ±250ps, the ICS9176C-03 is ideal for clocking Pentium™ systems. the 10 high drive (40mA), lowskew (±250ps) outputs make the ICS9176C-03 a perfect fit for PCI clocking requirements. The ICS9176C-03 has 10 outputs synchronized in phase and frequency to an input clock. The internal phase locked loop (PLL) acts either as 1X clock multiplier or a 1/2X clock multiplier depending on the state of the input control pins T0 and T1. With metal mask options, any type of ratio between the input clock and output clock can be achieved, including 2X. The PLL maintains the phase frequency relationship between the input clock and the outputs by externally feeding back FBOUT to FBIN. Any change in the input will be tracked by all 10 outputs. However, the change at the outputs will happen smoothly so no glitches will be present on any driven input. The PLL circuitry matches rising edges of the input clock and the output clock. Since the input to FBIN skew is guarenteed to ±500ps, the part acts as a "zero delay" buffer. The ICS9176C-03 has a total of eleven ouputs. Of these, FBOUT is dedicated as the feedback into the PLL and another, Q/2, has an output frequency half that of the remaining nine. These nine outputs can either by running at the same speed as the input, or at half the frequency of the input. With Q/2 as the feedback to FBIN, the nine 'Q' outputs will be running at twice the input frequency in the normal divide-by-1 mode. In this case, the output can go to 120 MHz with a 60 MHz input clock. The maximum rise and fall time of an output is 14ns and each is TTL-compatible with a 40mA symmetric drive. Features • 3.3 or 5.0 volt supply operation • ±500 skew (max) between input and outputs • ±250ps skew (max) between outputs • 10 symmetric, TLL-compatible outputs • 28-pin SOIC package • High drive, 40mA outputs • Power-down option • Output frequency range 25 MHz to 120 MHz • Input frequency range 25 MHz to 100 MHz • Ideal for PCI bus applications Selection Table T1 T0 Description 0 0 Power-down 0 1 Test Mode (PLL Off CLK=outputs) 1 0 Normal (PLL On) 1 1 Divide by 2 Mode Block Diagram The ICS9176C-03 is fabricated using CMOS technology which results in much lower power consumption and cost compared with the gallium arsenide based 1086E. The typical operating current for the ICS9176C-03 is 60mA versus 115mA for the GA1086E. 9176C-03 Rev D 01/29/02 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate. ICS9176C-03 Pin Assignment 28-Pin SOIC Pin Descriptions Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Name GND Q8 Q9 VDD GND NC NC VDD CLK T1 FBIN T0 VDD Q/2 GND FBOUT Q1 VDD GND Q2 Q3 VDD Q4 Q5 GND VDD Q6 Q7 Type Output Output Input Input Input Input Output Output Output Output Output Output Output Output Output Description GROUND Output clock 8. Output clock 9 Power supply GROUND No Connect. No Connect. Power supply. Input for reference clock. T1 selects normal operation, power-down, or test mode. FEEDBACK INPUT from output FBOUT. T0 selects normal operation, poewer -down, or test mode. Power Supply. Half-clock output. GROUND. FEEDBACK OUTPUT to input FBIN. Output clock1. Power Supply. GROUND. Output clock 2. Output clock 3. Power Supply. Output clock 4. Output clock 5. GROUND. Power Supply Output clock 6. Output clock 7. 2 ICS9176C-03 Timing Diagrams Timing in Divide by1 Mode Timing in Divide by 2 Mode Timing in Divide by 2 Mode Note: In test mode, the VCOs are bypassed. The test clock input is simply buffered, then output. The part is transparent. Damage to the device may occur if an output is shorted or forced to ground or VDD. Timing in Power-down Mode 3 ICS9176C-03 Absolute Maximum Ratings VDD referenced to GND......................................................... Operating Temperature under bias....................................... Storage Temperature............................................................... Voltage on I/O pins referenced to GND................................ Power Dissipation................................................................... 7V 0º to +70ºC -65ºC to +150ºC GND -0.5V to VDD +0.5V 0.5 Watts Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliabilty. Electrical Characteristics 3.3 Volt DC Characteristics VDD = +3.3V±5%, TA = 0ºC to 70ºC unless otherwise stated Parameter Symbol Test Conditions Min Typ Max Units Input Low Voltage VIL VDD=3.3V - - 0.8 V Input High Voltage VIH VDD=3.3V 2.0 - - V Input Current Ii VIN=0V,5V -5 - 5 mA Output Low Voltage VOL @IOL=12mA - 0.25 0.4 V Output Low Current IOL @VOL=0.8V 21 31 - mA Output High Voltage VOH @IOH=-14mA 2.4 2.8 - V Output High Current IOH @VOH=2.0V - -28 -34 mA Power Supply Current Idd @66.66MHz No load - 45 90 mA Power Down Current Iddpd - 0.5 8 mA 5.0 Volt DC Characteristics VDD = +5V±5%, TA = 0ºC to 70ºC unless otherwise stated Parameter Symbol Test Conditions Min Typ Max Units Input Low Voltage VIL VDD=5V - - 0.8 V Input High Voltage VIH VDD=5V 2.0 - - V Input Current Ii VIN=0V,5V -5 - 5 µA Output Low Voltage VOL @IOL=13mA - 0.25 0.4 V Output Low Current IOL @VOL=0.8V 27 36 - mA Output High Voltage VOH @IOH=-38mA 2.4 3.5 - V Output High Current IOH @VOH=2.0V - -77 -41 mA Power Supply Current Idd @ 66.66MHz No load - 74 180 mA Power Down Current Iddpd - 1.0 10 mA 4 ICS9176C-03 AC Characteristics (3.3 volt supply) Parameter Symbol Min Typ Max Units 2.5 - 7.5 ns tr Test Conditions VDD=4.5V, fCLK=100MHz 15pF load Input Clock Pulse Width* CLKW Output Rise Time, 0.8 to 2.0V* - 0.5 1 ns Output Fall time, 2.0V to 0.8V* tr 15pF load - 0.4 1 ns Output Duty Cycle* dt 15pF load 45 48/51 55 % Jitter, 1 sigma* T1s - 50 150 ps -150 80 156 ps 25 - 90 MHz 25 - 90 MHz 0 250 500 ps - 500 1 ns -250 50 250 ps 0.4 1.0 ns Jitter, absolute* Tabs Input Frequency fi Output Frequency (Q outputs) fo FBIN to IN skew tskew1a FBIN to IN skew tskew1b Skew between any 2 outputs at same frequency Skew between any 1 output and Q/2 tskew2 20 - 80MHz Note1,3. Input 50MHz & Higher rise time <3ns Note1,3. Input 50MHz & Lower rise time <3ns Note 1, 3. Notes: 1. All skew specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 2. Duty cycle measured at 1.4V. 3. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. *Guaranteed by design and characterization. Not subject to 100% test. 5 ICS9176C-03 AC Characteristics (5.0 volt supply) Parameter Symbol Min Typ Max Units 2.5 - 7.5 ns tr Test Conditions VDD=4.5V, fCLK=100MHz 15pF load Input Clock Pulse Width* CLKW Output Rise Time, 0.8 to 2.0V* - 0.5 1.0 ns Rise time, 20% to 80% VDD* tr 15pF load - 1.2 2 ns Output Fall time, 2.0V to 0.8V* tr 15pF load - 0.5 1 ns Fall time, 80% to 20% VDD* tr 15pF load - 1.0 2 ns Output Duty Cycle* dt 15pF load 45 48/51 55 % Jitter, 1 sigma* T1sa 25 - 80MHz - 50 100 ps Jitter, 1 sigma* T1sb 25 - 80MHz - 100 200 ps Jitter, absolute* Tabsa 25 - 80MHz -150 ±100 150 ps 80MHz & Higher -100 200 400 ps 25 - 100 MHz 25 - 120 MHz 250 500 ps - 0.5 1 ns -250 50 250 ps 0.400 1.0 ns Jitter, absolute* Tabsb Input Frequency fi Output Frequency (Q outputs) fo FBIN to IN skew tskew1 FBIN to IN skew tskew1 Skew between any 2 outputs at same frequency Skew between any 1 output and Q/2 tskew2 with Q/C as feedback Note1,3. Input 50MHz & Higher rise time <3ns Note1,3. Input 50MHz & Lower rise time <3ns Note 1, 3. Notes: 1. All skew specifications are measured with a 50Ω transmission line, load terminated with 50Ω to 1.4V. 2. Duty cycle measured at 1.4V. 3. Skew measured at 1.4V on rising edges. Loading must be equal on outputs. *Guaranteed by design and characterization. Not subject to 100% test. 6 ICS9176C-03 Applications FBOUT is normally connected to FBIN to facilitate input to output skew control. However, there is no requirement that the external feedback connection be a direct hardwire from an output pin to the FBIN pin. As long as the signal at FBIN is drived directly from the FBOUT pin and maintains its frequency, additional delays can be accommodated. The clock phase of the outputs (rising edge) will be adjusted so that the phase of FBIN and ithe input clock will be the same. See Figure 1 for an example. The ICS9176C-03 is also ideal for clocking multi-processor systems. The 10 outputs can be used to synchonize the operation of CPU cache and memory banks operating at different speeds. Figure 2 depicts a 2-CPU system in which processors and associated periperals are operating at 66 MHz. Each of the nine outputs operating at 66 MHz are fully utilized to drive the appropriate CPU, cache and memory control logic. The 33 MHz output is used to synchronize the operation of the slower memory bank to restart of the system. Figure 1 In Figure 1, the propagation delay through the divide by 2 circuit is eliminated. The internal phase-locked loop will adjust the output clock on the ICS9176C-03 to ensure zero phase delay between the FBIN and CLK signals, as a result, the rising edge at the output of the divide by two circuit will be aligned with the rising edge of the 66 MHz input clock. This type of configuration can be used to eliminate propagation delay as long as the signal at FBIN is continuous and is not gated or conditional. Figure 2 7 ICS9176C-03 In Millimeters In Inches SYMBOL COMMON DIMENSIONS COMMON DIMENSIONS MIN MAX MIN MAX A -2.65 -.104 A1 0.10 -.0040 -A2 2.05 2.55 .081 .100 B 0.33 0.51 .013 .020 C 0.18 0.32 .007 .013 SEE VARIATIONS SEE VARIATIONS D E 7.40 7.60 .291 .299 1.27 BASIC 0.050 BASIC e H 10.00 10.65 .394 .419 h 0.25 0.75 .010 .029 L 0.40 1.27 .016 .050 N SEE VARIATIONS SEE VARIATIONS α 0° 8° 0° 8° VARIATIONS N 28 D mm. MIN 17.70 MAX 18.40 MIN .697 D (inch) MAX .724 Reference Doc.: JEDEC Publication 95, MS-013 & MO-119 300 mil (Wide Body) SOIC 10-0031 Ordering Information ICS9176CM-03 Example: ICS XXXX- M PPP Pattern Number (2 or 3 digit number for parts with ROM code patterns) Package Type M=SOIC Device Type (consists of 3 or 4 digit numbers) Prefix ICS = Standard Device 8 ICS reserves the right to make changes in the device data identified in this publication without further notice. ICS advises its customers to obtain the latest version of all device data to verify that any information being relied upon by the customer is current and accurate.