ICS ICS2509C

Integrated
Circuit
Systems, Inc.
ICS2509C
3.3V Phase-Lock Loop Clock Driver
General Description
Features
The ICS2509C is a high performance, low skew, low jitter
clock driver. It uses a phase lock loop (PLL) technology to
align, in both phase and frequency, the CLKIN signal with
the CLKOUT signal. It is specifically designed for use with
synchronous SDRAMs. The ICS2509C operates at 3.3V VCC
and drives up to nine clock loads.
•
One bank of five outputs and one bank of four outputs provide
nine low-skew, low-jitter copies of CLKIN. Output signal
duty cycles are adjusted to 50 percent, independent of the
duty cycle at CLKIN. Each bank of outputs can be enabled or
disabled separately via control (OEA and OEB) inputs. When
the OE inputs are high, the outputs align in phase and
frequency with CLKIN; when the OE inputs are low, the
outputs are disabled to the logic low state.
•
•
•
•
•
•
•
•
Meets or exceeds PC133 registered DIMM
specification 1.1
Spread Spectrum Clock Compatible
Distributes one clock input to one bank of five and one
bank of four outputs
Separate output enable(OEA,OEB) for each output bank
Operating frequency 25 MHz to 175 Mhz
External feedback input (FBIN) terminal is used to
synchrionize the outputs to the clock input
No external RC network required
Operates at 3.3V Vcc
Plastic 24-pin 173mil TSSOP package
The ICS2509C does not require external RC filter
components. The loop filter for the PLL is included on-chip,
minimizing component count, board space, and cost. The
buffer mode shuts off the PLL and connects the input directly
to the output buffer. This buffer mode, the ICS2509C can be
use as low skew fanout clock buffer device. The ICS2509C
comes in 24 pin 173mil Thin Shrink Small-Outline package
(TSSOP) package.
FBOUT
CLKA0
CLKA1
FBIN
CLKIN
PLL
CLKA2
CLKA3
AVCC
CLKA4
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
GND
CLKA3
CLKA4
VCC
OEA
FBOUT
1
2
3
4
5
6
7
8
9
10
11
12
ICS2509C
Pin Configuration
Block Diagram
24
23
22
21
20
19
18
17
16
15
14
13
CLKIN
AVCC
VCC
CLKB0
CLKB1
GND
GND
CLKB2
CLKB3
VCC
OEB
FBIN
OEA
CLKB0
24 Pin TSSOP
4.40 mm. Body, 0.65 mm. pitch
CLKB1
CLKB2
CLKB3
OEB
2509 C Rev C 06/15/01
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.
ICS2509C
Pin Descriptions
PIN NUM BER
1
2, 10, 15
3
4
5
6, 7, 18, 19
8
9
PIN NAM E
AGND
VCC
CLKA0
CLKA1
CLKA2
GND
CLKA3
CLKA4
TYPE
PWR
PWR
OUT
OUT
OUT
PWR
OUT
OUT
11
OEA1
12
13
FBOUT
FBIN
14
OEB 1
16
17
20
21
22
CLKB3
CLKB2
CLKB1
CLKB0
VCC
OUT
OUT
OUT
OUT
PWR
23
AVCC
IN
24
CLKIN
IN
IN
OUT
IN
IN
DESCRIPTION
Analog Ground
Power Supply (3.3V)
Buffered clock output, Bank A
Buffered clock output, Bank A
Buffered clock output, Bank A
Ground
Buffered clock output, Bank A
Buffered clock output, Bank A
Output enable (has internal pull_up). When high, normal operation.
When low bank A clock outputs are disabled to a logic low state.
Feedback output
Feedback input
Output enable (has internal pull_up). When high, normal operation.
When low bank B clock outputs are disabled to a logic low state.
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Buffered clock output. Bank B
Power Supply (3.3V) digital supply.
Analog power supply (3.3V). When input is ground PLL is off and
bypassed.
Clock input
Note:
1. Weak pull-ups on these inputs
Functionality
INPUTS
OEA
OEB
AVCC
0
0
1
1
0
1
0
1
3.33
3.33
3.33
3.33
CLKA
(0:4)
0
0
Driven
Driven
OUTPUTS
CLKB
FBOUT
(0:3)
0
Driven
Driven
Driven
0
Driven
Driven
Driven
Source
PLL
Shutdown
PLL
PLL
PLL
PLL
N
N
N
N
Buffer M ode
0
0
0
0
0
Driven
CLKIN
Y
0
1
0
0
Driven
Driven
CLKIN
Y
1
0
0
Driven
0
Driven
CLKIN
Y
Driven
Driven
1
1
0
Driven
CLKIN
Y
Test mode:
When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers
2
ICS2509C
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . . .
Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . . .
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Ambient Operating Temperature . . . . . . . . . . . .
Storage Temperature . . . . . . . . . . . . . . . . . . . . . .
AVCC < (Vcc + 0.7V)
4.3 V
GND –0.5 V to Vcc +0.5 V
0°C to +70°C
–65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
Electrical Characteristics - OUTPUT
TA = 0 - 70C; VDD = VDDL = 3.3 V +/-10%; CL = 20 - 30 pF; RL = 470 Ohms (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
Output Impedance
RDSP
VO = VDD*(0.5)
36
VO = VDD*(0.5)
32
Output Impedance
RDSN
IOH = -8 mA
2.4
2.9
Output High Voltage
VOH
IOL = 8 mA
0.25
Output Low Voltage
VOL
-26
VOH = 2.4 V
IOH
Output High Current
-37
VOH = 2.0 V
19
25
VOL = 0.8 V
IOL
Output Low Current
13
17
VOL = 0.55 V
Rise Time1
Tr
VOL = 0.8 V, VOH = 2.0 V
0.5
1.4
Fall Time1
Tf
VOH = 2.0 V, VOL = 0.8 V
0.5
1.5
1
Duty Cycle
Dt
VT = 1.5 V;CL=30 pF
45
50
at
66-100
MHz
;
loaded
outputs
52
Tcyc-cyc
Cycle to Cycle jitter1
at 133 MHz ; loaded outputs
39
1
Absolute Jitter
Tjabs
10000 cycles; CL = 30 pF
57
Skew1
Tsk
VT = 1.5 V (Window) Output to Output
80
Phase error1
Tpe
VT = Vdd/2; CLKIN-FBIN
-150
40
3
Phase error Jitter1
Tpe
VT = Vdd/2; CLKIN-FBIN; Delay Jitter
-50
35
Delay Input-Output1
DR1
VT = 1.5 V; PLL_EN = 0
3.3
1
Guaranteed by design, not 100% tested in production.
3
MAX UNITS
0.4
-13.6
-22
Ω
Ω
V
V
mA
mA
2.1
2.7
55
100
75
150
150
50
3.7
ns
ns
%
ps
ps
ps
ps
ps
ns
ICS2509C
Electrical Characteristics - Input & Supply
TA = 0 - 70C; Supply Voltage VDD = 3.3 V +/-10% (unless otherwise stated)
PARAMETER
SYMBOL
CONDITIONS
Input High Voltage
VIH
Input Low Voltage
VIL
Input High Current
IIH
VIN = VDD
Input Low Current
IIL
VIN = 0 V;
Operating current
IDD1
CL = 0 pF; FIN @ 66M
1
Input Capacitance
CIN
Logic Inputs
CO1
Output Capacitance
Logic Outputs
MIN
2
VSS-0.3
TYP
0.1
19
140
4
8
MAX UNITS
VDD+0.3
V
0.8
V
100
uA
50
uA
170
mA
pF
pF
1
Guarenteed by design, not 100% tested in production.
Timing requirements over recommended ranges of supply
voltage and operating free-air temperature
Symbol
Fclk
Parameter
Test Conditions
Input clock frequency
Min.
Max.
Unit
25
175
MHz
Input clock frequency
40
60
%
duty cycle
Stabilization time
After power up
1
ms
Note: Time required for the PLL circuit to obtain phase lock of its feedback signal to its reference
In order for phase lock to be obtained, a fixed-frequency, fixed-phase reference signal must be
Until phase lock is obtained, the specifications for parameters given in the switching characteristics table are not
4
ICS2509C
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
500 Ω
Figure 1. Load Circuit for Outputs
Notes:
Figure 2. Voltage Waveforms
1. CL includes probe and jig capacitance.
Propagation Delay Times
2. All input pulses are supplied by generators having the following
characteristics: PRR ≤ 133 MHz, Z O = 5 0 Ω, Tr ≤ 1.2 ns, Tf ≤ 1.2 ns.
3. The outputs are measured one at a time with one transition per measurement.
Figure 3. Phase Error and Skew Calculations
5
ICS2509C
General Layout Precautions:
An ICS2509C is used as an example. It is similar to the
ICS2510C. The same rules and methods apply.
1) Use copper flooded ground on the top signal layer
under the clock buffer The area under U1 in figure 1
on the right is an example.
2) Use power vias for power and ground. Vias 20 mil or
larger in diameter have lower high frequency
impedance. Vias for signals may be minimum drill
size.
3) Make all power and ground traces are as wide as the
via pad for lower inductance.
4) VAA for pin 23 has a low pass RC filter to decouple
the digital and analog supplies. C9-11 may be replaced
with a single low ESR (0.8 ohm or less) device with
the same total capacitance.
5) Notice that ground vias are never shared.
6) All VCC pins have a decoupling capacitor. Power is
always routed from the plane connection via to the
capacitor pad to the VCC pin on the clock buffer.
7) Component R1 is located at the clock source.
Figure 1.
Component Values:
C1= As necessary for delay adjust
C[7:2]=.01uF
C8,C13=0.1uF
C[11:9]=4.7Uf
R1=10 ohm. Locate at driver
R2=10 ohm.
6
ICS2509C
c
N
L
E1
INDEX
AREA
E
1 2
α
D
A
A2
In Millimeters
SYMBOL COMMON DIMENSIONS
MIN
MAX
A
-1.20
A1
0.05
0.15
A2
0.80
1.05
b
0.19
0.30
c
0.09
0.20
D
SEE VARIATIONS
E
6.40 BASIC
E1
4.30
4.50
e
0.65 BASIC
L
0.45
0.75
N
SEE VARIATIONS
α
0°
8°
aaa
-0.10
VARIATIONS
A1
b
SEATING
PLANE
aaa C
D mm.
N
-Ce
In Inches
COMMON DIMENSIONS
MIN
MAX
-.047
.002
.006
.032
.041
.007
.012
.0035
.008
SEE VARIATIONS
0.252 BASIC
.169
.177
0.0256 BASIC
.018
.030
SEE VARIATIONS
0°
8°
-.004
MIN
7.70
24
D (inch)
MAX
7.90
MIN
.303
MAX
.311
Reference Doc.: JEDEC Publication 95, MO-153
10-0035
4.40 mm. Body, 0.65 mm. pitch TSSOP
(0.0256 Inch)
(173 mil)
Ordering Information
ICS2509CyG-T
Example:
ICS XXXX y G - PPP - T
Designation for tape and reel packaging
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
G=TSSOP
Revision Designator (will not correlate with datasheet revision)
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
7
ICS reserves the right to make changes in the device data identified in
this publication without further notice. ICS advises its customers to
obtain the latest version of all device data to verify that any
information being relied upon by the customer is current and accurate.