SONY ICX285

CXD3607R
Timing Generator for Progressive Scan CCD Image Sensor
Description
The CXD3607R is a timing generator IC which
generates the timing pulses required by Progressive
Scan CCD image sensors as well as signal processing
circuits.
Features
• Base oscillation frequency 57.3MHz
• High-speed/low-speed shutter function
• Supports FINE and DRAFT mode drive
(15 frames/s, 60 frames/s possible)
• Random trigger shutter function
(Supports TRIG and TRIGOUT mode drive)
• Horizontal driver for CCD image sensor
• Vertical driver for CCD image sensor
48 pin LQFP (Plastic)
Absolute Maximum Ratings
• Supply voltage VDDa, b Vss – 0.3 to +7.0
VL
–10.0 to Vss
VH
VL – 0.3 to +26.0
• Input voltage
VI
Vss – 0.3 to VDD + 0.3
Vss – 0.3 to VDD + 0.3
• Output voltage VO1
VO2
VL – 0.3 to Vss + 0.3
VO3
VL – 0.3 to VH + 0.3
• Operating temperature
Topr
–20 to +75
• Storage temperature
Tstg
–55 to +150
Applications
Progressive scan CCD cameras
Structure
Silicon gate CMOS IC
Applicable CCD Image Sensors
ICX285 (Type 2/3, 1450K pixels)
Recommended Operating Conditions
• Supply voltage VDDa
4.75 to 5.25
VDDb
3.0 to 3.6
VM
0.0
VH
14.55 to 15.45
VL
–7.5 to –6.5
• Operating temperature
Topr
–20 to +75
V
V
V
V
V
V
V
°C
°C
V
V
V
V
V
°C
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E01318-PS
CXD3607R
XSHD
XSHP
XCPDM
XCPOB
PBLK
ADCLK
RG
VSS1
H1
H2
VDD1
Block Diagram
16
17
18
19
20
21
10
11
12
13
14
15 VDD2
OSCI
27
28 VDD3
7 VDD4
OSCO
26
24 VSS2
25
CKI
36 VSS3
1 VSS4
Pulse Generator
CKO 23
MCKO 22
38 V1
1/2
39 V4
40 V2A
SSI 29
Register
SCK 30
42 V2B
47 V3
SEN 31
48 SUB
VD 32
V Driver
HD 33
37 VM
41 VH
TRIG 34
3
8
9
SYNSL
TEST1
TEST2
35
WEN
2
RST
45 VL
–2–
CXD3607R
VSS3
WEN
TRIG
HD
VD
SEN
SCK
SSI
VDD3
OSCI
OSCO
CKI
Pin Configuration (Top View)
36
35
34
33
32
31
30
29
28
27
26
25
VH
41
20 PBLK
V2B
42
19 XCPOB
NC
43
18 XCPDM
NC
44
17 XSHP
VL
45
16 XSHD
NC
46
15 VDD2
V3
47
14 VDD1
SUB
48
13 H2
1
2
3
4
5
6
7
8
9
10
11
12
H1
21 ADCLK
VSS1
40
RG
V2A
TEST2
22 MCKO
TEST1
39
VDD4
V4
NC
23 CKO
NC
38
NC
V1
SYNSL
24 VSS2
RST
37
VSS4
VM
∗ Groups of pins enclosed in the figure indicate sections for which power supply separation is possible.
–3–
CXD3607R
Pin Description
Pin
No.
Symbol
I/O
Description
1
VSS4
—
2
RST
I
Internal system reset input. (High: Normal operation, Low: Reset operation)
Normally apply reset during power-on.
3
SYNSL
I
Control input used to switch sync system. (High: CKI sync, Low: MCKO sync)
With pull-down resistor
4
NC
—
(Leave open.)
5
NC
—
(Leave open.)
6
NC
—
(Leave open.)
7
VDD4
—
3.3V power supply. (Power supply for common logic block)
8
TEST1
I
IC test pin 1 (Normally fix to GND.)
9
TEST2
I
IC test pin 2 (Normally fix to GND.)
10
RG
O
CCD reset gate pulse output.
11
VSS1
—
GND (GND for H1 and H2 pins)
12
H1
O
Horizontal CCD drive clock output.
13
H2
O
Horizontal CCD drive clock output.
14
VDD1
—
5.0V power supply. (Power supply for H1 and H2 pins)
15
VDD2
—
3.3V power supply. (Power supply for common logic block)
16
XSHD
O
CCD data level sample-and-hold pulse output.
17
XSHP
O
CCD precharge level sample-and-hold pulse output.
18
XCPDM
O
CCD dummy signal clamp pulse output.
19
XCPOB
O
CCD optical black signal clamp pulse output.
20
PBLK
O
Pulse output for horizontal and vertical blanking period pulse cleaning.
21
ADCLK
O
Clock output for analog/digital conversion IC.
22
MCKO
O
System clock output for signal processing IC. (28.6MHz)
23
CKO
O
Inverter output. (57.3MHz)
24
VSS2
—
GND (GND for common logic block)
25
CKI
I
Inverter input. (57.3MHz)
26
OSCO
O
Inverter output for oscillation. (57.3MHz)
27
OSCI
I
Inverter input for oscillation. (57.3MHz)
28
VDD3
—
29
SSI
I
Serial interface data input for internal mode settings.
30
SCK
I
Serial interface clock input for internal mode settings.
31
SEN
I
Serial interface strobe input for internal mode settings.
32
VD
I
Vertical sync signal input.
33
HD
I
Horizontal sync signal input.
34
TRIG
I
Trigger pulse input.
35
WEN
O
Memory write timing pulse output.
GND (GND for common logic block)
With pull-down resistor
3.3V power supply. (Power supply for common logic block)
–4–
CXD3607R
Pin
No.
Symbol
I/O
Description
36
VSS3
—
GND (GND for common logic block)
37
VM
—
GND (GND for vertical driver)
38
V1
O
CCD vertical register clock output.
39
V4
O
CCD vertical register clock output.
40
V2A
O
CCD vertical register clock output.
41
VH
—
15.0V power supply. (Power supply for vertical driver)
42
V2B
O
CCD vertical register clock output.
43
NC
—
(Leave open.)
44
NC
—
(Leave open.)
45
VL
—
–7.0V power supply. (Power supply for vertical driver)
46
NC
—
(Leave open.)
47
V3
O
CCD vertical register clock output.
48
SUB
O
CCD electronic shutter pulse output.
–5–
CXD3607R
Electrical Characteristics
DC Characteristics
Item
(Within the recommended operating conditions)
Pins
Symbol
Conditions
Min.
Typ.
Max.
Unit
Supply
voltage 1
VDD1
VDDa
4.75
5.0
5.25
V
Supply
voltage 2
VDD2 to 4
VDDb
3.0
3.3
3.6
V
Supply
voltage 3
VH
VH
14.55
15.0
15.45
V
Supply
voltage 4
VM
VM
—
0
—
V
Supply
voltage 5
VL
VL
–7.5
–7.0
–6.5
V
Input
voltage 1∗1
RST, TEST1,
Vt+
SSI, SCK, SEN,
Vt–
VD, HD, TRIG
Input ∗1, ∗2
SYNSL, TEST2
voltage 2
0.8VDDb
0.2VDDb
0.8VDDb
Vt+
XCPDM, XCPOB, VOH1
PBLK, ADCLK,
VOL1
WEN
Feed current where IOH = –3.3mA VDDb – 0.8
Output
voltage 2
XSHD, XSHP,
CKO
VOH2
Feed current where IOH = –6.6mA VDDb – 0.8
VOL2
Pull-in current where IOL = 4.8mA
Output
voltage 3
RG, MCKO
VOH3
Feed current where IOH = –10.4mA VDDb – 0.8
VOL3
Pull-in current where IOL = 7.2mA
Output
voltage 4
H1, H2
VOH4
Feed current where IOH = –22.0mA VDDa – 0.8
VOL4
Pull-in current where IOL = 14.4mA
IOL
V1, V2A, V2B, V3, V4 = –8.25V
VOM1
V1, V2A, V2B, V3, V4 = –0.25V
VOM2
V2A, V2B = 0.25V
VOH
V2A, V2B = 14.75V
IOSL
SUB = –8.25V
IOSH
SUB = 14.75V
Output
current 2
V1, V2A, V2B,
V3, V4
SUB
Pull-in current where IOL = 2.4mA
V
V
0.2VDDb
Vt–
Output
voltage 1
Output
current 1
V
V
V
0.4
V
V
0.4
V
V
0.4
V
V
0.4
10.0
V
mA
–5.0
5.0
mA
mA
–7.2
5.4
mA
mA
–4.0
mA
∗1 These input pins are Schmitt trigger inputs, and have a protective diode on the power supply side in the IC.
Therefore, they do not support 5V input.
∗2 These input pins are with pull-down resistor in the IC.
Note) This table shows the conditions for 3.3V drive.
–6–
CXD3607R
Inverter I/O Characteristics for Oscillation
Item
Pins
(Within the recommended operating conditions)
Symbol
Conditions
Min.
Typ.
Max.
Unit
LVth
—
—
VDDb/2
—
V
VIH
—
0.7VDDb
—
—
V
VIL
—
—
—
0.3VDDb
V
VOH
Feed current where IOH = –9mA
VDDb/2
—
—
V
VOL
Pull-in current where IOL = 9mA
—
—
VDDb/2
V
VIN = VDDb or VSS
500k
2M
5M
Ω
30
—
75
MHz
Logical Vth
OSCI
Input voltage
OSCI
Output voltage
OSCO
Feedback
resistor
OSCI
OSCO
RFB
Oscillator
frequency
OSCI
OSCO
f
—
Inverter Input Characteristics for Base Oscillation Clock Duty Adjustment
(Within the recommended operating conditions)
Item
Pins
Logical Vth
Input voltage
CKI
Symbol
Conditions
Min.
Typ.
Max.
Unit
LVth
—
—
VDDb/2
—
V
VIH
—
0.7VDDb
—
—
V
VIL
—
—
—
0.3VDDb
V
0.3
—
—
Vp-p
VIN
Input amplitude
fmax 75MHz sine wave
Note) Input voltage is the input voltage characteristics for direct input from an external source. Input
amplitude is the input amplitude characteristics in the case of input through a capacitor.
Switching Characteristics
Item
Rise time
Fall time
Output noise
voltage
(VH = 15.0V, VM = GND, VL = –7.0V)
Symbol
Conditions
Min.
Typ.
Max.
Unit
TTLM
VL to VM
200
350
500
ns
TTMH
VM to VH
200
350
500
ns
TTLH
VL to VH
30
60
90
ns
TTML
VM to VL
200
350
500
ns
TTHM
VH to VM
200
350
500
ns
TTHL
VH to VL
30
60
90
ns
VCLH
1.0
V
VCLL
1.0
V
VCMH
1.0
V
VCML
1.0
V
1. The MOS structure of this IC has a low tolerance for static electricity, so full care should be given for
measures to prevent electrostatic discharge.
2. For noise and latch-up countermeasures, be sure to connect a by-pass capacitor (0.1µF or more)
between each power supply pin (VH, VL) and GND.
3. To protect the CCD image sensor, clamp the SUB pin output at VH before input to the CCD image sensor.
See the CCD image sensor data sheet for details.
–7–
CXD3607R
Switching Waveforms
TTMH
TTHM
VH
V2A, V2B
TTLM
90%
90%
10%
10%
TTML
VM
90%
90%
10%
10%
TTML
TTLM
VL
VM
90%
90%
V1, V3, V4
10%
10%
TTLH
TTHL
90%
VL
VH
90%
SUB
10%
10%
VL
Waveform Noise
VM
VCMH
VCML
VCLH
VCLL
VL
–8–
CXD3607R
AC Characteristics
AC characteristics between the serial interface clocks
SSI
0.2VDDb
0.2VDDb
0.8VDDb
0.8VDDb
SSI
0.8VDDb
SCK
0.2VDDb
ts1
SEN
th1
0.2VDDb
ts3
SEN
0.2VDDb
ts2
(Within the recommended operating conditions)
Symbol
ts1
th1
ts2
ts3
Definition
Min.
Typ.
Max.
Unit
SSI setup time, activated by the rising edge of SCK
20
ns
SSI hold time, activated by the rising edge of SCK
20
ns
SCK setup time, activated by the rising edge of SEN
20
ns
SEN setup time, activated by the rising edge of SCK
20
ns
Serial interface clock internal loading characteristics
Example: During FINE mode
HD
0.2VDDb
8H
9H
0.2VDDb
V2
ts1
th1
SCK
0.8VDDb
0.8VDDb
SEN
∗ Be sure to maintain a constantly high SEN logic level from around the falling edge of the HD 8H after the
falling edge of VD to around the 9H falling edge and during that horizontal period.
(Within the recommended operating conditions)
Symbol
Definition
Min.
Typ.
Max.
Unit
ts1
Second SCK clock setup time after the rising edge of SEN,
activated by the falling edge of HD
5
ns
th1
SEN hold time, activated by the falling edge of 9H HD
30
µs
–9–
CXD3607R
Serial interface clock output variation characteristics
The serial interface data “Standby setting” is loaded to the CXD3607R and controlled at the rising edge of the
second SCK clock after the rising edge of SEN.
SEN
0.8VDDb
SCK
Output signal
tpdPULSE
(Within the recommended operating conditions)
Symbol
Definition
Min.
signal delay, activated by the rising edge of the
tpdPULSE Output
second SCK clock after the rising edge of SEN
Typ.
10
Max.
Unit
100
ns
RST loading characteristics
RST
0.2VDDb
0.2VDDb
tw1
(Within the recommended operating conditions)
Symbol
tw1
Definition
Min.
Typ.
Max.
ns
35
RST pulse width
Unit
VD, HD and TRIG loading characteristics
VD/HD/TRIG
0.8VDDb
0.2VDDb
ts1
MCKO
th1
0.2VDDb
0.8VDDb
MCKO load capacitance = 16pF
(Within the recommended operating conditions)
Symbol
Definition
Min.
ts1
th1
VD/HD/TRIG setup time, activated by the rising edge of MCKO
20
ns
VD/HD/TRIG hold time, activated by the rising edge of MCKO
5
ns
– 10 –
Typ.
Max.
Unit
CXD3607R
Output variation characteristics
MCKO
0.8VDDb
WEN
tpd1
WEN load capacitance = 10pF
(Within the recommended operating conditions)
Symbol
tpd1
Min.
Definition
Time until WEN changes after the rise of MCKO
– 11 –
–6
Typ.
Max.
Unit
0
ns
CXD3607R
Description of Operation
Pulses output from the CXD3607R are controlled mainly by the RST and SYNSL pins and by the serial
interface data.
Control by the RST Pin
System reset is performed by setting the CXD3607R RST pin (Pin 2) low. After reset is canceled, the serial
data block is “XSHP, XSHD logic phase adjustment setting” D0 bit = 1 and all other bits = 0.
In addition, when RST = low, some circuit operations in the IC are stopped as shown in the Pin Status Table
below.
Pin Status Table (RST = low)
Pin No.
Symbol
I/O status
Pin No.
Symbol
I/O status
1
VSS4
—
25
CKI
ACT
2
RST
L
26
OSCO
ACT
3
SYNSL
ACT
27
OSCI
ACT
4
NC
—
28
VDD3
—
5
NC
—
29
SSI
DIS
6
NC
—
30
SCK
DIS
7
VDD4
—
31
SEN
DIS
8
TEST1
—
32
VD
DIS
9
TEST2
—
33
HD
DIS
10
RG
ACT
34
TRIG
DIS
11
VSS1
—
35
WEN
L
12
H1
ACT
36
VSS3
—
13
H2
ACT
37
VM
—
14
VDD1
—
38
V1
VL
15
VDD2
—
39
V4
VL
16
XSHD
ACT
40
V2A
VM
17
XSHP
ACT
41
VH
—
18
XCPDM
H
42
V2B
VM
19
XCPOB
H
43
NC
—
20
PBLK
H
44
NC
—
21
ADCLK
ACT
45
VL
—
22
MCKO
ACT
46
NC
—
23
CKO
ACT
47
V3
VM
24
VSS2
—
48
SUB
VL
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled status.
VM and VL indicate the voltage levels applied to VM (Pin 37) and VL (Pin 45), respectively.
– 12 –
CXD3607R
Control by the SYNSL Pin
The CXD3607R sync system can be switched by the CXD3607R SYNSL pin (Pin 3).
Low: MCKO sync (Normally use with this system configuration.)
Select this when sync signals VD and HD are generated by the MCKO output of the CXD3607R. The VD
and HD inputs are loaded to the CXD3607R at the rising edge of the MCKO pulse.
High: CKI sync
Select this when sync signals VD and HD are generated by the CKI input of the CXD3607R. The VD and
HD inputs are loaded to the CXD3607R at the rising edge of the CKI pulse, and the two MCKO logic
phases (a) and (b) existing after power-on can be aligned at the initial HD input by resetting the internal
clock.
Low: MCKO sync
High: CKI sync
High: MCKO reset for CKI sync
CKI
CKI
HD
MCKO
CXD3607R
Sync signal
generator block
CKI
Sync signal
generator block
CXD3607R
VD/HD
VD/HD
MCKO (a)
MCKO (b)
Control by the Serial Interface Data
The CXD3607R loads the serial interface data in the following format at the rising edge of the second SCK
clock after the rising edge of SEN.
∗ Make sure that SCK does not stop even while SEN is high.
SSI
SD11 SD10 SD9
SD8
SD7
SD6
SD5
SD4
SD3
SD2
SD1
SD0
SCK
SEN
In addition, the data are actually reflected at the following positions.
→ Reflected at the falling edge of the HD 8H after the falling
edge of VD.
2. Special drive data “SUB stop setting” → Reflected at the falling edge of the HD 9H after the falling
edge of VD.
4. Shutter data “Shutter SUB setting”
→ Reflected at the falling edge of the HD 9H after the falling
edge of VD.
5. TRIG data
→ Reflected at the falling edge of the HD 1H after the falling
edge of TRIG.
(Only when the TRIG function setting is 1: TRIG function
enabled)
6. Other data “Standby setting”
→ Reflected at the rising edge of the second SCK clock after
the rising edge of SEN.
Data other than the following
There are six categories of serial interface data: drive mode data, special drive data, logic phase adjustment
data, shutter data, TRIG data and other data. The details of the data for each category are described below.
∗ After reset is canceled, the serial data block is “XSHP, XSHD logic phase adjustment setting” D0 bit = 1 and
all other bits = 0.
– 13 –
CXD3607R
1. Drive mode data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
0
1
1
1
0
1
1
0
X
D2
D1
D0
Description of settings
Drive mode setting, TRIG
function setting
2. Special drive data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
0
0
1
0
1
0
X
X
X
X
D1
D0
Description of settings
SG and SUB stop settings
3. Logic phase adjustment data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
0
1
0
Description of settings
1
1
D1
D0
0
0
0
0
0
XSHP logic phase adjustment
setting
0
0
D1
D0
0
0
0
0
0
XSHD logic phase adjustment
setting
0
1
D1
D0
0
0
0
0
0
ADCLK logic phase adjustment
setting
1
4. Shutter data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
1
1
0
1
1
0
0
0
D5
D4
D3
D2
D1
D0
1
D11
D10
D9
D8
D7
D6
0
D5
D4
D3
D2
D1
D0
1
D11
D10
D9
D8
D7
D6
Description of settings
Shutter V setting
Shutter SUB setting
5. TRIG data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
0
0
1
1
1
1
1
0
0
D3
D2
D1
D0
0
1
D3
D2
D1
D0
1
0
D7
D6
D5
D4
1
1
X
D10
D9
D8
0
D3
D2
D1
D0
1
D7
D6
D5
D4
0
Description of settings
SG and SUB stop settings
High-speed sweep setting
Clamp pulse stop setting
SG generation position setting
SUB setting
6. Other data
SD11 SD10 SD9 SD8 SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0
1
1
1
1
1
0
0
X
X
– 14 –
X
X
D0
Description of settings
Standby setting
CXD3607R
Detailed Description of each Data
1. Drive mode data
(1) Drive mode setting
The CXD3607R drive mode can be switched as follows.
∗ TRIGOUT mode is the mode which stops the SG pulse (ternary value output of the V2A and V2B pulses)
and the corresponding V pulse of FINE mode. Note that this is different from the special drive data “SG
stop setting”.
D1
D0
Description of operation
0
0
DRAFT mode
0
1
FINE mode
1
X
TRIGOUT mode
(2) TRIG function setting (valid in DRAFT, FINE and TRIGOUT modes)
The CXD3607R random trigger shutter function disabled/enabled setting can be switched as follows.
∗ For details, see “Special Drive Sequence (Random trigger shutter drive)”.
D2
Description of operation
0
TRIG function disabled
1
TRIG function enabled
2. Special drive data
(1) SG stop setting (valid in DRAFT and FINE modes)
SG pulse (ternary value output of the V2A and V2B pulses) stopped/not stopped can be selected by the
D0 setting.
∗ When SG stopped is selected, the corresponding V pulse is not stopped.
∗ When SG stopped is selected, WEN becomes inactive during that VD period.
D0
Description of operation
0
SG not stopped
1
SG stopped
(2) SUB pulse stop setting (valid in DRAFT, FINE and TRIGOUT modes)
SUB pulse stopped/not stopped can be selected by the D1 setting.
D1
Description of operation
0
SUB not stopped
1
SUB stopped
– 15 –
CXD3607R
3. Logic phase adjustment data
(1) XSHP and XSHD logic phase adjustment setting
The XSHP and XSHD logic phase adjustment can be selected by the D1 and D0 setting.
∗ The default when reset is 90°.
∗ For details, see the high-speed phase timing chart.
D1
D0
Description of operation
0
0
0°
0
1
90° (default)
1
0
180°
1
1
270°
(2) ADCLK logic phase adjustment setting
The ADCLK logic phase adjustment can be selected by the D1 and D0 setting.
∗ The default when reset is 0° (pulse delayed 90° relative to MCKO).
∗ For details, see the high-speed phase timing chart.
D1
D0
Description of operation
0
0
0° (default)
0
1
90°
1
0
180°
1
1
270°
– 16 –
CXD3607R
4. Shutter data
(1) Shutter V setting (valid in DRAFT and FINE modes)
The SG stopped VD period, that is to say the exposure time, can be adjusted from 0 to 4095V in 1V units
by the D11 to D0 setting. Setting all 0 results in the high-speed shutter corresponding to the shutter SUB
setting.
∗ During the SG stopped VD period, data other than 5. TRIG data and 6. Other data are not reflected.
∗ During the SG stopped VD period, only the SG pulse is stopped, and the corresponding V pulse is not
stopped.
∗ During the SG stopped VD period, PBLK, XCPOB and XCPDM are active, and WEN is inactive.
The SG stopped VD period (V) for each serial setting value and the shutter V setting outline diagrams (for
SG stopped VD periods 0V and 1V) are shown below.
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SG stopped VD period (V)
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
2
:
:
1
1
1
1
1
1
1
1
1
1
1
0
4094
1
1
1
1
1
1
1
1
1
1
1
1
4095
Shutter V setting: 0V = high-speed shutter
VD
V2A
SUB
Exposure time
Serial data
reflected
Shutter V setting: 1V
VD
V2A
SUB
Exposure time
Serial data
reflected
– 17 –
CXD3607R
(2) Shutter SUB setting (valid in DRAFT, FINE and TRIGOUT modes)
The charge drain period by the SUB pulse can be adjusted from 1 to 4095H in 1H units by the D11 to D0
setting. The number of SUB pulses for each serial setting value is shown below.
∗ Setting values in excess of the maximum number of pulses per VD period (example: 1068 pulses for
VD = 1068H) are fixed to the maximum number of pulses.
∗ When performing long-time exposure with the shutter V setting, setting values in excess of the maximum
number of pulses per VD period are fixed to the maximum number of pulses.
∗ Setting all 1 results in all SUB output (ALL), for any VD period.
D11 D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
Number of SUB pulses
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
0
0
0
0
1
1
3
:
:
1
1
1
1
1
1
1
1
1
1
0
1
4093
1
1
1
1
1
1
1
1
1
1
1
0
4094
1
1
1
1
1
1
1
1
1
1
1
1
All
1H
2H
3H
HD
V2A
Shutter SUB setting
0
1
2
3
:
4093
4094
4095
(All)
– 18 –
4H
4094H
4095H 4096H to
CXD3607R
5. TRIG data
(1) SG stop setting (valid only during TRIG drive)
SG pulse (ternary value output of the V2A and V2B pulses) stopped/not stopped during TRIG drive can be
selected by the D0 setting.
∗ When SG stopped is selected, the corresponding V pulse is not stopped.
D0
Description of operation
0
SG not stopped (TRIG drive)
1
SG stopped (TRIG drive)
(2) SUB stop setting (valid only during TRIG drive)
SUB pulse stopped/not stopped during TRIG drive can be selected by the D1 setting.
D1
Description of operation
0
SUB not stopped (TRIG drive)
1
SUB stopped (TRIG drive)
(3) High-speed sweep setting (valid only during TRIG drive)
High-speed sweep on/off during TRIG drive can be selected by the D2 setting.
(For details, see Chart-4 to Chart-7.)
D2
Description of operation
0
High-speed sweep on (TRIG drive)
1
High-speed sweep off (TRIG drive)
∗ The number of V transfers (stages) for high-speed sweep differs according to the drive mode during
TRIG pulse input.
(For details, see Chart-12 and Chart-13.)
DRAFT mode: 20 (stages/H) × 53 (H) = 1060 (stages)
FINE/TRIGOUT mode: 5 (stages/H) × 210 (H) = 1050 (stages)
(4) Clamp pulse stop setting (valid only during TRIG drive)
XCPDM, XCPOB and PBLK stopped/not stopped from SG pulse generation until 7H after the falling edge
of the next valid VD during TRIG drive can be selected by the D3 setting.
(For details, see Chart-4 to Chart-7.)
D3
Description of operation
0
Clamp pulses not stopped (TRIG drive)
1
Clamp pulses stopped (TRIG drive)
– 19 –
CXD3607R
(5) SG generation position setting (valid only during TRIG drive)
The SG pulse (ternary value output of the V2A and V2B pulses) generation position during TRIG drive can
be selected from 2 to 2048H counting from the next HD after the falling edge of the TRIG pulse by the D10
to D0 setting. The SG generation position (H) for each serial setting value is shown below.
(For details, see Chart-4 to Chart-7.)
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
SG generation position (H)
0
0
0
0
0
0
0
0
0
0
0
2
0
0
0
0
0
0
0
0
0
0
1
2
0
0
0
0
0
0
0
0
0
1
0
3
0
0
0
0
0
0
0
0
0
1
1
4
:
:
1
1
1
1
1
1
1
1
1
0
1
2046
1
1
1
1
1
1
1
1
1
1
0
2047
1
1
1
1
1
1
1
1
1
1
1
2048
∗ When high-speed sweep is on, a SG generation prohibited area exists. When this area is designated, the SG
pulse is generated at the position indicated below. When the drive mode during TRIG pulse input is:
DRAFT mode: When the prohibited area 2 to 57H is designated, the SG pulse is generated at 58H.
FINE/TRIGOUT mode: When the prohibited area 2 to 214H is designated, the SG pulse is
generated at 215H.
∗ VD input is not accepted until 2H after the SG generation position (H), and is accepted from 3H onward.
(Example: When the SG generation position is 58H, VD input is not accepted from 1 to 59H, and is
accepted from 60H onward.)
(6) SUB setting (valid only during TRIG drive)
The number of SUB pulses during TRIG drive can be selected by the D7 to D0 setting. The number of
SUB pulses for each serial setting value is shown below.
D7
D6
D5
D4
D3
D2
D1
D0
Number of SUB pulses
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
3
:
:
1
1
0
1
0
1
0
1
213
1
1
0
1
0
1
1
0
214
1
1
0
1
0
1
1
1
215
∗ When high-speed sweep is off, the number of SUB pulses is two regardless of the drive mode during
TRIG pulse input and the SUB setting value.
∗ When high-speed sweep is on, the maximum number of SUB pulses is as follows according to the drive
mode during TRIG pulse input. Setting values in excess of the maximum number of pulses are fixed to
the maximum number of pulses. (For details, see Chart-4 to Chart-7.)
DRAFT mode: Max. 58 pulses
FINE/TRIGOUT mode: Max. 215 pulses
– 20 –
CXD3607R
6. Other data
(1) Standby setting
Standby operation can be selected by the D0 setting. The Pin Status Table during standby operation is
shown below.
∗ The standby setting bit is loaded at the rising edge of the second SCK clock after the rising edge of
SEN, and control is applied immediately.
∗ Serial data is loaded as normal during standby operation.
D0
Description of operation
0
Normal operation
1
Standby operation
Pin Status Table (Standby setting bit = 1)
Pin No.
Symbol
I/O status
Pin No.
Symbol
I/O status
1
VSS4
—
25
CKI
ACT
2
RST
ACT
26
OSCO
ACT
3
SYNSL
ACT
27
OSCI
ACT
4
NC
—
28
VDD3
—
5
NC
—
29
SSI
ACT
6
NC
—
30
SCK
ACT
7
VDD4
—
31
SEN
ACT
8
TEST1
—
32
VD
DIS
9
TEST2
—
33
HD
DIS
10
RG
L
34
TRIG
DIS
11
VSS1
—
35
WEN
L
12
H1
L
36
VSS3
—
13
H2
L
37
VM
—
14
VDD1
—
38
V1
VM
15
VDD2
—
39
V4
VM
16
XSHD
L
40
V2A
VH
17
XSHP
L
41
VH
—
18
XCPDM
L
42
V2B
VH
19
XCPOB
L
43
NC
—
20
PBLK
L
44
NC
—
21
ADCLK
L
45
VL
—
22
MCKO
ACT
46
NC
—
23
CKO
ACT
47
V3
VM
24
VSS2
—
48
SUB
VH
Note) ACT means that the circuit is operating, and DIS means that loading is stopped.
L indicates a low output level, and H a high output level in the controlled state.
VM and VL indicate the voltage levels applied to VM (Pin 37) and VL (Pin 45), respectively.
– 21 –
CXD3607R
Detailed Description of Output Pins
The CXD3607R generates special pulses that are used by signal processing circuits, etc. These details are
described below.
• WEN (Pin 30)
The CXD3607R outputs a WEN signal that indicates the effective line period output from the CCD image
sensor. The WEN signal is high during the vertical effective line period. For details, see the vertical timing
charts for each drive mode.
∗ When SG stopped is selected by the SG stop setting, WEN is inactive during the SG stopped VD period.
∗ When performing long-time exposure with the shutter V setting, WEN is inactive during the SG stopped VD
period.
Special Drive Sequence (Random trigger shutter drive)
Cameras using the CXD3607R can perform random trigger shutter drive which allows image capturing at an
optional timing. The TRIG pulse is loaded from the TRIG pin at the rising edge of MCKO, and reflected from the
falling edge of the next HD.
The random trigger shutter drive sequence in DRAFT mode is shown below.
(1)
TRIG
Not accepted
VD
Not accepted
HD
Mode
DRAFT
DRAFT (TRIG function enabled)
TRIGOUT
DRAFT
(4) SG generation position setting
(6) SG and V pulse stopped
(2) High-speed sweep setting
V2A
(3) SUB setting
SUB
Exposure A
CCDOUT
Exposure B
Exposure A
(part-way)
Main exposure
None
Exposure C
Main exposure
(5) Clamp pulse stop setting
XCPOB, XCPDM
– 22 –
Exposure
Exposure C
CXD3607R
(1) If the drive mode data “TRIG function setting” is 1: Enabled at the falling edge of the TRIG pulse, operation
switches to TRIG drive.
∗ Operation cannot be guaranteed for a TRIG pulse low-active period of 2H or less.
∗ The TRIG pulse is valid when input with the falling edge synchronized to the falling edge of VD.
∗ The TRIG pulse is not accepted after switching to TRIG drive.
∗ The VD pulse is not accepted for until 2H after SG generation after switching to TRIG drive. Serial data is
also not reflected by the falling edge of VD during this period. (Example: When SG is generated at 58H,
VD is not accepted from 1 to 59H)
(2) Operation switches to TRIG drive mode and high-speed sweep for vertical register block charge drain
starts from the falling edge of the next HD after the falling edge of the input TRIG pulse. The number of
high-speed sweep stages differs according to the drive mode at the falling edge of the TRIG pulse as
follows. DRAFT: 20 (stages/H) × 53 (H) = 1060 (stages), FINE/TRIGOUT: 5 (stages/H) × 210 (H) = 1050
(stages). High-speed sweep off can also be selected by the TRIG data “High-speed sweep setting”.
(3) The charge drain period using the SUB pulse can be selected by the TRIG data “SUB setting”.
When high-speed sweep is on, the maximum number of SUB pulses is as follows according to the drive
mode at the falling edge of the TRIG pulse. DRAFT: max. 58 pulses, FINE/TRIGOUT: max. 215 pulses.
When high-speed sweep is off, the number of SUB pulses is two regardless of the drive mode at the falling
edge of the TRIG pulse and the SUB setting value.
(4) The SG pulse generation position can be selected by the TRIG data “SG generation position setting”. After
SG pulse output, V transfer is not performed and standby mode is established until the next VD input.
(5) The clamp pulses can also be stopped after SG pulse generation by the TRIG data “Clamp pulse stop
setting”.
(6) Be sure to drive in TRIGOUT mode during the next VD period after TRIG drive. (Operation in other modes
can be not guaranteed.)
∗ TRIG drive ends at the first VD input 3H onward after SG pulse generation. Even when operation shifted
to TRIG drive during long-time exposure using the “Shutter V setting”, note that serial data is always
reflected at the first VD input 3H onward after SG pulse generation.
Specifications for Each Drive Mode and A Table Corresponding Timing Charts
Drive mode
Total
High-speed Number of highFrame
number
sweep H
speed sweep
rate (s)
of HD (H) period (H) stages (stage)
Vertical
timing
chart
Readout Normal
High-speed
block H transfer block sweep block
chart
H chart
H chart
DRAFT
1/60
267
0
0
Chart-1
Chart-8
Chart-9
—
FINE
1/15
1068
0
0
Chart-2 Chart-10
Chart-11
—
TRIGOUT
1/15
1068
0
0
Chart-3
Chart-11
—
DRAFT → TRIG
(high-speed
sweep on)
—
—
53
(fixed)
1060
(fixed)
Chart-4 Chart-10
—
Chart-12
DRAFT → TRIG
(high-speed
sweep off)
—
—
0
0
Chart-5 Chart-10
—
—
FINE/TRIGOUT
→ TRIG
(high-speed
sweep on)
—
—
210
(fixed)
1050
(fixed)
Chart-6 Chart-10
—
Chart-13
FINE/TRIGOUT
→ TRIG
(high-speed
sweep off)
—
—
0
0
Chart-7 Chart-10
—
—
– 23 –
—
Readout block (Chart-8)
DRAFT
260H
TRIG function disabled
Normal transfer block (Chart-9)
1/60s
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MODE
DRAFT mode
∗ The number of SUB pulses is determined by the serial interface data.
DRAFT
TRIG function setting TRIG function disabled
Drive mode setting
OUT
WEN
PBLK
XCPDM
XCPOB
SUB
V4
V3
V2B
V2A
V1
HD
1033
1
1
9
17
25
33
41
49
57
65
73
81
VD
1025
1028
1036
1
4
4
12
20
28
36
44
52
60
68
76
84
89
92
Chart-1 Vertical Timing Chart
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
TRIG function disabled
DRAFT
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
– 24 –
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
977
980
985
988
993
996
1001
1004
1009
1012
1017
1020
1025
1028
1033
1036
1
1
4
1
4
9
12
17
20
25
28
33
36
41
44
49
52
57
60
CXD3607R
FINE
1040H
TRIG function disabled
Readout block (Chart-10) Normal transfer block (Chart-11)
∗ The number of SUB pulses is determined by the serial interface data.
FINE
TRIG function setting TRIG function disabled
Drive mode setting
OUT
WEN
PBLK
XCPDM
XCPOB
SUB
V4
V3
V2B
V2A
V1
HD
VD
1/15s
FINE mode
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MODE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1033
1034
1035
1036
1037
1038
1039
1040
1
2
Chart-2 Vertical Timing Chart
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
TRIG function disabled
FINE
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
– 25 –
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
1
2
3
4
5
CXD3607R
Normal transfer block (Chart-11)
TRIG function disabled
TRIGOUT
1040H
∗ The number of SUB pulses is determined by the serial interface data.
TRIGOUT
TRIG function setting TRIG function disabled
Drive mode setting
OUT
WEN
PBLK
XCPDM
XCPOB
SUB
V4
V3
V2B
V2A
V1
HD
VD
1/15s
TRIGOUT mode
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
MODE
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1033
1034
1035
1036
1037
1038
1039
1040
1
2
Chart-3 Vertical Timing Chart
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
TRIG function disabled
TRIGOUT
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
– 26 –
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
1
2
3
4
5
CXD3607R
MODE
DRAFT mode → TRIG drive
(High-speed sweep on, SG generation position: 58H, SUB setting: 58 pulses)
Chart-4 Vertical Timing Chart
∗ The VD fall is not accepted until 2H after SG generation.
TRIG
(Example: When the SG generation position is 58H, VD input is not accepted from 1 to 59H, and is accepted from 60H onward.)
VD
High-speed sweep block (Chart-12)
Fixed to 53H (20 stages × 53H = 1060 stages)
Readout block (Chart-10)
240
241
242
243
244
245
246
247
248
249
250
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
50
51
52
53
54
55
56
57
58
59
60
61
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
HD
Selectable in the range of 58 to 2048H by the
SG generation position setting. (Example: 58H)
V1
SG prohibited area (1 to 57H)
V2A
V2B
V3
SUB
Selectable from 1 to 58 pulses by the SUB setting. (Example: 58 pulses)
XCPOB
XCPDM
PBLK
These pulses can be stopped by
the clamp pulse stop setting.
49
Drive mode setting
DRAFT
240
241
242
243
244
245
246
247
248
249
250
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
DRAFT
TRIGOUT
TRIG function enabled
TRIG function disabled
∗ The number of SUB pulses is determined by the serial interface data.
CXD3607R
TRIG fuction setting TRIG function disabled
50
51
52
53
54
55
56
57
58
59
60
61
1
2
3
4
5
6
7
8
1
2
3
4
5
52
41
44
33
36
25
28
17
20
9
12
1
4
1
4
1
1033
1036
1028
OUT
1025
WEN
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
– 27 –
V4
MODE
DRAFT mode → TRIG drive
(High-speed sweep off, SG generation position: 2H, SUB setting: fixed to 2 pulses)
Chart-5 Vertical Timing Chart
∗ The VD fall is not accepted until 2H after SG generation.
TRIG
(Example: When the SG generation position is 2H, VD input is not accepted from 1 to 3H, and is accepted from 4H onward.)
VD
Readout block (Chart-10)
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
HD
Selectable in the range of 2 to 2048H by the
SG generation position setting. (Example: 2H)
V1
V2A
V2B
V3
SUB
Fixed to two pulses regardless of the SUB setting.
XCPOB
XCPDM
PBLK
These pulses can be stopped by the clamp pulse stop setting.
49
Drive mode setting
DRAFT
DRAFT
TRIG function enabled
∗ The number of SUB pulses is determined by the serial interface data.
TRIGOUT
TRIG function disabled
CXD3607R
TRIG fuction setting TRIG function disabled
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
1
2
3
4
5
52
41
44
33
36
25
28
17
20
9
12
1
4
1
4
1
1033
1036
1028
OUT
1025
WEN
260
261
262
263
264
265
266
267
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
– 28 –
V4
Chart-6 Vertical Timing Chart
MODE
FINE/TRIGOUT mode → TRIG drive
(High-speed sweep on, SG generation position: 215H, SUB setting: 215 pulses)
∗ The VD fall is not accepted until 2H after SG generation.
TRIG
(Example: When the SG generation position is 215H, VD input is not accepted from 1 to 216H, and is accepted from 217H onward.)
High-speed sweep block (Chart-13)
Fixed to 210H (5 stages × 210H = 1050 stages)
207
208
209
210
211
212
213
214
215
216
217
218
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
HD
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
VD
Readout block (Chart-10)
Selectable in the range of 215 to 2048H by the
SG generation position setting. (Example: 215H)
V1
SG prohibited area (1 to 214H)
V2A
V2B
V4
SUB
Selectable from 1 to 215 pulses by the SUB setting. (Example: 215 pulses)
XCPOB
XCPDM
PBLK
These pulses can be stopped by
the clamp pulse stop setting.
Drive mode setting
FINE
TRIG fuction setting TRIG function disabled
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
207
208
209
210
211
212
213
214
215
216
217
218
1
2
3
4
5
6
7
8
1
2
3
4
5
OUT
1
2
3
4
5
6
7
8
1
2
3
4
5
WEN
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
– 29 –
V3
FINE
TRIGOUT
TRIG function enabled
TRIG function disabled
CXD3607R
∗ The number of SUB pulses is determined by the serial interface data.
MODE
FINE/TRIGOUT mode → TRIG drive
Chart-7 Vertical Timing Chart
(High-speed sweep off, SG generation position: 2H, SUB setting: fixed to 2 pulses)
∗ The VD fall is not accepted until 2H after SG generation.
TRIG
(Example: When the SG generation position is 2H, VD input is not accepted from 1 to 3H, and is accepted from 4H onward.)
VD
Readout block (Chart-10)
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
HD
Selectable in the range of 2 to 2048H by the
SG generation position setting. (Example: 2H)
V1
V2A
V2B
V3
SUB
Fixed to two pulses regardless of the SUB setting.
XCPOB
XCPDM
PBLK
These pulses can be stopped by the clamp pulse stop setting.
WEN
Drive mode setting
FINE
TRIG fuction setting TRIG function disabled
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
1
2
3
4
5
1
2
3
4
5
6
7
8
1
2
3
4
5
OUT
1061
1062
1063
1064
1065
1066
1067
1068
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
1
2
3
4
5
6
7
8
9
10
– 30 –
V4
FINE
TRIGOUT
TRIG function enabled
TRIG function disabled
CXD3607R
∗ The number of SUB pulses is determined by the serial interface data.
MODE
DRAFT mode readout block
Chart-8 Horizontal Timing Chart
(1790)
0
50
100
150
200
250
300
350
400
800
850
900
950
1000
1050
(1790)
0
50
1H
HD
0
180
1790
MCKO
OUT
OB (40)
4
OB (40)
DM (20)
43
380 400 402
43
380
43
43
380
43
4
43
H1
H2
V1
66
118
150
234
202
286
318
801
V2A
55
87
1011
804
1063
66
906
– 31 –
139
171
223
255
307 339
1000 1032
55
87
139
171
223
255
307 339
1000 1032
55
87
V2B
55
87
V3
76
108
160
192
244
276
328
360
1021 1053
76
V4
45
97
129
181
213
265
297
990
349
1042
45
97
SUB
150
276
PBLK
XCPOB
XCPDM
382
398
WEN
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
MODE
DRAFT mode normal transfer block
Chart-9 Horizontal Timing Chart
(1790)
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
(1790)
0
50
2H to
HD
0
180
1790
MCKO
OUT
OB (40)
4
DM (20)
OB (40)
43
380 400 402
43
380
43
43
380
43
4
43
H1
H2
V1
66
150
118
202
234
286
318
370
66
V2A
– 32 –
55
87
139
171
223
255
307
339
55
87
55
87
139
171
223
255
307
339
55
87
V2B
V3
108
76
160
192
244
276
328
360
76
V4
45
97
129
181
213
265
297
45
349
97
SUB
276
150
PBLK
44
44
400
XCPOB
12
42
12
42
XCPDM
382 398
WEN
211
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
MODE
Chart-10 Horizontal Timing Chart
FINE mode readout block
(1790)
0
50
100
150
200
250
300
350
400
800
850
900
950
1000
1050
(1790)
0
50
1H
HD
0
180
1790
MCKO
OUT
OB (40)
4
OB (40)
DM (20)
4
43
43
380 400 402
43
380
43
43
380
43
H1
H2
V1
129
804
V2A
– 33 –
87
801
906
801
906
213
87
V2B
87
213
87
V3
171
297
V4
45
255
45
SUB
150
276
PBLK
XCPOB
XCPDM
382 398
WEN
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
Chart-11 Horizontal Timing Chart
(1790)
0
50
100
MODE
FINE/TRIGOUT mode normal transfer block
150
200
250
300
350
400
450
500
550
600
650
700
(1790)
0
50
2H to
HD
0
180
1790
MCKO
OUT
OB (40)
4
DM (20)
OB (40)
43
380 400 402
43
380
43
43
380
43
4
43
H1
H2
V1
129
339
V2A
– 34 –
87
213
87
87
213
87
V2B
V3
171
297
V4
45
255
45
SUB
276
150
PBLK
44
44
400
XCPOB
12
42
12
42
XCPDM
382 398
WEN
211
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
Chart-12 Horizontal Timing Chart
(1790)
0
50
MODE
DRAFT mode → TRIG drive high-speed sweep block
After the fall of TRIG
100
150
200
250
300
350
400
450
500
1600
1650
1700
1750
(1790)
0
50
1H to
HD
180
0
1790
MCKO
OUT
OB (40)
4
OB (40)
DM (20)
43
380 400 402
43
380
4
43
H1
43
H2
43
V1
#1
66
#2
#3
150
118
202
380
#4
234
286
318
370
#5
#19
454
402
486
43
#20
1578
1630
1662
1714
#1
66
V2A
– 35 –
55
87
139
171
223
255
307 339
391
423
475
1567 1599
1651
1683
55
87
55
87
139
171
223
255
307 339
391
423
475
1567 1599
1651
1683
55
87
V2B
V3
108
76
160
192
244
276
328
360
412
444
1588
496
1620
1672
1704
76
V4
45
97
129
181
213
265 297
349
381
433
465
1557
1609 1641
1693
45
97
SUB
150
276
PBLK
44
XCPOB
12
42
XCPDM
WEN
211
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
MODE
FINE/TRIGOUT mode → TRIG drive high-speed sweep block
Chart-13 Horizontal Timing Chart
(1790)
0
50
After the fall of TRIG
100
150
200
250
300
350
400
450
500
550
1650
1700
1750
(1790)
0
50
1H to
HD
0
180
1790
MCKO
OUT
OB (40)
4
OB (40)
DM (20)
43
380 400 402
43
380
4
43
H1
43
H2
43
380
#1
#2
#5
43
#1
V1
129
339
465
1683
V2A
– 36 –
87
213
423
549
87
87
213
423
549
87
V2B
V3
171
507
297
1641
V4
45
255
381
45
SUB
150
276
PBLK
44
XCPOB
12
42
XCPDM
WEN
211
CXD3607R
∗ The HD of this chart indicates the actual CXD3607R load timing.
∗ The numbers at the output pulse transition points indicate the count at the MCKO rise from the fall of HD.
Chart-14 High-Speed Phase Timing Chart
MODE
DRAFT/FINE/TRIGOUT mode
HD
HD'
CKI
CKO
1
2
3
4
5
6
7
40
41
42
43
44
45
46
377
378
379
380
381
382
MCKO
– 37 –
H1
H2
RG
XSHP
(Logical phase 90˚)
XSHD
(Logical phase 90˚)
ADCLK
(Logical phase 0˚)
CXD3607R
∗ HD’ indicates the HD which is the actual CXD3607R load timing. (when MCKO sync is selected)
∗ The phase relationship of each pulse shows the logical position relationship. For the actual output waveform, a delay is added to each pulse.
∗ The logical phases of XSHP, XSHD and ADCLK can be specified by the serial interface data.
CXD3607R
Application Circuit Block Diagram
Digital OUT
CCD OUT
V2B
V3
V4
SUB
ADCLK
PBLK
XCPOB
XCPDM
10
35
38
32
TG
CXD3607R
40
33
34
42
MCKO
CKO
Signal
Processor
Block
WEN
VD
HD
TRIG
V-Dr
47
2
RST
39
3
SYNSL
48
OSCI
OSCO
CKI
25 26 27
8
9
29 30 31
SEN
V2A
23
SCK
V1
13
SSI
RG
22
TEST2
H2
16 17 18 19 20 21
12
TEST1
H1
XSHP
CDS/ADC Block
XSHD
CCD
ICX285
Controller
This block diagram shows the connection relationship with each block, and is not an actual circuit diagram.
See the CCD image sensor data sheet for a concrete example of circuit connection with a CCD image sensor.
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for
any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
Notes for Power-on
Of the four –7.0V, +15.0V, +3.3V, +5.0V power supplies, be sure to start up the –7.0V and +15.0V power
supplies in the following order to prevent the SUB pin of the CCD image sensor from going to negative
potential.
15V
t1
20%
0V
20%
t2
–7.0V
t2 ≥ t1
– 38 –
CXD3607R
Package Outline
Unit: mm
48PIN LQFP (PLASTIC)
9.0 ± 0.2
∗
7.0 ± 0.1
36
S
25
13
48
B
(0.22)
0.5 ± 0.2
A
(8.0)
24
37
12
1
+ 0.05
0.127 – 0.02
0.5
+ 0.08
0.18 – 0.03
0.13 M
+ 0.2
1.5 – 0.1
0.1
S
0.5 ± 0.2
0.18 ± 0.03
0˚ to 10˚
0.127 ± 0.04
0.1 ± 0.1
DETAIL B: PALLADIUM
DETAIL A
NOTE: Dimension “∗” does not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL
EPOXY RESIN
PALLADIUM PLATING
SONY CODE
LQFP-48P-L01
LEAD TREATMENT
EIAJ CODE
P-LQFP48-7x7-0.5
LEAD MATERIAL
COPPER ALLOY
PACKAGE MASS
0.2g
JEDEC CODE
– 39 –
Sony Corporation