IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES FAST CMOS BUFFER/CLOCK DRIVER FEATURES: IDT49FCT805BT/CT DESCRIPTION: • • • • • • • • • • • 0.5 MICRON CMOS Technology Guaranteed low skew < 500ps (max.) Very low duty cycle distortion < 600ps (max.) Low CMOS power levels TTL compatible inputs and outputs TTL level output voltage swings High drive: -32mA IOH, +48mA IOL Two independent output banks with 3-state control 1:5 fanout per bank "Heartbeat" monitor output ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) • Available in the following packages: – Commercial: QSOP, SOIC, SSOP – Military: CERDIP, LCC This buffer/clock driver is built using advanced dual metal CMOS technology. The FCT805T is a non-inverting clock driver consisting of two banks of drivers. Each bank drives five output buffers from a standard TTL compatible input. This part has extremely low output skew, pulse skew, and package skew. The device has a “heart-beat” monitor for diagnostics and PLL driving. The monitor output is identical to all other outputs and complies with the output specifications in this document. The FCT805T is designed for fast, clean edge rates to provide accurate clock distribution in high speed systems. FUNCTIONAL BLOCK DIAGRAM OE A 5 IN A OA 1 -OA 5 5 IN B OB 1 -OB 5 OE B MON The IDT logo is a registered trademark of Integrated Device Technology, Inc. MILITARY AND COMMERCIAL TEMPERATURE RANGES JULY 2000 1 c 2000 Integrated Device Technology, Inc. DSC-4771/2 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES OB1 OA2 3 18 OB2 OA3 4 17 GND 5 16 GND OA4 6 15 OB4 OA5 7 14 OB5 (1) 8 13 MON OEA 9 12 OEB INA 10 11 INB 2 20 19 18 OB2 5 17 OB3 OA4 6 16 GND OA5 7 15 OB4 8 14 OB5 OA3 4 GND (1) GND 1 9 10 11 12 13 OEA GND OB3 3 OB1 19 QSOP/ SOIC/ SSOP/ CERDIP TOP VIEW MON 2 VCC OA1 OEB VCC VCC 20 INB 1 INA VCC OA1 INDEX OA2 PIN CONFIGURATION LCC TOP VIEW NOTE: 1. Pin 8 is internally connected to GND. To insure compatibility with all products, pin 8 should be connected to GND at the board level. PIN DESCRIPTION ABSOLUTE MAXIMUM RATINGS(1) Symbol Description Max Unit Pin Names Description VTERM Terminal Voltage with Respect to GND –0.5 to +7 V OEA, OEB TSTG Storage Temperature –65 to +150 °C INA, INB Clock Inputs IOUT DC Output Current –60 to +120 mA OAx, OBx Clock Outputs MON Monitor Output NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3-State Output Enable Inputs (Active LOW) FUNCTION TABLE (1) Inputs OEA, OEB CAPACITANCE (TA = +25OC, f = 1.0MHz) Symbol Parameter(1) Conditions Typ. Max. Unit CIN Input Capacitance VIN = 0V 4.5 6 pF COUT Output Capacitance VOUT = 0V 5.5 8 pF 2 INA, INB OAx, OBx MON L L L L L H H H H L Z L H H Z H NOTE: 1. H = HIGH L = LOW Z = High-Impedance NOTE: 1. This parameter is measured at characterization but not tested. Outputs IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, Military: TA = -55°C to +125°C, VCC = 5V ± 10% Parameter Test Conditions(1) Min. Typ.(2) VIH Input HIGH Level Max. Unit Guaranteed Logic HIGH Level 2 — — V VIL IIH Input LOW Level Guaranteed Logic LOW Level — — 0.8 V Input HIGH Current(5) VCC = Max. VI = 2.7V — — ±1 µA IIL Input LOW Current(5) VCC = Max. VI = 0.5V — — ±1 µA IOZH High Impedance Output Current VCC = Max. VO = 2.7V — — ±1 µA IOZL (3-State Output Pins) VO = 0.5V — — ±1 II Input HIGH Current VCC = Max., VI = VCC (Max.) — — ±1 µA VIK Clamp Diode Voltage VCC = Min., IIN = –18mA — –0.7 –1.2 V –60 –120 –255 mA 2.4 3.3 — V 2 3 — V — 0.3 0.55 V ±1 µA Symbol GND(3) IOS Short Circuit Current VCC = Max., VO = VCC = Min. IOH = –12mA MIL VOH Output HIGH Voltage VIN = VIH or VIL IOH = –15mA COM'L IOH = –24mA MIL IOH = –32mA COM'L(4) VOL Output LOW Voltage VCC = Min. IOL = 32mA MIL IOFF Input/Output Power Off Leakage(5) VIN = VIH or VIL VCC = 0V, VIN or VO ≤ 4.5V IOL = 48mA COM'L — — VH Input Hysteresis for all inputs — — 150 — mV ICCL Quiescent Power Supply Current VCC = Max., VIN = GND or VCC — 5 500 µA ICCH ICCZ NOTES: 1. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are at Vcc = 5V, +25°C ambient. 3. Not more than one output should be shorted at one time. Duration of the test should not exceed one second. 4. Duration of the condition should not exceed one second. 5. The test limit for this parameter is ±5µA at TA = -55°C. 3 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES POWER SUPPLY CHARACTERISTICS Symbol ∆ICC ICCD Test Conditions(1) Parameter Quiescent Power Supply Current VCC = Max. TTL Inputs HIGH VIN = 3.4V(3) Dynamic Power Supply Current(4) VCC = Max. VIN = VCC Outputs Open VIN = GND Min. Typ.(2) Max. Unit — 1 2 mA — 60 100 µA/MHz — 1.5 3 — 1.8 4 — 33 55.5 — 33.5 57.5 OEA = OEB = GND 50% Duty Cycle IC Total Power Supply Current(6) VCC = Max. VIN = VCC Outputs Open VIN = GND fO = 25MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = VCC VIN = GND Mon. Output Toggling VCC = Max. VIN = VCC Outputs Open VIN = GND (5) fO = 50MHz 50% Duty Cycle VIN = 3.4V OEA = OEB = GND VIN = GND Eleven Outputs Toggling NOTES: 1. 2. 3. 4. 5. For conditions shown as Max. or Min., use appropriate value specified under Electrical Characteristics for the applicable device type. Typical values are at VCC = 5V, +25°C ambient. Per TTL driven input (VIN = 3.4V); all other inputs at VCC or GND. This parameter is not directly testable, but is derived for use in Total Power Supply calculations. Values for these conditions are examples of the IC formula. These limits are guaranteed but not tested. 6. IC = IQUIESCENT + IINPUTS + IDYNAMIC IC = ICC + ∆ICC DHNT + ICCD (fONO) ICC = Quiescent Current (ICCL, ICCH and ICCZ) ∆ICC = Power Supply Current for a TTL High Input (VIN = 3.4V) DH = Duty Cycle for TTL Inputs High NT = Number of TTL Inputs at DH ICCD = Dynamic Current Caused by an Input Transition Pair (HLH or LHL) fO = Output Frequency NO = Number of Outputs at fO All currents are in milliamps and all frequencies are in megahertz. 4 (5) mA IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES SWITCHING CHARACTERISTICS OVER OPERATING RANGE - MILITARY(1,2) Symbol Parameter FCT805CT Min.(4) Max. Unit 5.7 1.5 5.2 ns Output Rise Time Output Fall Time — — 2 1.5 — — 2 1.5 ns ns tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) — 0.9 — 0.7 ns tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) — 0.9 — 0.8 ns tSK(PP) Part-to-part skew: skew between outputs of different packages at same power supply voltage, — 1.5 — 1.2 ns tR tF CL = 50pF RL = 500Ω FCT805BT Min.(4) Max. 1.5 tPLH tPHL Propagation Delay INA to OAx, INB to OBx Conditions(3) tPZL temperature, package type and speed grade Output Enable Time 1.5 6.5 1.5 6 ns tPZH tPLZ OEA to OAx, OEB to OBx Output Disable Time 1.5 6.5 1.5 6 ns tPHZ OEA to OAx, OEB to OBx NOTES: 1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested. 2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply skew. 3. See Test Circuits and Waveforms. 4. Minimum limits are guaranteed but not tested on Propagation Delays. SWITCHING CHARACTERISTICS OVER OPERATING RANGE - COMMERCIAL(1,2) Symbol Parameter FCT805CT Min.(4) Max. Unit 5 1.5 4.5 ns Output Rise Time Output Fall Time — — 1.5 1.5 — — 1.5 1.5 ns ns tSK(O) Output skew: skew between outputs of all banks of same package (inputs tied together) — 0.7 — 0.5 ns tSK(P) Pulse skew: skew between opposite transitions of same output (|tPHL -– tPLH|) — 0.7 — 0.6 ns tSK(PP) Part-to-part skew: skew between outputs of different — 1.2 — 1 ns tR tF CL = 50pF RL = 500Ω FCT805BT Min.(4) Max. 1.5 tPLH tPHL Propagation Delay INA to OAx, INB to OBx Conditions(3) packages at same power supply voltage, temperature, package type and speed grade tPZL tPZH Output Enable Time OEA to OAx, OEB to OBx 1.5 6 1.5 5 ns tPLZ tPHZ Output Disable Time OEA to OAx, OEB to OBx 1.5 6 1.5 5 ns NOTES: 1. tPLH, tPHL, and tSK(pp) are production tested. All other parameters are guaranteed but not production tested. 2. Propagation delay range indicated by Min. and Max. limit is dues to Vcc, operating temperature, and process parameters. These propagation delay limits do not imply skew. 3. See Test Circuits and Waveforms. 4. Minimum limits are guaranteed but not tested on Propagation Delays. 5 IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES TEST CIRCUITS AND WAVEFORMS SWITCH POSITION VCC Test Switch Disable LOW Enable LOW Closed Disable HIGH Enable HIGH GND 7V 500 Ω Pulse Generator V IN V OUT D.U.T. 50pF 500 Ω RT DEFINITIONS: CL = Load capacitance: includes jig and probe capacitance. RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. CL Test Circuits for All Outputs INPUT 3V 3V 1.5V 1.5V INPUT 0V t PHL t PLH 0V tPLH1 tPLH1 V OH V OH 2.0V 0.8V OUTPUT tR 1.5V OUTPUT 1 1.5V VO L t SK(o) VO L t SK(o) V OH 1.5V tF OUTPUT 2 Package Delay VO L tPH L2 t PLH 2 tSK (o) = t PLH2 - tP LH 1 3V or t PH L2 - t PHL1 1.5V INPUT Output Skew 0V t PLH t PHL VO H 1.5V OUTPUT 3V V OL 1.5V tSK (p) = t PHL - tPLH INPUT tP LH1 Pulse Skew - tSK(P) t PH L1 VOH PACKAGE 1 OUTPUT DISABLE ENABLE CONTROL INPUT tPZL OUTPUT NORMALLY LOW tPLZ 3.5V SW ITCH CLOSED SW ITCH OPEN tS K(pp) PACKAGE 2 OUTPUT 0V 1.5V 0V V OL tPH L2 tPLH2 tSK (pp) = t PLH2 - t PLH1 or t PH L2 - tPHL1 Part-to-Part Skew - tSK(PP) 0.3V V OH 0V NOTE: 1. Package 1 and Package 2 are same device type and speed grade. Enable and Disable Times NOTES: 1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH 2. Pulse Generator for All Pulses: Rate ≤ 1.0MHz; tF ≤ 2.5ns; tR ≤ 2.5ns 6 VOH 1.5V tPH Z t PZH OUTPUT NORMALLY HIGH 1.5V V OL t SK(pp) 3V 1.5V 3.5V 0.3V V OL 1.5V 0V IDT49FCT805BT/CT FAST CMOS BUFFER/CLOCK DRIVER MILITARY AND COMMERCIAL TEMPERATURE RANGES ORDERING INFORMATION IDT49FCT XXXX Device Type XX Package X Process Blank B Commercial (0°C to +70°C) MIL-STD-883, Class B (– 55°C to +125°C) SO Q PY Commercial Options Small Outline IC Quarter-size Small Outline Package Shrink Small Outline Package D L Military Options CERDIP Leadless Chip Carrier 805BT 805CT CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 Fast CMOS Buffer/Clock Driver for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 7 for Tech Support: [email protected] (408) 654-6459