3.3 VOLT TIME SLOT INTERCHANGE DIGITAL SWITCH 128 x 128 outputs, each of which consists of 32 channels (64 Kbit/s per channel) to form a multiplexed 2.048 Mb/s stream. FEATURES: • • • • • • • • • • IDT72V8981 128 x 128 channel non-blocking switch Serial Telecom Bus Compatible (ST-BUS®) 4 RX inputs—32 channels at 64 Kbit/s per serial line 4 TX output—32 channels at 64 Kbit/s per serial line Three-state serial outputs Microprocessor Interface (8-bit data bus) 3.3V Power Supply Available in 44-pin Plastic Leaded Chip Carrier (PLCC), and 44-pin Plastic Quad Flatpack (PQFP) Operating Temperature Range -40°° C to +85°°C 3.3V I/O with 5V Tolerant Inputs FUNCTIONAL DESCRIPTION A functional block diagram of the IDT72V8981 device is shown below. The serial streams operate continuously at 2.048 Mb/s and are arranged in 125µs wide frames each containing 32, 8-bit channels. Four input (RX0-3) and four output (TX0-3) serial streams are provided in the IDT72V8981 device allowing a complete 128 x 128 channel non-blocking switch matrix to be constructed. The serial interface clock (C4i) for the device is 4.096 MHz. The received serial data is internally converted to a parallel format by the on chip serial-to-parallel converters and stored sequentially in a 128-position Data Memory. By using an internal counter that is reset by the input 8 KHz frame pulse, F0i, the incoming serial data streams can be framed and sequentially addressed. Data to be output on the serial streams may come from two sources: Data Memory or Connection Memory. The Connection Memory is 16 bits wide and DESCRIPTION: The IDT72V8981 is a ST-BUS® compatible digital switch controlled by a microprocessor. The IDT72V8981 can handle as many as 128, 64 Kbit/s input and output channels. Those 128 channels are divided into 4 serial inputs and FUNCTIONAL BLOCK DIAGRAM C4i F0i VCC ODE GND Timing Unit Output MUX RX0 RX1 RX2 TX0 Receive Serial Data Streams Transmit Serial Data Streams Data Memory RX3 Control Register Connection Memory TX1 TX2 TX3 Microprocessor Interface 5702 drw01 DS CS R/W A0/ DTA D0/ A5 D7 IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The ST-BUS is a trademark of Mitel Corp. AUGUST 2003 1 2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice. DSC-5702/4 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range ODE TX0 TX1 TX2 DNC(1) 43 42 41 40 RX0 DTA 2 DNC(1) RX1 3 44 RX2 4 1 DNC(1) 5 INDEX 6 PIN CONFIGURATION RX3 7 39 TX3 VCC 8 38 DNC(1) VCC 9 37 VCC 10 36 DNC(1) DNC(1) 27 28 D5 (1) D4 26 29 25 17 D6 D3 A2 D7 D2 30 5702 drw02 DNC 24 31 16 CS 15 A1 23 A0 DS D1 R/W 32 22 14 21 D0 C4i 20 33 A5 13 A4 GND F0i 19 DNC(1) 34 A3 35 12 18 11 DNC(1) VCC VCC RX1 RX0 DTA DNC(1) ODE TX0 TX1 TX2 DNC(1) 42 41 40 38 36 35 34 37 RX2 39 DNC(1) 43 INDEX 44 PLCC: 0.05in. pitch, 0.65in. x 0.65in. (J44-1, order code: J) TOP VIEW RX3 1 33 TX3 VCC 2 32 DNC(1) VCC 3 31 VCC 4 30 DNC(1) DNC(1) VCC 5 29 DNC(1) VCC 6 28 GND D0 D1 D4 22 23 21 11 20 A2 19 D2 D3 18 24 17 25 10 16 9 A1 15 26 14 27 8 13 7 12 F0i C4i A0 DNC(1) D5 D6 CS D7 DS R/W A5 A4 A3 DNC(1) 5702 drw03 PQFP: 0.80mm pitch, 10mm x 10mm (DB44-1, order code: DB) TOP VIEW NOTE: 1. DNC - Do Not Connect 2 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range PIN DESCRIPTIONS SYMBOL GND VCC DTA RX0-3 F0i C4i A0-A5 DS R/W CS D0-D7 TX0-3 ODE NAME Ground. VCC Data Acknowledgment (Open Drain) RX Input 0 to 3 Frame Pulse Clock Address 0 to 5 Data Strobe I/O O I I I I I Read/Write Chip Select Data Bus 0 to 7 I I I/O TX Outputs 0 to 3 (Three-state Outputs) Output Drive Enable O I DESCRIPTION Ground Rail. +3.3 Volt Power Supply. This active LOW output indicates that a data bus transfer is complete. A pull-up resistor is required at this output. Serial data input streams. These streams have 32 channels at data rates of 2.048 Mb/s. This input identifies frame synchronization signals formatted to ST-BUS® specifications. 4.096 MHz serial clock for shifting data in and out of the data streams. These lines provide the address to IDT72V8981 internal registers. This is the input for the active HIGH data strobe on the microprocessor interface. This input operates with CS to enable the internal read and write generation. This input controls the direction of the data bus lines (D0-D7) during a microprocessor access. Active LOW input enabling a microprocessor read or write of control register or internal memories. These pins provide microprocessor access to data in the internal control register. Connection Memory HIGH, Connection Memory LOW and data memory. Serial data output streams. These streams are composed of 32, 64 Kbit/s channels at data rates of 2.048 Mb/s. This is an output enable for the TX0-3 serial outputs. If this input is LOW, TX0-3 are high-impedance. If this is HIGH, each channel may still be put into high-impedance by software control. 3 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range As information enters the IDT72V8981 it must first pass through an internal serial-to-parallel converter. Likewise, before data leaves the device, it must pass through the internal parallel-to-serial converter. This data preparation has an effect on the channel positioning in the frame immediately following the incoming frame—mainly, data cannot leave in the same time slot. Therefore, information that is to be output in the same channel position as the information is input, relative to the frame pulse, will be output in the following frame. Whether information can be output during a following timeslot after the information entered the IDT72V8981 depends on which RX stream the channel information enters on and which TX stream the information leaves on. This is caused by the order in which input stream information is placed into Data Memory and the order in which stream information is queued for output. Table 1 shows the allowable input/output stream combinations for the minimum two channel delay. FUNCTIONAL DESCRIPTION (Cont'd) is split into two 8-bit blocks—Connection Memory HIGH and Connection Memory LOW. Each location in Connection Memory is associated with a particular channel in an output stream so as to provide a one-to-one correspondence between Connection and Data Memories. This correspondence allows for per channel control for each TX output stream. In Processor Mode, data output on the TX is taken from the Connection Memory Low and originates from the microprocessor (Figure 2). Where as in Connection Mode (Figure 1), data is read from Data Memory using the address in Connection Memory. Data destined for a particular channel on the serial output stream is read during the previous channel time slot to allow time for memory access and internal parallel-to-serial conversion. CONNECTION MODE In Connection Mode, the addresses of input source for all output channels are stored in the Connection Memory Low. The Connection Memory Low locations are mapped to corresponding 8-bit x 32-channel output. The contents of the Data Memory at the selected address are then transferred to the parallelto-serial converters. By having the output channel to specify the input channel through the Connection Memory, input channels can be broadcast to several output channels. SOFTWARE CONTROL If the A5 address line input is LOW then the IDT72V8981 Internal Control Register is addressed. If A5 input line is high, then the remaining address input lines are used to select the 32 possible channels per input or output stream. The address input lines and the Stream Address bits (STA) of the Control register give the user the capability of selecting all positions of IDT72V8981 Data and Connection memories. The IDT72V8981 memory mapping is illustrated in Table 2 and Figure 3. The data in the control register (Table 3) consists of Memory Select and Stream Address bits, Split Memory and Processor Mode bits. In Split Memory mode (Bit 7 of the Control register) reads are from the Data Memory and writes are to the Connection Memory as specified by the Memory Select Bits (Bits 4 and 3 of the Control Register). The Memory Select bits allow the Connection Memory HIGH or LOW or the Data Memory to be chosen, and the Stream Address bits define internal memory subsections corresponding to input or output streams. The Processor Enable bit (bit 6) places EVERY output channel on every output stream in Processor mode; i.e., the contents of the Connection Memory LOW (CML, see Table 5) are output on the TX output streams once every frame unless the ODE input pin is LOW. If PE bit is HIGH, then the IDT72V8981 behaves as if bits 2 (Channel Source) and 0 (Output Enable) of every Connection Memory High (CMH) locations were set to HIGH, regardless of the actual value. If PE is LOW, then bit 2 and 0 of each Connection Memory High location operates normally. In this case, if bit 2 of the CMH is HIGH, the associated TX output channel is in Processor Mode. If bit 2 of the CMH is LOW, then the contents of the CML define the source information (stream and channel) of the time slot that is to be switched to an output. If the ODE input pin is LOW, then all the serial outputs are high-impedance. If ODE is HIGH, then bit 0 (Output Enable) of the CMH location enables (if HIGH) or disables (if LOW) the output stream and channel. PROCESSOR MODE In Processor Mode the CPU writes data to specific Connection Memory Low locations which are to be output on the TX streams. The contents of the Connection Memory Low are transferred to the parallel-to-serial converter one channel before it is to be output and are transmitted each frame to the output until it is changed by the CPU. CONTROL The Connection Memory High bits (Table 4) control the per-channel functions available in the IDT72V8981. Output channels are selected into specific modes such as: Processor mode or Connection mode and Output Drivers Enabled or in three-state condition. OUTPUT DRIVE ENABLE (ODE) The ODE pin is the master three-state output control pin. If the ODE input is held LOW all TX outputs will be placed in high impedance regardless Connection Memory High programming. However, if ODE is HIGH, the contents of Connection Memory High control the output state on a per-channel basis. DELAY THROUGH THE IDT72V8981 The transfer of information from the input serial streams to the output serial streams results in a delay through the device. The delay through the IDT72V8981 device varies according to the combination of input and output streams and the movement within the stream from channel to channel. Data received on an input stream must first be stored in Data Memory before it is sent out. RX Receive Serial Data Streams Data Memory Connection Memory Transmit Serial Data Streams Receive Serial Data Streams TX Data Memory Connection Memory Transmit Serial Data Streams TX 5702 drw06 Microprocessor 5702 drw05 Figure 1. Connection Mode Figure 2. Processor Mode 4 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range During the microprocessor initialization routine, the microprocessor should program the desired active paths through the matrices, and put all other channels into the high impedance state. Care should be taken that no two connected TX outputs drive the bus simultaneously. With the CMH setup, the microprocessor controlling the matrices can bring the ODE signal high to relinquish high impedance state control to the Connection Memory High bits outputs. INITIALIZATION OF THE IDT72V8981 On initialization or power up, the contents of the Connection Memory High can be in any state. This is a potentially hazardous condition when multiple TX outputs are tied together to form matrices. The ODE pin should be held low on power up to keep all outputs in the high impedance condition until the contents of the CMH are programmed. TABLE 1 — INPUT STREAM TO OUT- TABLE 2 — ADDRESS MAPPING PUT STREAM COMBINATIONS THAT A5 A4 A3 A2 A1 A0 HEX ADDRESS LOCATION CAN PROVIDE THE MINIMUM 0 X X X 0 0 00-1F Control Register(1) 2-CHANNEL DELAY 1 0 0 0 0 0 20 Channel 0(2) Input Output Stream 0 1,2,3 1 3 1 1 1 1 1 0 0 0 0 1 21 Channel 1(2) • • • • • • • • • • • • • • • • • • • • • 1 1 1 1 1 3F Channel 31(2) NOTES: 1. Writing to the Control Register is the only fast transaction. 2. Memory and stream are specified by the contents of the Control Register. Control Register CRb7 CRb6 The Control Register is only accessed when A5=0. All other address bits have no effect when A5=0. When A5 =1, only 32 bytes are randomly accessable via A0-A4 at any one instant. Which 32 bytes are accessed is determined by the state of CRb0 -CRb4. The 32 bytes correlate to 32 channel of one ST-BUS stream. CRb5 CRb4 0 1 1 CRb4 CRb3 CRb2 CRb1 CRb0 CRb3 1 0 1 Connection Memory High Connection Memory Low Data Memory Channel 0 Channel 0 Channel 0 Channel 0 Channel 1 Channel 1 Channel 1 Channel 1 Channel 2 Channel 2 Channel 2 Channel 2 10000 0 10000 1 10001 0 Channel 31 Channel 31 Channel 31 Channel 31 11111 1 Figure 3. Address Mapping 5 CRb1 0 0 1 1 External Address Bits CRb0 Stream 0 0 1 1 0 2 1 3 A5-A0 5702 drw07 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range TABLE 3 — CONTROL REGISTER CONFIGURATION Mode Control Bits 7 Bit 6 (unused) Memory Select Stream Address Bits (unused) Bits 5 4 Name 3 2 1 0 Description 7 SM (Split Memory) When 1, all subsequent reads are from the Data Memory and writes are to the Connection Memory LOW, except when the Control Register is accessed again. When 0, the Memory Select bits specify the memory for the operations. In either case, the Stream Address Bits select the subsection of the memory which is made available. 6 PE (Processor Mode) When 1, the contents of the Connection Memory LOW are output on the Serial Output streams except when the ODE pin is LOW. When 0, the Connection Memory bits for each channel determine what is output. 5 4-3 unused MS1-MS0 (Memory Select Bits) 2 1-0 0-0 - Not to be used. 0-1 - Data Memory (read only from the microprocessor port) 1-0 - Connection Memory LOW 1-1 - Connection Memory is HIGH unused STA1-0 (Stream Address Bits) The number expressed in binary notation on these bits refers to the input or output stream which corresponds to the subsection of memory made accessible for subsequent operations. TABLE 4 — CONNECTION MEMORY HIGH REGISTER No Corresponding Memory - These bits give 0s if read 7 Bit 2 5 4 Name CS (Channel Source) 1 0 6 3 CS (unused) OE 2 1 0 Description When 1, the contents of the corresponding location in Connection Memory LOW are output on the location's channel and stream. When 0, the contents of the corresponding location in Connection Memory LOW act as an address for the Data Memory and determine the source of the connection to the location's channel and stream. unused OE (Output Enable) If the ODE pin is HIGH and bit 6 of the Control Register is 0, then this bit enables the output driver for the location's channel and stream. This allows individuals channels on individuals streams to be made high-impedance, allowing switching matrices to be constructed. A 1 enables the driver and a 0 disables it. TABLE 5 — CONNECTION MEMORY LOW REGISTER (unused) 7 Bit Stream Address Bits 6 Channel Address Bits 5 4 Name 7 3 2 1 0 Description unused 6-5(1) Stream Address Bits The number expressed in binary notation on these 2 bits are the number of the stream for the source of the connection. Bit 6 is the most significant bit, e.g., If bit 6 is 1, bit 5 is 0 then the source of the connection is a channel on RX2. 4-0(1) Channel Address Bits The number expressed in binary notation on these 5 bits is the number of the channel which is the source of the connection (the stream where the channel lies is defined by bits 7, 6 and 5). Bit 4 is the most significant bit, e.g., if bit 4 is 1, bit 3 is 0, bit 2 is 0, bit 1 is 1 and bit 0 is 1, then the source of the connection is channel 19. NOTE: 1. If bit 2 of the corresponding Connection HIGH location is 1 or bit 6 of the Control Register is 1, then these entire 8 bits are output on the channel and stream associated with this location. Otherwise, the bits are used as indicated to define the source of the connection which is output on the channel and stream associated with this location. 6 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range (1) ABSOLUTE MAXIMUM RATINGS Symbol Vcc Vi Parameter Min. Max. Unit Symbol Voltage -0.3 5 V Voltage on Digital Inputs VO Voltage on Digital Outputs IO Current at Digital Outputs TS Storage Temperature PD Package Power Dissapation GND - 0.3 VCC +0.5 GND - 0.3 -55 RECOMMENDED OPERATING CONDITIONS Symbol V VCC +0.3 V 20 mA +125 °C 1 W Parameter Typ.(1) Max. Unit 3.0 3.6 V 0 5.25 V -40 25 +85 °C Min. VCC Positive Supply VI Input Voltage TOP Operating Temperature Commercial NOTE: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC ELECTRICAL CHARACTERISTICS Min. Typ.(1) Max. Units Test Conditions ICC Supply Current 3 5 mA Outputs Unloaded VIH Input High Voltage 2.0 V VIL Input Low Voltage 0.8 V IIL Input Leakage 15 µA CI Symbol Parameter VI between GND and VCC Input Capacitance pF VOH Output High Voltage 2.4 V IOH = 10mA IOH Output High Current 10 mA Sourcing. VOH = 2.4V VOL Output Low Voltage 0.4 V IOL = 5mA IOL Output Low Current 5 mA Sinking. VOL = 0.4V I OZ High Impedance Leakage 5 µA VO between GND and VCC CO Output Pin Capacitance 10 pF NOTE: 1. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. Test Point VCC S1 is open circuit except when testing output levels or high impedance states. RL Output Pin S1 S2 CL GND S2 is switched to VCC or GND when testing output levels or high impedance states. GND 5702 drw08 Figure 4. Output Load 7 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS (1) CLOCK TIMING Symbol Characteristics Min. Typ.(2) Max. Unit tCLK Clock Period(3) 244 ns tCH Clock Width High 122 ns tCL Clock Width Low 110 122 150 ns tCTT Clock Transition Time 20 ns tFPS Frame Pulse Setup Time 5 20 190 ns tFPH Frame Pulse Hold Time 5 20 190 ns tFPW Frame Pulse Width 244 ns NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. Contents of Connection Memory are not lost if the clock stops, however, TX output go into the high impedance state. C4i F0i Channel 31 Bit 0 Bit Cells Channel 0 Bit 7 5702 drw09 Figure 5. Frame Alignment tCLK tCTT tCTT tCHL tCL tCH C4i (( )) tFPH tFPS tFPH tFPS tFPW F0i 5702 drw10 Figure 6. Clock Timing 8 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS Symbol Characteristics (1) SERIAL STREAM TIMING Min. Typ.(2) Max. Unit Test Conditions tTAZ TX0-3 Delay - Active to High Z 30 45 ns RL = 1KΩ(3), CL = 150pF tTZA TX0-3 Delay - High Z to Active 45 60 ns CL = 150pF tTAA TX0-3 Delay - Active to Active 40 60 ns CL = 150pF tTOH TX0-3 Hold Time 20 45 ns CL = 150pF tOED Output Driver Enable Delay 45 60 ns RL = 1KΩ(3), CL = 150pF tSIS Serial Input Setup Time 10 20 ns tSIH Serial Input Hold Time 10 20 ns tZDO High Z to Valid Data 32 cycles C4i cycles NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. Bit Cell Boundary ODE tOED tOED C4i TX0-3 tTAZ tTOH 5702 drw12 Figure 8. Output Driver Enable TX0-3 tTZA TX0-3 Bit Cell Boundaries C4i tTAA tTOH tSIS tSIH TX0-3 5702 drw11 RX0-3 5702 drw13 Figure 9. Serial Inputs Figure 7. Serial Outputs and External Control 9 IDT72V8981 3.3V Time Slot Interchange Digital Switch 128 x 128 Commercial Temperature Range AC ELECTRICAL CHARACTERISTICS Symbol Characteristics (1) PROCESSOR BUS Min. Typ.(2) Max. Unit Test Conditions tCSS Chip Select Setup Time 0 ns tRWS Read/Write Setup Time 5 ns tADS Address Setup Time 5 ns tAKD Acknowledgment Delay Fast 40 60 ns CL = 150pF tAKD Acknowledgment Delay Slow 4.5 cycles C4i cycles(4) tFWS Fast Write Data Setup Time 10 20 ns tSWD Slow Write Data Delay 2.0 1.7 cycles tRDS Read Data Setup Time 0.5 cycles C4i cycles, CL = 150pF tDHT Data Hold Time Read 20 50 75 ns RL = 1KΩ(3), CL = 150pF tDHT Data Hold Time Write 10 ns tRDZ Read Data to High Impedance 10 50 ns tCSH Chip Select Hold Time 0 5 ns tRWH Read/Write Hold Time 0 5 ns tADH Address Hold Time 0 5 ns tAKH Acknowledgment Hold Time 20 40 ns C4i cycles RL = 1KΩ(3), CL = 150pF RL = 1KΩ(3), CL = 150pF NOTE: 1. Timing is over recommended temperature and power supply voltages. 2. Typical figures are at 25°C and are for design aid only; not guaranteed and not subject to production testing. 3. High Impedance is measured by pulling to the appropriate rail with RL, with timing corrected to cancel time taken to discharge CL. 4. Processor accesses are dependent on the C4i clock, and so some things are expressed as multiples of the C4i. DS tCSS tCSH tRWS tRWH tADS tADH CS R/W A5-A0 tAKD tAKH DTA tRDS tSWD tFWS tRDZ tDHT D7-D0 5702 drw15 Figure 10. Processor Bus 10 ORDERING INFORMATION IDT XXXXXX Device Type XX Package X Process/ Temperature Range BLANK Commercial (-40°C to +85°C) J DB Plastic Leaded Chip Carrier (PLCC, J44-1) Plastic Quad Flatpack (PQFP, DB44-1) 72V8981 128 x 128 3.3V Time Slot Interchange Digital Switch 5702 drw16 DATASHEET DOCUMENT HISTORY 05/23/2000 08/18/2000 01/24/2001 03/10/2003 05/09/2003 08/20/2003 pgs. pgs. pgs. pg. pgs. pg. 1, 2 and 11. 1, 2 and 11. 1 and 7. 1. 1-3, 5, 9, and 11. 7. CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054 for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com 11 for Tech Support: 408-330-1753 email: [email protected]