IDT IDTCV125PA

IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PROGRAMMABLE FLEXPC
CLOCK FOR P4 PROCESSOR
DESCRIPTION:
FEATURES:
IDTCV125 is a 56 pin clock device, incorporating both Intel CK410M and
CKSSCD requirements, for Intel advance P4 processors. The CPU output
buffer is designed to support up to 400MHz processor. This chip has four PLLs
inside for CPU, SRC/PCI, LVDS, and 48MHz/DOT96 IO clocks. This device
also implements Band-gap referenced IREF to reduce the impact of VDD variation
on differential outputs, which can provide more robust system performance.
Static PLL frequency divide error can be as low as 36 ppm, worse case 114
ppm, providing high accuracy output clock. Each CPU/SRC/LVDS has its own
Spread Spectrum selection.
• Power management control suitable for notebook applications
• One high precision PLL for CPU, SSC and N programming
• One high precision PLL for SRC/PCI, supports 100MHz output
frequency, SSC and N programming
• One high precision PLL for LVDS. Supports 100/96MHz output
frequency, SSC programming
• One high precision PLL for 96MHz/48MHz
• Band-gap circuit for differential outputs
• Support spread spectrum modulation, –0.5 down spread and
others
• Support SMBus block read/write, index read/write
• Selectable output strength for REF
• Allows for CPU frequency to change to a slower frequency to
conserve power when an application is less executionintensive
• Smooth transition for N programming
• Available in TSSOP package
OUTPUTS:
•
•
•
•
•
•
•
KEY SPECIFICATION:
•
•
•
•
IDTCV125
2*0.7V current –mode differential CPU CLK pair
6*0.7V current –mode differential SRC CLK pair
One CPU_ITP/SRC selectable CLK pair
6*PCI, 2 free running, 33.3MHz
1*96MHz, 1*48MHz
1*REF
One 100/96 MHz differential LVDS
CPU/SRC CLK cycle to cycle jitter < 85ps
PCI CLK cycle to cycle jitter < 250ps
Static PLL frequency divide error < 114 ppm
Static PLL frequency divide error for 48MHz < 5 ppm
FUNCTIONAL BLOCK DIAGRAM
PLL1
SSC
N Programmable
X1
CPU CLK
Output Buffer
Stop Logic
CPU[1:0]
CPU_ITP/SRC7
XTAL
Osc Amp
IREF
REF
X2
SDATA
SCLK
LVDS CLK
Output Buffer
Stop Logic
PLL2
SSC
SM Bus
Controller
ITP_EN
LVDS
IREF
PLL3
SSC
N Programmable
SRC CLK
Output Buffer
Stop Logic
SRC[6:1]
VTT_PWRGD#/PD
SEL100/96#
SEL
100/96MHz
PCI[3:0], PCIF[1:0]
IREF
FSA.B.C
PCI_STOP#
Control
Logic
CPU_STOP#
48MHz
48MHz/96MHz
Output BUffer
PLL4
DOT96
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
DECEMBER 2004
1
© 2004 Integrated Device Technology, Inc.
DSC 6552/14
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
PIN CONFIGURATION
Symbol
Description
Min
VDD_PCI
1
56
PCI0
VDDA
3.3V Core Supply Voltage
VSS_PCI
2
55
PCI_STOP#
VDDIN
3.3V Logic Input Supply Voltage GND - 0.5
PCI1
3
54
CPU_STOP#
TSTG
Storage Temperature
PCI2
4
53
FSC/TEST_SEL
5
TAMBIENT
Ambient Operating Temperature
PCI3
52
REF
VSS_PCI
6
TCASE
Case Temperature
51
VSS_REF
VDD_PCI
7
ESD Prot
Input ESD Protection
50
XTAL_IN
PCIF0/ITP_EN
8
49
XTAL_OUT
PCIF1/SEL100/96#
9
48
VDD_REF
VTT_PWRGD#/PD
10
47
SDA
VDD48
11
46
SCL
USB48/FSA
12
45
VSS_CPU
VSS48
13
44
CPU0
DOT96
14
43
CPU0#
DOT96#
15
42
VDD_CPU
FSB/TEST_MODE
16
41
CPU1
LVDS
17
40
CPU1#
LVDS#
18
39
IREF
SRC1
19
38
VSSA
SRC1#
20
37
VDDA
VDD_SRC
21
36
CPU2_ITP/SRC7
SRC2
22
35
CPU2_ITP#/SRC7#
SRC2#
23
34
VDD_SRC
SRC3
24
33
SRC6
SRC3#
25
32
SRC6#
SRC4
26
31
SRC5
SRC4#
27
30
SRC5#
VDD_SRC
28
29
VSS_SRC
(1)
(2)
(2)
–65
0
2000
Max
Unit
4.6
V
4.6
V
+150
°C
+70
°C
+115
°C
V
Human Body Model
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTES:
1. 130K internal pull-up resistor.
2. Can be configured as 100MHz or 96MHz output clock, depending on pin9 power on
pull-up (100MHz) or pull-down (96MHz) latch. If using internal pull-up resistor, power
on would be 100MHz.
TSSOP
TOP VIEW
FREQUENCY SELECTION TABLE
FSC, B, A
CPU
SRC[7:0]
PCI
USB
DOT
REF
101
100
100
33.3
48
96
14.318
001
133
100
33.3
48
96
14.318
011
166
100
33.3
48
96
14.318
010
200
100
33.3
48
96
14.318
000
266
100
33.3
48
96
14.318
100
333
100
33.3
48
96
14.318
110
400
100
33.3
48
96
14.318
111
Reserve
100
33.3
48
96
14.318
2
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Number
Name
Type
Description
1
VDD_PCI
PWR
3.3V
2
VSS_PCI
GND
GND
3
PCI1
OUT
PCI clock
4
PCI2
OUT
PCI clock
5
PCI3
OUT
PCI clock
6
VSS_PCI
GND
GND
7
VDD_PCI
PWR
3.3V
8
PCIF0/ITP_EN
I/O
PCI clock, free running. CPU2 select (sampled on VTT_PWRGD# assertion) HIGH = CPU2.
9
PCIF1/SEL100/96#
I/O
PCI clock, free running. SEL100/96MHz (sampled on VTT_PWRGD# assertion) HIGH, LVDS = 100MHz.
10
VTT_PWRGD#/PD
IN
Level-sensitive strobe used to latch the FSA, FSB, FSC/TEST_SEL, and PCIF0/ITP_EN inputs. After
VTT_PWRGD# assertion, becomes a real-time input for asserting power down. (Active HIGH). Latch PCIF1/
SEL100/96# input.
11
VDD48
PWR
12
USB48/FSA
I/O
13
VSS48
GND
GND
3.3V
48MHz clock/FSA for CPU frequency selection
14
DOT96
OUT
96MHz 0.7 current mode differential clock output
15
DOT96#
OUT
96MHz 0.7 current mode differential clock output
16
FSB/TEST_MODE
IN
CPU frequency selection. Selects REF/N or Hi-Z when in test mode, Hi-Z = 1, REF/N = 0.
17
LVDS
OUT
Differential serial reference clock
18
LVDS#
OUT
Differential serial reference clock
19
SRC1
OUT
Differential serial reference clock
20
SRC1#
OUT
Differential serial reference clock
21
VDD_SRC
PWR
3.3V
22
SRC2
OUT
Differential serial reference clock
23
SRC2#
OUT
Differential serial reference clock
24
SRC3
OUT
Differential serial reference clock
25
SRC3#
OUT
Differential serial reference clock
26
SRC4
OUT
Differential serial reference clock
27
SRC4#
OUT
Differential serial reference clock
28
VDD_SRC
PWR
3.3V
29
VSS_SRC
GND
GND
30
SRC5#
OUT
Differential serial reference clock
31
SRC5
OUT
Differential serial reference clock
32
SRC6#
OUT
Differential serial reference clock
33
SRC6
OUT
Differential serial reference clock
34
VDD_SRC
PWR
3.3V
35
CPU2_ITP#/SRC7#
OUT
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7#.
36
CPU2_ITP/SRC7
OUT
Selectable CPU or SRC differential clock output. ITP_EN = 0 at VTT_PWRGD# assertion = SRC7.
37
VDDA
PWR
3.3V
38
VSSA
GND
GND
39
IREF
OUT
Reference current for differential output buffer
40
CPU1#
OUT
Host 0.7 current mode differential clock output
41
CPU1
OUT
Host 0.7 current mode differential clock output
42
VDD_CPU
PWR
3.3V
3
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONT.)
Pin Number
Name
Type
43
CPU0#
OUT
Host 0.7 current mode differential clock output
Description
44
CPU0
OUT
Host 0.7 current mode differential clock output
45
VSS_CPU
GND
46
SCL
IN
GND
SM bus clock
47
SDA
I/O
48
VDD_REF
PWR
3.3V
SM bus data
49
XTAL_OUT
OUT
XTAL output
50
XTAL_IN
IN
51
VSS_REF
GND
XTAL input
52
REF
OUT
53
FSC/TEST_SEL
IN
CPU frequency selection. Selects test mode if pulled above 2V when VTT_PWRGD# is asserted LOW.
54
CPU_STOP#
IN
Stop all stoppable CPU CLK
55
PCI_STOP#
IN
Stop all stoppable PCI, SRC CLK
56
PCI0
OUT
GND
14.318 MHz reference clock output
PCI clock
INDEX BLOCK WRITE PROTOCOL
Bit
1
2-9
10
11-18
19
20-27
28
29-36
37
38-45
46
# of bits
1
8
1
8
1
8
1
8
1
8
1
From
Master
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
Slave
Master
INDEX BLOCK READ PROTOCOL
Master can stop reading any time by issuing the stop bit without waiting
until Nth byte (byte count bit30-37).
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Byte count, N (0 is not valid)
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Nth data byte
Acknowledge
Stop
Bit
1
2-9
10
11-18
19
20
21-28
29
30-37
# of bits
1
8
1
8
1
1
8
1
8
From
Master
Master
Slave
Master
Slave
Master
Master
Slave
Slave
38
39-46
47
48-55
1
8
1
8
Master
Slave
Master
Slave
Master
Slave
Master
INDEX BYTE READ
INDEX BYTE WRITE
Description
Start
D2h
Ack (Acknowledge)
Register offset byte (starting byte)
Ack (Acknowledge)
Repeated Start
D3h
Ack (Acknowledge)
Byte count, N (block read back of N
bytes), power on is 8
Ack (Acknowledge)
first data byte (Offset data byte)
Ack (Acknowledge)
2nd data byte
Ack (Acknowledge)
:
Ack (Acknowledge)
Nth data byte
Not acknowledge
Stop
Setting bit[11:18] = starting address. After reading back the first data byte,
master issues Stop bit.
Setting bit[11:18] = starting address, bit[20:27] = 01h.
4
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
RESOLUTION
SSC MAGNITUDE CONTROL FOR CPU,
SRC, AND SMC
SMC[2:0]
000
001
010
011
100
101
110
111
CPU (MHz)
100
133
166
200
266
333
400
-0.25
-0.5
-0.75
-1
±0.125
±0.25
±0.375
±0.5
Resolution
0.666667
0.666667
1.333333
1.333333
1.333333
2.666667
2.666667
N=
150
200
125
150
200
125
150
SPREAD SPECTRUM CONTROL
SELECTION (SSC) FOR LVDS
SEL 100/96# CONFIGURATION
SEL 100/96#
LVDS Frequency
Unit
0
96
MHz
S[3:0]
Spread
MHz
0000
-0.8%
0001
-1%
0010
-1.25%
0011
-1.5%
0100
-1.75%
0101
-2%
0110
-0.3%
1
100
S.E. CLOCK STRENGTH SELECTION
(PCI, REF, USB48)
Str[1:0]
Level
0111
-0.5%
00
1
1000
±0.3%
01
0.8
1001
±0.4%
10
0.6
1010
±0.5%
11
1.2
1011
±0.6%
1100
±0.8%
1101
±1%
1110
±1.25%
1111
±1.5%
5
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CONTROL REGISTERS
N PROGRAMMING PROCEDURE
Use Index byte write.
For N programming, the user only needs to access Byte 11, Byte 12, and Byte 9.
•
•
1.
2.
3.
Write Byte 11 for CPU PLL N, CPU f = N* Resolution (see resolution table).
Write Byte 12 for SRC PLL N, SRC f = N*0.666667, PCI = SRC f /3.
Enable N Programming bit, Byte 9 bit 1. Once this bit is enabled, any N value will be changed on the fly.
BYTE 0
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
0
Reserved
1
SRC1, SRC1#
Output Enable
Tristate
Enable
RW
1
2
SRC2, SRC2#
Output Enable
Tristate
Enable
RW
1
3
SRC3, SRC3#
Output Enable
Tristate
Enable
RW
1
4
SRC4, SRC4#
Output Enable
Tristate
Enable
RW
1
5
SRC5, SRC5#
Output Enable
Tristate
Enable
RW
1
6
SRC6, SRC6#
Output Enable
Tristate
Enable
RW
1
7
CPU2, CPU2#/
Output Enable
Tristate
Enable
RW
1
SRC7, SRC7#
BYTE 1
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
0
CPU[2:0], SRC[7:1],
Spread Spectrum mode enable
Spread off
Spread on
RW
0
PCI[5:0], PCIF[1:0]
1
CPU0, CPU0#
Output Enable
Tristate
Enable
RW
1
2
CPU1, CPU1#
Output Enable
Tristate
Enable
RW
1
3
Reserved
RW
0
4
REF
Output Enable
Tristate
Enable
RW
1
5
USB48
Output Enable
Tristate
Enable
RW
1
6
DOT96
Output Enable
Tristate
Enable
RW
1
7
PCIF0
Output Enable
Tristate
Enable
RW
1
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
0
PCIF1
Output Enable
Tristate
Enable
RW
1
1
Reserved
RW
1
2
PCI0
Output Enable
Tristate
Enable
RW
1
3
PCI1
Output Enable
Tristate
Enable
RW
1
4
PCI2
Output Enable
Tristate
Enable
RW
1
5
PCI3
Output Enable
Tristate
Enable
RW
1
6
Reserved
RW
1
7
Reserved
RW
1
BYTE 2
6
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 3
Bit
Output(s) Affected
0
1
2
3
4
5
6
7
Reserved
SRC1
SRC2
SRC3
SRC4
SRC5
SRC6
SRC7
Description / Function
Allow controlled by
PCI_STOP# assertion
Bit
Output(s) Affected
0
0
1
Type
Power On
Free running, not
affected by PCI_STOP#
Stopped with
PCI_STOP#
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
Description / Function
0
1
Type
Power On
CPU0, CPU0#
Allow control of CPU0
with assertion of CPU_STOP#
Not stopped
by CPU_STOP#
Stopped with
CPU_STOP#
RW
1
1
CPU1, CPU1#
Allow control of CPU1
with assertion of CPU_STOP#
Not stopped
by CPU_STOP#
Stopped with
CPU_STOP#
RW
1
2
CPU2, CPU2#
Allow control of CPU2
with assertion of CPU_STOP#
Not stopped
by CPU_STOP#
Stopped with
CPU_STOP#
RW
1
BYTE 4
3
PCIF0
Allow controlled by
Not stopped
Stopped with
RW
0
4
PCIF1
PCI_STOP# assertion
by PCI_STOP#
PCI_STOP#
RW
0
5
Reserved
RW
0
RW
0
RW
0
6
DOT96
7
Reserved
DOT96 power down drive mode
Driven in power down
Tristate
BYTE 5
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
0
CPU0, CPU0#
CPU0 PD drive mode
Driven in power down
Tristate in power down
RW
0
1
CPU1, CPU1#
CPU1 PD drive mode
Driven in power down
Tristate in power down
RW
0
2
CPU2, CPU2#
CPU2 PD drive mode
Driven in power down
Tristate in power down
RW
0
3
SRC[7:1], SRC[7:1]#
SRC PD drive mode
Driven in power down
Tristate in power down
RW
0
4
CPU0, CPU0#
CPU0 CPU_STOP drive mode
Driven in CPU_STOP#
Tristate when stopped
RW
0
5
CPU1, CPU1#
CPU1 CPU_STOP drive mode
Driven in CPU_STOP#
Tristate when stopped
RW
0
6
CPU2, CPU2#
CPU2 CPU_STOP drive mode
Driven in CPU_STOP#
Tristate when stopped
RW
0
7
SRC[7:1], SRC[7:1]#
SRC PCI_STOP drive mode
Driven in PCI_STOP
Tristate when stopped
RW
0
7
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 6
Bit
Output(s) Affected
Description / Function
0
CPU[2:0]
FSA latched value on power up
R
1
CPU[2:0]
FSB latched value on power up
R
2
CPU[2:0]
FSC latched value on power up
3
PCI, SRC
Software PCI_STOP control for
PCI and SRC CLK
Stop all PCI, PCIF, and
SRC which can be stopped
by PCI_STOP#
Software STOP
Disabled
RW
1
4
REF
REF drive strength
1x drive
2x drive
RW
1
5
Reserved
RW
0
Test clock mode entry control
Normal operation
Test mode, controlled
by Byte 6, Bit 7
RW
0
CPU, SRC, PCI
PCIF, REF,
USB48, DOT96
Only valid when Byte 6, Bit 6
is HIGH
Hi-Z
REF/N
RW
0
Output(s) Affected
Description / Function
0
1
6
7
0
1
Type
Power On
R
BYTE 7
Bit
Type
Power On
0
Vendor ID
R
1
1
Vendor ID
R
0
2
Vendor ID
R
1
3
Vendor ID
R
0
4
Revision ID
R
0
5
Revision ID
R
0
6
Revision ID
R
0
7
Revision ID
R
0
BYTE 8, LVDS CONTROL BYTE
Bit
Output(s) Affected
Description/Function
0
1
Type
Power On
0
LVDS
HW/ SMBus control
HW(1)
SW
RW
0
1
LVDS SSC EN
Spread spectrum enable
Off
On
RW
1
2
LVDS Enable
Output Enable
Disable
Enable
RW
1
3
SEL 100/96#
Select LVDS frequency
96MHz
100MHZ
RW
SEL 100/96#
4
S3
see SSC table
RW
0
5
S2
see SSC table
RW
0
6
S1
see SSC table
RW
0
7
S0
see SSC table
RW
0
NOTE:
1. If bit 0 is set to 0, LVDS output frequency is selected by HW SEL 100/96#. If bit 0 is set to 1, LVDS output frequency is selected by bit 3.
8
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 9
Bit
Output(s) Affected
0
1
2
3
4
5
6
7
One cycle read
Description / Function
0
1
Type
Power On
N Programming enable
LVDS PLL power down
disable
Disable
normal
enable
enable
Power down
SRC, PLL2, SSC enable
USB PLL power down
SRC PLL power down
CPU PLL power down
Only valid when Byte1 bit0 is 1
normal
normal
normal
disable
Power down
Power down
Power down
enable
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
1
Bit
Output(s) Affected
Description / Function
0
1
Type
Power On
0
1
2
3
4
5
6
7
SRC SMC0
SRC SMC1
SRC SMC2
Reserved
CPU SMC0
CPU SMC1
CPU SMC2
Reserved
SRC/PCI SSC control
see SMC table
RW
RW
RW
RW
RW
RW
RW
RW
1
0
0
0
1
0
0
0
Type
Power On
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
Type
Power On
RW
RW
RW
RW
RW
RW
RW
RW
0
1
1
0
1
0
0
1
BYTE 10
CPU PLL SSC control
see SMC table
BYTE 11
Bit
Output(s) Affected
Description / Function
0
1
2
3
4
5
6
7
CPU_N0, LSB
CPU_N1
CPU_N2
CPU_N3
CPU_N4
CPU_N5
CPU_N6
CPU_N7, MSB
CPU CLK = N* Resolution
see Resolution table
Bit
Output(s) Affected
Description / Function
0
1
2
3
4
5
6
7
SRC_N0, LSB
SRC_N1
SRC_N2
SRC_N3
SRC_N4
SRC_N5
SRC_N6
SRC_N7, MSB
0
1
BYTE 12
0
SRC f = N*SRC Resolution
Resolution = 0.666667
100MHz N= 150
9
1
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
BYTE 13
Bit
Output(s) Affected
0
1
2
3
4
5
6
7
48MHzStr0
48MHStr1
REFStr0
REFStr1
PCIStrC0
PCIStrC1
PCIFStr0
PCIFStr1
Description / Function
0
1
USB48MHz0 strength selection
REF strength selection
PCI strength selection
PCIF strength selection
Type
Power On
RW
RW
RW
RW
RW
RW
RW
RW
0
0
0
0
0
0
0
0
ELECTRICAL CHARACTERISTICS - INPUT / SUPPLY / COMMON OUTPUT
PARAMETERS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%
Symbol
Parameter
Test Conditions
Min.
Typ.
Max.
Unit
VIH
Input HIGH Voltage
3.3V ± 5%
2
—
VDD + 0.3
V
VIL
Input LOW Voltage
3.3V ± 5%
VSS - 0.3
—
0.8
V
VIH_FS
LOW Voltage, HIGH Threshold
For FSA.B.C test_mode
0.7
—
VDD + 0.3
V
VIL_FS
LOW Voltage, LOW Threshold
For FSA.B.C test_mode
VSS - 0.3
—
0.35
V
IIH
Input HIGH Current
VIN = VDD
–5
—
5
µA
IIL1
Input LOW Current
VIN = 0V, inputs with no pull-up resistors
–5
—
—
µA
IIL2
Input LOW Current
VIN = 0V, inputs with pull-up resistors
–200
—
—
µA
IDD3.3OP
Operating Supply Current
Full active, CL = full load
—
—
400
mA
IDD3.3PD
Powerdown Current
All differential pairs driven
—
—
70
mA
All differential pairs tri-stated
—
—
12
VDD = 3.3V
—
14.31818
—
MHz
—
—
7
nH
Logic inputs
Output pin capacitance
—
—
—
—
5
6
pF
XTAL_IN
—
—
5
FI
Input Frequency(1)
LPIN
Pin Inductance(2)
CIN
COUT
Input Capacitance(2)
CINX
COUTX
TSTAB
XTAL_OUT
—
—
12
Clock Stabilization(2,3)
From VDD power-up or de-assertion of PD to first clock
—
—
1.8
ms
Modulation Frequency(2)
Triangular modulation
30
—
33
KHz
TDRIVE_SRC(2)
SRC output enable after PCI_STOP# de-assertion
—
—
15
ns
TDRIVE_PD(2)
CPU output enable after PD de-assertion
—
—
300
us
TFALL_PD(2)
Fall time of PD
—
—
5
ns
TRISE_PD(3)
Rise time of PD
—
—
5
ns
TDRIVE_CPU_STOP#(2)
CPU output enable after CPU_STOP# de-assertion
—
—
10
us
TFALL_CPU_STOP#(2)
Fall time of CPU_STOP#
—
—
5
ns
TRISE_CPU_STOP#(3)
Rise time of CPU_STOP#
—
—
5
ns
NOTES:
1. Input frequency should be measured at the REF output pin and tuned to ideal 14.31818MHz to meet ppm frequency accuracy on PLL outputs.
2. This parameter is guaranteed by design, but not 100% production tested.
3. See TIMING DIAGRAMS for timing requirements.
10
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIAL PAIR(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
Parameter
Min.
Typ.
Max.
Unit
VO = VX
3000
—
—
Ω
Output HIGH Voltage
IOH = -1mA
2.4
—
—
V
VOL3
Output LOW Voltage
IOL = 1mA
—
—
0.4
V
VHIGH
Voltage HIGH(2)
Statistical measurement on single-ended signal using
660
—
1150
mV
VLOW
Voltage LOW(2)
oscilloscope math function
–300
—
150
VOVS
Max Voltage(2)
Measurement on single-ended signal using absolute value
—
—
1150
VUDS
Min Voltage(2)
–300
—
—
VCROSS(ABS)
Crossing Voltage (abs)(2)
250
—
550
mV
d - VCROSS
Crossing Voltage (var)(2)
Variation of crossing over all edges
—
—
140
mV
Long Accuracy(2,3)
See TPERIOD Min. - Max. values
–300
—
300
ppm
400MHz nominal / -0.5% spread
2.4993
—
2.5133
333.33MHz nominal / -0.5% spread
2.9991
—
3.016
266.66MHz nominal / -0.5% spread
3.7489
—
3.77
200MHz nominal / -0.5% spread
4.9985
—
5.0266
166.66MHz nominal / -0.5% spread
5.9982
—
6.032
133.33MHz nominal / -0.5% spread
7.4978
—
7.54
100MHz nominal / -0.5% spread
9.997
—
10.0533
96MHz nominal
10.4135
—
10.4198
400MHz nominal / -0.5% spread
2.4143
—
—
333.33MHz nominal / -0.5% spread
2.9141
—
—
266.66MHz nominal / -0.5% spread
3.6639
—
—
200MHz nominal / -0.5% spread
166.66MHz nominal / -0.5% spread
4.9135
5.9132
—
—
—
—
133.33MHz nominal / -0.5% spread
7.4128
—
—
100MHz nominal / -0.5% spread
9.912
—
—
Current Source Output Impedance(2)
VOH3
ZO
ppm
TPERIOD
TABSMIN
Average Period(3)
Absolute Min Period(2,3)
Test Conditions
96MHz nominal
mV
ns
ns
10.1635
—
—
tR
Rise Time(2)
VOL = 0.175V, VOH = 0.525V
175
—
700
ps
tF
Fall Time(2)
VOL = 0.175V, VOH = 0.525V
175
—
700
ps
d-tR
Rise Time Variation(2)
—
—
125
ps
d-tF
Fall Time Variation(2)
—
—
125
ps
dT3
Cycle(2)
45
—
55
%
Duty
Measurement from differential waveform
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
3. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
11
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS - CPU, SRC, AND DOT96 0.7 CURRENT MODE
DIFFERENTIAL PAIR, CONTINUED(1)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 2pF
Symbol
tSK3
tJCYC-CYC
Parameter
Skew, CPU[1:0](2)
Skew, CPU2(2)
Test Conditions
Min.
—
—
Typ.
—
—
Max.
100
250
Skew, SRC(2)
—
—
250
Jitter, Cycle to Cycle, CPU[1:0](2)
—
—
85
—
—
100
—
—
—
—
125
250
VT = 50%
Jitter, Cycle to Cycle, CPU2(2)
Measurement from differential waveform
SRC(2)
Jitter, Cycle to Cycle,
Jitter, Cycle to Cycle, DOT96(2)
Unit
ps
ps
NOTES:
1. SRC clock outputs run only at 100MHz.
2. This parameter is guaranteed by design, but not 100% production tested.
ELECTRICAL CHARACTERISTICS - PCICLK / PCICLK_F
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 30pF
Symbol
Parameter
Test Conditions
ppm
Static Error(1,2)
Min.
Typ.
Max.
Unit
See Tperiod Min. - Max. values
TPERIOD
Clock Period(2)
—
—
0
ppm
33.33MHz output nominal
29.991
—
30.009
ns
33.33MHz output spread
29.991
—
30.1598
VOH
Output HIGH Voltage
IOH = -1mA
2.4
—
—
V
VOL
Output LOW Voltage
IOL = 1mA
—
—
0.55
V
IOH
Output HIGH Current
VOH at Min. = 1V
-33
—
—
mA
VOH at Max. = 3.135V
—
—
-33
VOL at Min. = 1.95V
30
—
—
IOL
Output LOW Current
mA
VOL at Max. = 0.4V
—
—
38
Edge Rate(1)
Rising edge rate
1
—
4
V/ns
Edge Rate(1)
Falling edge rate
1
—
4
V/ns
tR1
Rise Time(1)
VOL = 0.8V, VOH = 2V
0.3
—
1.2
ns
tF1
Fall Time(1)
VOL = 0.8V, VOH = 2V
0.3
—
1.2
ns
Cycle(1)
dT1
Duty
VT = 1.5V
45
—
55
%
tSK1
Skew(1)
VT = 1.5V
—
—
500
ps
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
—
500
ps
tJCYC-CYC
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
12
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ELECTRICAL CHARACTERISTICS, 48MHZ, USB
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
ppm
Static Error(1,2)
See Tperiod Min. - Max. values
TPERIOD
Clock Period(2)
48MHz output nominal
VOH
Output HIGH Voltage
VOL
IOH
IOL
Min.
Typ.
Max.
Unit
—
—
0
ppm
20.8257
—
20.834
ns
IOH = -1mA
2.4
—
—
V
Output LOW Voltage
IOL = 1mA
—
—
0.55
V
Output HIGH Current
VOH at Min. = 1V
-29
—
—
mA
VOH at Max. = 3.135V
—
—
-23
VOL at Min. = 1.95V
29
—
—
Output LOW Current
mA
VOL at Max. = 0.4V
—
—
27
Edge Rate(1)
Rising edge rate
1
—
2
V/ns
Edge Rate(1)
Falling edge rate
1
—
2
V/ns
tR1
Rise Time(1)
VOL = 0.8V, VOH = 2V
0.5
—
1.2
ns
tF1
Fall Time(1)
VOL = 0.8V, VOH = 2V
0.5
—
1.2
ns
VT = 1.5V
45
—
55
%
—
—
350
ps
Min.
Typ.
Max.
Unit
—
—
0
ppm
69.827
—
69.855
ns
dT1
tJCYC-CYC
Duty
Cycle(1)
Jitter, Cycle to Cycle
NOTES:
1. This parameter is guaranteed by design, but not 100% production tested.
2. All long term accuracy and clock period specifications are guaranteed with the assumption that the REF output is at 14.31818MHz.
ELECTRICAL CHARACTERISTICS - REF-14.318MHZ
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C, Supply Voltage: VDD = 3.3V ± 5%; CL = 10 - 20pF
Symbol
Parameter
Test Conditions
Long Accuracy(1)
See Tperiod Min. - Max. values
Clock Period
14.318MHz output nominal
VOH
Output HIGH Voltage(1)
IOH = -1mA
2.4
—
—
V
VOL
Output LOW Voltage(1)
IOL = 1mA
—
—
0.4
V
IOH
Output HIGH Current
VOH at Min. = 1V
-33
—
—
mA
VOH at Max. = 3.135V
—
—
-33
VOL at Min. = 1.95V
30
—
—
ppm
TPERIOD
IOL
Output LOW Current
mA
VOL at Max. = 0.4V
—
—
38
Edge Rate(1)
Rising edge rate
1
—
4
V/ns
Edge Rate(1)
Falling edge rate
1
—
4
V/ns
tR1
Rise Time(1)
VOL = 0.8V, VOH = 2V
0.3
—
1.2
ns
tF1
Fall Time(1)
VOL = 0.8V, VOH = 2V
0.3
—
1.2
ns
dT1
Duty Cycle(1)
VT = 1.5V
45
—
55
%
Jitter, Cycle to Cycle(1)
VT = 1.5V
—
—
1000
ps
tJCYC-CYC
NOTE:
1. This parameter is guaranteed by design, but not 100% production tested.
13
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PCI STOP FUNCTIONALITY
The PCI_STOP# signal is on an active low input controlling PCI and SRC outputs. If PCIF[1:0] and SRC clocks can be set to be free-running through SMBus
programming, they will ignore both the PCI_STOP# pin and the PCI_STOP register bit.
PCI_STOP#
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
DOT96
DOT96#
REF
1
Normal
Normal
Normal
Normal
33MHz
48MHz
Normal
Normal
14.318MHz
0
Normal
Normal
IREF * 6 or float
Low
Low
48MHz
Normal
Normal
14.318MHz
PCI_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
The clock samples the PCI_STOP# signal on a rising edge of PCIF clock. After detecting the PCI_STOP# assertion low, all PCI[6:0] and stoppable PCIF[1:0]
clocks will latch low on their next high to low transition. After the PCI clocks are latched low, the SRC clock, (if set to stoppable) will latch high at IREF * 6 (or
tristate if Byte 2 Bit 6 = 1) upon its next low to high transition and the SRC# will latch low as shown below.
tSU
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
PCI_STOP# - DE-ASSERTION
The de-assertion of the PCI_STOP# signal is to be sampled on the rising edge of the PCIF free running clock domain. After detecting PCI_STOP# de-assertion,
all PCI[6:0], stoppable PCIF[1:0] and stoppable SRC clocks will resume in a glitch free manner.
tSU
tDRIVE_SRC
PCI_STOP#
PCIF[1:0] 33MHz
PCI[3:0] 33MHz
SRC 100MHz
SRC# 100MHz
14
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
CPU STOP FUNCTIONALITY
The CPU_STOP# signal is an active low input controlling the CPU outputs. This signal can be asserted asynchronously.
CPU_STOP#
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
DOT96
DOT96#
REF
1
Normal
Normal
Normal
Normal
33MHz
48MHz
Normal
Normal
14.318MHz
0
IREF * 6 or float
Low
Normal
Normal
33MHz
48MHz
Normal
Normal
14.318MHz
CPU_STOP# ASSERTION (TRANSITION FROM ‘1’ TO ‘0’)
Asserting CPU_STOP# pin stops all CPU outputs that are set to be stoppable after their next transition. When the SMBus CPU_STOP tri-state bit corresponding
to the CPU output of interest is programmed to a ‘0’, CPU output will stop CPU_True = High and CPU_Complement = Low. When the SMBus CPU_STOP#
tri-state bit corresponding to the CPU output of interest is programmed to a ‘1’, CPU outputs will be tri-stated.
CPU_STOP#
CPU
CPU#
CPU_STOP# - DE-ASSERTION (TRANSITION FROM ‘0’ TO ‘1’)
With the de-assertion of CPU_STOP# all stopped CPU outputs will resume without a glitch. The maximum latency from the de-assertion to active outputs
is two to six CPU clock periods. If the control register tristate bit corresponding to the output of interest is programmed to ‘1’, then the stopped CPU outputs will
be driven High within 10nS of CPU_STOP# de-assertion to a voltage greater than 200mV.
CPU_STOP#
CPU
CPU#
CPU Internal
tDRIVE_CPU_Stop
10nS > 200mV
15
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD, POWER DOWN
PD is an asynchronous active high input used to shut off all clocks cleanly prior to clock power. When PD is asserted high all clocks will be driven low before
turning off the VCO. In PD de-assertion all clocks will start without glitches.
PD
CPU
CPU#
SRC
SRC#
PCIF/PCI
USB
0
Normal
1
IREF * 2 or float
Normal
Normal
Normal
33MHz
Float
IREF * 2 or float
Float
Low
PD ASSERTION
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
16
DOT96
DOT96#
REF
48MHz
Normal
Normal
14.318MHz
Low
IREF * 2 or float
Float
Low
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PD DE-ASSERTION
tSTABLE <1.8mS
PD
CPU 133MHz
CPU# 133MHz
SRC 100MHz
SRC# 100MHz
USB 48MHz
PCI 33MHz
REF 14.31818
tDRIVE_PWRDWN
<300µS, <200mV
17
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
DIFFERENTIAL CLOCK TRISTATE
To minimize power consumption, CPU[2:0] clock outputs are individually configurable through SMBus to be driven or tristated during PD and CPU_STOP#
mode and the SRC clock is configurable to be driven or tristated during PCI_STOP# and PD mode. Each differential clock (SRC, CPU[2:0]) output can be
disabled by setting the corresponding output’s register OE bit to “0” (disable). Disabled outputs are to be tristated regardless of “CPU_STOP”, “SRC_STOP”
and “PD” register bit settings.
Signal
Pin PD
Pin CPU_STOP#
CPU_STOPTristate Bit
PD Tristate Bit
Non-Stoppable Outputs
Stoppable Outputs
CPU
0
1
X
X
Running
Running
CPU
0
0
0
X
Running
Driven at IREF x 6
CPU
0
0
1
X
Running
Tristate
CPU
1
X
X
0
Driven at IREF x 2
Driven at IREF x 2
CPU
1
X
X
1
Tristate
Tristate
NOTES:
1. Each output has four corresponding control register bits; OE, PD, CPU_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
Signal
Pin PD
Pin PCI_STOP#
PCI_STOPTristate Bit
PD Tristate Bit
Non-Stoppable Outputs
Stoppable Outputs
SRC
0
1
X
X
Running
Running
SRC
0
0
0
X
Running
Driven at IREF x 6
SRC
0
0
1
X
Running
Tristate
SRC
1
X
X
0
Driven at IREF x 2
Driven at IREF x 2
SRC
1
X
X
1
Tristate
Tristate
NOTES:
1. SRC output has four corresponding control register bits; OE, PD, SRC_STOP, and “Free Running”.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
TRISTATE DOT96 CLOCK CONTROL
Signal
Pin PD
PD Tristate Bit
Output
DOT96
1
X
Running
DOT96
0
0
Driven at IREF x 2
DOT96
0
1
Tristate
NOTES:
1. DOT output has two corresponding control register bits; OE and PD.
2. IREF x 6 and IREF x 2 is the output current in the corresponding mode.
3. See CONTROL REGISTERS section for bit address.
18
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
Symbol
Parameter
Min.
Typ.
Max.
Unit
tR1
Clock Rise Time(1,2,3)
175
—
700
ps
tF1
Clock Fall Time(1,2,3)
175
—
700
ps
∆ tR
Clock Rise Time Variation(2,3,4)
—
—
125
ps
∆ tF
Clock Fall Time Variation(2,3,4)
—
—
125
ps
Rise/Fall Matching(2,3,5)
—
—
20
%
VHIGH
Voltage HIGH(2,3,6)
660
700
850
mV
VLOW
Voltage LOW (2,3,7)
-150
0
—
mV
VCROSS(ABS)
Crossing Voltage (abs)(2,3,8,9,10)
250
—
550
mV
VCROSS(REL)
Crossing Voltage (rel)(2,3,10,11)
TOTAL ∆ VCROSS
tJCYC-CYC
dT3
Calc.
—
Calc.
Total Variation of VCROSS Over All Edges(2,3,12)
—
—
140
mV
Cycle-to-Cycle Jitter(2,13)
—
—
350
ps
Duty
Cycle(2,13)
45
—
55
%
VOVS
Maximum Voltage Allowed at Output (overshoot)(2,3,14)
—
—
VHIGH + 0.3V
V
VUDS
Minimum Voltage Allowed at Output (undershoot)(2,3,15)
-0.3
—
—
V
VRB
Ringback Margin(2,3)
n/a
—
0.2
V
NOTES:
1. Measured from VOL = 1.75V to VOH =0.525V. Only valid for Rising LVDS and Falling LVDS#. Signal must be monotonic through the VOL to VOH region for tRISE and tFALL.
2. Test configuration is Rs = 32.2Ω, Rp = 49.9Ω, 2pF.
3. Measurement taken from single-ended waveform.
4. Measured with oscilloscope, averaging off, using Min. Max. statistics. Variation is the delta between Min. and Max.
5. Measured with oscilloscope, averaging off, the difference between the tRISE (average) of LVDS versus the tFALL (average) of LVDS#.
6. VHIGH is defined as the statistical average HIGH value as obtained by using the oscilloscope VHIGH math function.
7. VLOW is defined as the statistical average LOW value as obtained by using the oscilloscope VLOW math function.
8. Measured at crossing point where the instantaneous voltage value of the rising edge of LVDS equals the falling edge of LVDS#.
9. This measurement refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing.
10. The crossing point must meet the absolute and relative crossing point specifications simultaniously.
11. VCROSS (rel) Min. and Max. are derived using the following: VCROSS (rel) Min. = 0.25V + 0.5 (VHAVG - 0.7V), VCROSS (rel) Max. = 0.55V + 0.5 (0.7V - VHAVG).
12. ∆ VCROSS is defined as the total variation of all crossing voltages of Rising LVDS and Falling LVDS#. This is the maximum allowed variance in VCROSS for any particular system.
13. Measurement is taken from differential waveform.
14. Overshoot is defined as the absolute value of the maximum voltage.
15. Undershoot is defined as the absolute value of the minimum voltage.
19
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS AVERAGE PERIOD, TPERIOD(1,2,3,4)
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
96MHz
Spread
Min.
100MHz
Max.
Min.
Max.
Unit
0% (no spread)
10.406
10.427
9.99
10.01
ns
0.8% down-spread
10.406
10.511
9.99
10.09
ns
1% down-spread
10.406
10.531
9.99
10.11
ns
1.25% down-spread
10.406
10.557
9.99
10.135
ns
1.5% down-spread
10.406
10.583
9.99
10.16
ns
1.75% down-spread
10.406
10.61
9.99
10.185
ns
2% down-spread
10.406
10.636
9.99
10.21
ns
2.5% down-spread
10.406
10.688
9.99
10.26
ns
3% down-spread
10.406
10.74
9.99
10.31
ns
±0.3% down-spread
10.375
10.458
9.96
10.04
ns
±0.4% down-spread
10.365
10.469
9.95
10.05
ns
±0.5% down-spread
10.354
10.479
9.94
10.06
ns
±0.6% down-spread
10.344
10.49
9.93
10.07
ns
±0.8% down-spread
10.323
10.511
9.91
10.09
ns
±1% down-spread
10.302
10.531
9.89
10.11
ns
±1.25% down-spread
10.276
10.557
9.865
10.135
ns
±1.5% down-spread
10.25
10.583
9.84
10.16
ns
NOTES:
1. Test configuration is Rs = 32.2Ω, Rp = 49.9Ω, 2pF.
2. The average period over any 1µS period of tiime must be greater than the minimum and less than the maximum specified period.
3. Measurement is taken from differential waveform.
4. Calculated using a ±0.1% accuracy in spread modulation. Assumes 300ppm long term accuracy on CLKIN.
tRISE (LVDS)
VOH = 0.525V
LVDS
LVDS#
VCROSS
VOL = 0.175V
tFALL (LVDS#)
Single-Ended Measurement Point for tRISE and tFALL
20
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
MISCELLANEOUS AC TIMING REQUIREMENTS
Following Conditions Apply Unless Otherwise Specified:
Operating Condition: TA = 0°C to +70°C
Symbol
tPZL
Parameter
Output Enable Delay (All Outputs)
(1)
Min.
Typ.
Max.
Unit
0
—
10
µs
0
—
10
µs
—
—
3
ms
—
—
3
ms
tPZH
tPLZ
Output Disable Delay (All Outputs)(1)
tPHZ
tSTABLE
All Clock Stabilization from Power-Up(2)
tSPREAD
Setting Period for Spread Selection Change
(2,3)
NOTES:
1. These specifications apply to the LVDS and SMBus pins. These pins must be tri-stated when PWRDWN is asserted. LVDS is driven differential when PWRDWN is de-asserted unless
it is disabled.
2. The time specified is from when VDD achieves its nominal operating level (typical condition VDD = 3.3V) and PWRDWN is de-asserted until the frequency output is stable and operating
within specification.
3. The time specified is measured from the spread selection change or output frequency change until the LVDS clock is operating at the new spread modulation and frequency.
If there is another change in spread selection or output frequency during the tSPREAD settling period, then the settling period start resets to the most recent change in spread selection
and output frequency.
21
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
PWRDWN (POWER DOWN) CLARIFICATION
PWRDWN
CLOCK VCO
On
Off
LVDS
tPHZ
LVDS#
PWRDWN Assertion
VDD
PWRDWN
CLOCK VCO
Off
Starting
tSTABLE
LVDS
LVDS#
tPZH
PWRDWN De-Assertion
22
Stable
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
LVDS SYSTEM IMPLEMENTATION
Clock
Rs
Rp
Unit
LVDS Clock
33.2
49.9
Ω
5%
1%
33Ω
5%
CV125
Clock
LVDS
TLA
33Ω
5%
Clock#
LVDS#
475Ω
1%
TLB
49.9Ω
1%
49.9Ω
1%
2pF
5%
Test Load Board Configuration
23
2pF
5%
IDTCV125
PROGRAMMABLE FLEXPC CLOCK FOR P4 PROCESSOR
COMMERCIAL TEMPERATURE RANGE
ORDERING INFORMATION
XXX
IDTCV
Device Type
XX
Package
X
Grade
CORPORATE HEADQUARTERS
2975 Stender Way
Santa Clara, CA 95054
Blank
Commercial Temperature Range
(0°C to +70°C)
PA
PAG
Thin Small Shrink Outline Package
TSSOP - Green
125
Programmable FlexPC Clock for P4 Processor
for SALES:
800-345-7015 or 408-727-6116
fax: 408-492-8674
www.idt.com
24
for Tech Support:
[email protected]
(408) 654-6459