IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 OptiMOS®-T2 Power-Transistor Product Summary V DS 55 R DS(on),max (SMD version) 21.3 ID 25 V mΩ A Features • N-channel - Enhancement mode PG-TO263-3-2 • Automotive AEC Q101 qualified PG-TO262-3-1 PG-TO220-3-1 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green product (RoHS compliant) • 100% Avalanche tested Type Package Marking IPB25N06S3L-22 PG-TO263-3-2 3N06L22 IPI25N06S3L-22 PG-TO262-3-1 3N06L22 IPP25N06S3L-22 PG-TO220-3-1 3N06L22 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current1) ID Conditions T C=25 °C, V GS=10 V T C=100 °C, V GS=10 V2) Value 25 Unit A 25 Pulsed drain current2) I D,pulse T C=25 °C 100 Avalanche energy, single pulse2) E AS I D=12.5 A 120 mJ Avalanche current, single pulse I AS 25 A Gate source voltage3) V GS ±16 V Power dissipation P tot 50 W Operating and storage temperature T j, T stg -55 ... +175 °C T C=25 °C IEC climatic category; DIN IEC 68-1 Rev. 1.1 55/175/56 page 1 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics2) Thermal resistance, junction - case R thJC - - 3.3 Thermal resistance, junction ambient, leaded R thJA - - 62 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area4) - - 40 K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0 V, I D= 1 mA 55 - - Gate threshold voltage V GS(th) V DS=V GS, I D=20 µA 1.2 1.7 2.2 Zero gate voltage drain current I DSS V DS=55 V, V GS=0 V, T j=25 °C - 0.01 1 - 1 100 V DS=55 V, V GS=0 V, T j=125 °C2) V µA Gate-source leakage current I GSS V GS=16 V, V DS=0 V - 1 100 nA Drain-source on-state resistance R DS(on) V GS=5 V, I D=11 A - 32.9 39.9 mΩ V GS=5 V, I D=11 A, SMD version - 32.6 39.6 V GS=10 V, I D=17 A - 18.4 21.6 V GS=10 V, I D=17 A, SMD version - 18.1 21.3 Rev. 1.1 page 2 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 Parameter Symbol Values Conditions Unit min. typ. max. - 2260 - - 283 - Dynamic characteristics2) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 270 - Turn-on delay time t d(on) - 9 - Rise time tr - 26 - Turn-off delay time t d(off) - 30 - Fall time tf - 43 - Gate to source charge Q gs - 11 - Gate to drain charge Q gd - 6 - Gate charge total Qg - 31 47 Gate plateau voltage V plateau - 4.7 - V - - 25 A - - 100 0.6 0.9 1.3 V - 15 - ns - 15 - nC V GS=0 V, V DS=25 V, f =1 MHz V DD=27.5 V, V GS=10 V, I D=25 A, R G=14.8 Ω pF ns Gate Charge Characteristics2) V DD=11 V, I D=25 A, V GS=0 to 10 V nC Reverse Diode Diode continous forward current2) IS Diode pulse current2) I S,pulse Diode forward voltage V SD Reverse recovery time2) t rr Reverse recovery charge2) Q rr T C=25 °C V GS=0 V, I F=25 A, T j=25 °C V R=27.5 V, I F=I S, di F/dt =100 A/µs 1) Current is limited by bondwire; with an R thJC = 3.3 K/W the chip is able to carry 31 A at 25°C. For detailed information see Application Note ANPS071E 2) Defined by design. Not subject to production test. 3) Qualified at -5V and +16V. 4) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.1 page 3 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 1 Power dissipation 2 Drain current P tot = f(T C); V GS ≥ 4 V I D = f(T C); V GS ≥ 4 V 30 50 40 20 I D [A] P tot [W] 30 20 10 10 0 0 0 50 100 150 0 200 50 T C [°C] 100 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 1000 101 0.1 100 100 1 µs Z thJC [K/W] 0.05 I D [A] 10 µs 100 µs 10-1 0.05 1 ms 10 10-2 single pulse 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] V DS [V] Rev. 1.1 10-7 page 4 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 5 Typ. output characteristics 6 Typ. drain-source on resistance I D = f(V DS); T j = 25 °C R DS(on) = f(I D); T j = 25 °C parameter: V GS parameter: V GS 100 60 8V 10 V10V 8V 55 4.5 V 7V 80 5V 5.5 V 50 45 6.5 V R DS(on) [mΩ] 60 I D [A] 6V 5.5 V 40 40 35 6V 30 6.5 V 20 5V 25 4.5 V 20 7V 8V 10 V 15 0 10 0 2 4 6 0 10 20 V DS [V] 30 40 50 I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = 4 V R DS(on) = f(T j); I D = 25 A; V GS = 10 V parameter: T j 35 60 50 30 I D [A] R DS(on) [mΩ] -55 °C 40 25 °C 30 175 °C 25 20 20 15 10 0 10 0 1 2 3 4 5 6 Rev. 1.1 -60 -20 20 60 100 140 180 T j [°C] V GS [V] page 5 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: I D 104 3 2.5 Ciss 200µA C [pF] V GS(th) [V] 2 1.5 20µA 103 Coss 1 Crss 0.5 0 -60 -20 20 60 100 140 0 180 5 10 T j [°C] 15 20 12 Typ. avalanche characteristics IF = f(VSD) I AV = f(t AV) parameter: T j parameter: T j(start) 100 I AV [A] 102 I F [A] 30 V DS [V] 11 Typical forward diode characteristicis 101 175 °C 150°C 100°C 25°C 10 25 °C 100 1 0 0.2 0.4 0.6 0.8 1 1.2 1.4 V SD [V] Rev. 1.1 25 0.1 1 10 100 1000 t AV [µs] page 6 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 13 Typical avalanche energy 14 Drain-source breakdown voltage E AS = f(T j); V BR(DSS) = (T j); I D = 1 mA parameter: I D 66 280 64 6.25 A 240 62 60 V BR(DSS) [V] E AS [mJ] 200 160 12.5 A 120 58 56 54 52 80 25 A 50 40 48 0 46 0 50 100 150 200 -60 -20 20 T j [°C] 60 100 140 180 T j [°C] 15 Typ. gate charge 16 Gate charge waveforms V GS = f(Q gate); I D = 25 A pulsed parameter: V DD 12 11 V 10 44 V VG Qg V GS [V] 8 6 4 Qgat 2 Qg Qg 0 0 10 20 30 40 50 Q gate [nC] Rev. 1.1 page 7 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2007 All Rights Reserved. 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Rev. 1.1 page 8 2007-11-07 IPB25N06S3L-22 IPI25N06S3L-22, IPP25N06S3L-22 Revision History Version Date Changes Data Sheet 2.1 15.12.2006 Removal of ordering code Data Sheet 2.1 15.12.2006 Update of Infineon Logo Data Sheet 2.1 Implementation of avalanche 15.12.2006 current single pulse Data Sheet 2.1 15.12.2006 Removal of ESD class Data Sheet 2.1 15.12.2006 Update of Infineon address Data Sheet 2.1 Removal of foot note 3, avalanche 15.12.2006 diagrams Data Sheet 2.1 15.12.2006 Update of Qrr and trr typ Data Sheet 2.1 15.12.2006 Update of disclaimer Data Sheet 2.1 Implementation of RoHS and AEC 15.12.2006 logo, update of feature list Data Sheet 1.1 07.11.2007 Update of data sheet layout Data Sheet 1.1 07.11.2007 Adaptation of Ias Data Sheet 1.1 implementation of footnote 2 for 07.11.2007 Eas specification Data Sheet 1.1 removal of Vdg specification from 07.11.2007 data sheet Rev. 1.1 page 9 2007-11-07