IPD70P04P4L-08 OptiMOS®-P2 Power-Transistor Product Summary V DS -40 V R DS(on) 7.8 mW ID -70 A Features • P-channel - Logic Level - Enhancement mode • AEC qualified PG-TO252-3-313 • MSL1 up to 260°C peak reflow • 175°C operating temperature • Green package (RoHS compliant) • 100% Avalanche tested Type Package Marking IPD70P04P4L-08 PG-TO252-3-313 4P04L08 Maximum ratings, at T j=25 °C, unless otherwise specified Parameter Symbol Continuous drain current ID Conditions T C=25°C, V GS=-10V T C=100°C, Value -70 V GS=-10V1) -55 Unit A Pulsed drain current1) I D,pulse T C=25°C -280 Avalanche energy, single pulse1) E AS I D=-35A 24 mJ Avalanche current, single pulse I AS - -70 A Gate source voltage V GS - ±162) V Power dissipation P tot T C=25 °C 75 W Operating and storage temperature T j, T stg - -55 ... +175 °C IEC climatic category; DIN IEC 68-1 - - 55/175/56 Rev. 1.0 page 1 2011-03-14 IPD70P04P4L-08 Parameter Symbol Values Conditions Unit min. typ. max. Thermal characteristics1) Thermal resistance, junction - case R thJC - - - 2.0 SMD version, device on PCB R thJA minimal footprint - - 62 6 cm2 cooling area3) - - 40 K/W Electrical characteristics, at T j=25 °C, unless otherwise specified Static characteristics Drain-source breakdown voltage V (BR)DSS V GS=0V, I D= -1mA -40 - - Gate threshold voltage V GS(th) V DS=V GS, I D=-120µA -1.2 -1.7 -2.2 Zero gate voltage drain current I DSS V DS=-32V, V GS=0V, T j=25°C - -0.05 -1 T j=125°C1) - -20 -200 V DS=-32V, V GS=0V, V µA Gate-source leakage current I GSS V GS=-16V, V DS=0V - - -100 nA Drain-source on-state resistance R DS(on) V GS=-4.5V, I D=-40A - 9.0 12.9 mW V GS=-10V, I D=-70A - 5.7 7.8 Rev. 1.0 page 2 2011-03-14 IPD70P04P4L-08 Parameter Symbol Values Conditions Unit min. typ. max. - 4177 5430 - 1185 1778 Dynamic characteristics1) Input capacitance C iss Output capacitance C oss Reverse transfer capacitance Crss - 45 90 Turn-on delay time t d(on) - 12 - Rise time tr - 10 - Turn-off delay time t d(off) - 50 - Fall time tf - 41 - Gate to source charge Q gs - 14 18 Gate to drain charge Q gd - 10 20 Gate charge total Qg - 71 92 Gate plateau voltage V plateau - -3.5 - V - - -70 A - - -280 - -1 -1.3 V - 46 - ns - 43 - nC V GS=0V, V DS=-25V, f =1MHz V DD=-20V, V GS=-10V, I D=-70A, R G=3.5W pF ns Gate Charge Characteristics1) V DD=-32V, I D=-70A, V GS=0 to -10V nC Reverse Diode Diode continous forward current1) IS Diode pulse current1) I S,pulse Diode forward voltage V SD Reverse recovery time1) t rr Reverse recovery charge1) Q rr T C=25°C V GS=0V, I F=-70A, T j=25°C V R=-20V, I F=-50A, di F/dt =-100A/µs 1) Defined by design. Not subject to production test. 2) VGS=+5V/-16V according AEC; VGS=+16V for max 168h at TJ=175°C 3) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm2 (one layer, 70 µm thick) copper area for drain connection. PCB is vertical in still air. Rev. 1.0 page 3 2011-03-14 IPD70P04P4L-08 2 Drain current P tot = f(T C); V GS ≤ -6V I D = f(T C); V GS = -10V 80 80 60 60 -I D [A] P tot [W] 1 Power dissipation 40 20 40 20 0 0 0 50 100 150 200 0 50 100 T C [°C] 150 200 T C [°C] 3 Safe operating area 4 Max. transient thermal impedance I D = f(V DS); T C = 25 °C; D = 0 Z thJC = f(t p) parameter: t p parameter: D =t p/T 101 1000 1 µs 0.5 100 10 µs 100 0.1 Z thJC [K/W] -I D [A] 100 µs 1 ms 0.05 10-1 0.01 10 10-2 10-3 1 0.1 1 10 100 10-6 10-5 10-4 10-3 10-2 10-1 100 t p [s] -V DS [V] Rev. 1.0 single pulse page 4 2011-03-14 IPD70P04P4L-08 5 Typ. output characteristics 6 Typ. drain-source on-state resistance I D = f(V DS); T j = 25 °C R DS(on) = (I D); T j = 25 °C parameter: -V GS parameter: -V GS 60 280 2.8V 3V 10V 5V 3.5V 55 50 45 210 40 R DS(on) [mW] -I D [A] 4.5V 140 35 30 25 4V 20 15 70 3.5V 4V 4.5V 5V 10V 10 5 3V 0 0 0 1 2 3 4 5 0 6 20 40 -V DS [V] 60 -I D [A] 7 Typ. transfer characteristics 8 Typ. drain-source on-state resistance I D = f(V GS); V DS = -6V R DS(on) = f(T j); I D = -70 A; V GS = -10 V parameter: T j 280 13 12 210 R DS(on) [mW] -I D [A] 11 140 10 9 8 70 7 175 °C 25 °C -55 °C 6 0 2 3 4 5 6 -20 20 60 100 140 180 T j [°C] -V GS [V] Rev. 1.0 -60 page 5 2011-03-14 IPD70P04P4L-08 9 Typ. gate threshold voltage 10 Typ. capacitances V GS(th) = f(T j); V GS = V DS C = f(V DS); V GS = 0 V; f = 1 MHz parameter: -I D 2.4 105 2 104 Ciss C [pF] -V GS(th) [V] 1200µA 1.6 120µA Coss 103 102 1.2 Crss 101 0.8 -60 -20 20 60 100 140 0 180 5 10 T j [°C] 15 20 25 30 140 180 -V DS [V] 11 Typical forward diode characteristicis 12 Drain-source breakdown voltage IF = f(VSD) V BR(DSS) = f(T j); I D = -1 mA parameter: T j 103 45 44 43 42 -I F [A] -V BR(DSS) [V] 102 41 40 39 175 °C 25 °C 101 38 37 36 100 35 0 0.4 0.8 1.2 1.6 -V SD [V] Rev. 1.0 -60 -20 20 60 100 T j [°C] page 6 2011-03-14 IPD70P04P4L-08 13 Typ. gate charge 14 Gate charge waveforms V GS = f(Q gate); I D = -70 A pulsed parameter: V DD 12 V GS 10 Qg -V GS [V] 8 -32V -8V 6 4 Q gate 2 Q gs Q gd 0 0 10 20 30 40 50 60 Q gate [nC] Rev. 1.0 page 7 2011-03-14 IPD70P04P4L-08 Published by Infineon Technologies AG 81726 Munich, Germany © Infineon Technologies AG 2011 All Rights Reserved. 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Infineon Technologies components may be used in life-support devices or systems only with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Rev. 1.0 page 8 2011-03-14 IPD70P04P4L-08 Revision History Version Rev. 1.0 Date Changes 0.1 08.03.2010 Initial Target Data Sheet 0.2 20.12.2010 Preliminary Data Sheet 1.0 14.03.2011 Final Data Sheet page 9 2011-03-14