IRF IRLMS1503

PD - 91508D
IRLMS1503
HEXFET® Power MOSFET
l
l
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Generation V Technology
Micro6 Package Style
Ultra Low RDS(on)
N-Channel MOSFET
Description
Fifth Generation HEXFET® power MOSFETs from
International Rectifier utilize advanced processing
techniques to achieve extremely low on-resistance
per silicon area. This benefit, combined with the fast
switching speed and ruggedized device design that
HEXFET® power MOSFETs are well known for,
provides the designer with an extremely efficient and
reliable device for use in a wide variety of applications.
A
D
D
1
6
D
2
5
D
G
3
4
S
VDSS = 30V
RDS(on) = 0.10Ω
Top View
The Micro6 package with its customized leadframe
produces a HEXFET® power MOSFET with RDS(on)
60% less than a similar size SOT-23. This package is
ideal for applications where printed circuit board space
is at a premium. It's unique thermal design and RDS(on)
reduction enables a current-handling increase of
nearly 300% compared to the SOT-23.
Micro6
Absolute Maximum Ratings
Parameter
ID @ TA = 25°C
ID @ TA = 70°C
IDM
PD @TA = 25°C
V GS
dv/dt
TJ, TSTG
Max.
Continuous Drain Current, VGS @ 10V
Continuous Drain Current, VGS @ 10V
Pulsed Drain Current 
Power Dissipation
Linear Derating Factor
Gate-to-Source Voltage
Peak Diode Recovery dv/dt ‚
Junction and Storage Temperature Range
Units
3.2
2.6
18
1.7
13
± 20
5.0
-55 to + 150
A
W
mW/°C
V
V/ns
°C
Thermal Resistance Ratings
Parameter
RθJA
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Maximum Junction-to-Ambient „
Min.
Typ.
–––
–––
Max
Units
75
°C/W
1
3/17/04
IRLMS1503
Electrical Characteristics @ TJ = 25°C (unless otherwise specified)
Parameter
Drain-to-Source Breakdown Voltage
∆V(BR)DSS/∆TJ Breakdown Voltage Temp. Coefficient
V (BR)DSS
RDS(on)
Static Drain-to-Source On-Resistance
VGS(th)
gfs
Gate Threshold Voltage
Forward Transconductance
IDSS
Drain-to-Source Leakage Current
I GSS
Qg
Qgs
Qgd
td(on)
tr
td(off)
tf
Ciss
Coss
Crss
Gate-to-Source Forward Leakage
Gate-to-Source Reverse Leakage
Total Gate Charge
Gate-to-Source Charge
Gate-to-Drain ("Miller") Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Min.
30
–––
–––
–––
1.0
1.1
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
–––
Typ.
–––
0.037
–––
–––
–––
–––
–––
–––
–––
–––
6.4
1.1
1.9
4.6
4.4
10
2.0
210
90
32
Max. Units
Conditions
–––
V
V GS = 0V, ID = 250µA
––– V/°C Reference to 25°C, ID = 1mA
0.100
V GS = 10V, ID = 2.2A ƒ
Ω
0.20
V GS = 4.5V, ID = 1.1A ƒ
–––
V
V DS = V GS, ID = 250µA
–––
S
V DS = 10V, I D = 1.1A
1.0
V DS = 24V, V GS = 0V
µA
25
V DS = 24V, VGS = 0V, TJ = 125°C
-100
V GS = -20V
nA
100
V GS = 20V
9.6
I D = 2.2A
1.7
nC V DS = 24V
2.8
V GS = 10V, See Fig. 6 and 9 ƒ
–––
V DD = 15V
–––
I D = 2.2A
ns
–––
R G = 6.0Ω
–––
R D = 6.7Ω, See Fig. 10 ƒ
–––
V GS = 0V
–––
pF
V DS = 25V
–––
ƒ = 1.0MHz, See Fig. 5
Source-Drain Ratings and Characteristics
IS
I SM
V SD
trr
Qrr
Parameter
Continuous Source Current
(Body Diode)
Pulsed Source Current
(Body Diode) 
Diode Forward Voltage
Reverse Recovery Time
Reverse RecoveryCharge
Min. Typ. Max. Units
–––
–––
1.7
–––
–––
18
–––
–––
–––
–––
36
39
1.2
54
58
A
V
ns
nC
Conditions
MOSFET symbol
showing the
G
integral reverse
p-n junction diode.
TJ = 25°C, IS = 2.2A, VGS = 0V ƒ
TJ = 25°C, I F = 2.2A
di/dt = 100A/µs ƒ
D
S
Notes:
 Repetitive rating; pulse width limited by
ƒ Pulse width ≤ 300µs; duty cycle ≤ 2%.
‚ ISD ≤ 2.2A, di/dt ≤ 150A/µs, VDD ≤ V(BR)DSS,
„ Surface mounted on FR-4 board, t ≤ 5sec.
max. junction temperature. ( See fig. 11 )
TJ ≤ 150°C
2
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IRLMS1503
100
100
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 3.0V
I D , Drain-to-Source Current (A)
I D , Drain-to-Source Current (A)
10
1
3.0V
20µs PULSE WIDTH
TJ = 25 °C
0.1
0.1
1
10
1
RDS(on) , Drain-to-Source On Resistance
(Normalized)
I D , Drain-to-Source Current (A)
2.0
TJ = 25 ° C
TJ = 150 ° C
1
V DS = 10V
20µs PULSE WIDTH
5.0
6.0
7.0
VGS , Gate-to-Source Voltage (V)
Fig 3. Typical Transfer Characteristics
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1
10
Fig 2. Typical Output Characteristics
100
4.0
20µs PULSE WIDTH
TJ = 150 °C
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
10
3.0V
0.1
0.1
10
VDS , Drain-to-Source Voltage (V)
0.1
3.0
VGS
15V
10V
7.0V
5.5V
4.5V
4.0V
3.5V
BOTTOM 3.0V
TOP
TOP
8.0
ID = 2.2A
1.5
1.0
0.5
0.0
-60 -40 -20
VGS = 10V
0
20
40
60
80 100 120 140 160
TJ , Junction Temperature ( °C)
Fig 4. Normalized On-Resistance
Vs. Temperature
2
IRLMS1503
VGS = 0V,
f = 1MHz
Ciss = Cgs + Cgd , Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
C, Capacitance (pF)
300
250
Ciss
200
Coss
150
100
Crss
50
20
VGS , Gate-to-Source Voltage (V)
350
0
1
10
ID = 2.2A
VDS = 24V
VDS = 15V
16
12
8
4
FOR TEST CIRCUIT
SEE FIGURE 9
0
100
0
VDS , Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance Vs.
Drain-to-Source Voltage
4
6
8
10
Fig 6. Typical Gate Charge Vs.
Gate-to-Source Voltage
100
100
OPERATION IN THIS AREA LIMITED
BY RDS(on)
ID , Drain Current (A)
ISD , Reverse Drain Current (A)
2
QG , Total Gate Charge (nC)
10
TJ = 150 ° C
TJ = 25 ° C
1
10us
10
100us
1ms
1
10ms
0.1
0.4
V GS = 0 V
0.6
0.8
1.0
1.2
1.4
VSD ,Source-to-Drain Voltage (V)
Fig 7. Typical Source-Drain Diode
Forward Voltage
4
1.6
TC = 25 °C
TJ = 150 °C
Single Pulse
0.1
1
10
100
VDS , Drain-to-Source Voltage (V)
Fig 8. Maximum Safe Operating Area
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IRLMS1503
VDS
QG
10V
QGS
VGS
QGD
RD
D.U.T.
RG
+
- VDD
VG
10V
Pulse Width ≤ 1 µs
Duty Factor ≤ 0.1 %
Charge
Fig 9a. Basic Gate Charge Waveform
Fig 10a. Switching Time Test Circuit
Current Regulator
Same Type as D.U.T.
VDS
90%
50KΩ
.2µF
12V
.3µF
D.U.T.
+
V
- DS
10%
VGS
VGS
td(on)
3mA
IG
tr
t d(off)
tf
ID
Current Sampling Resistors
Fig 9b. Gate Charge Test Circuit
Fig 10b. Switching Time Waveforms
Thermal Response (Z thJA )
100
D = 0.50
0.20
10
0.10
0.05
0.02
1
PDM
0.01
t1
SINGLE PULSE
(THERMAL RESPONSE)
t2
Notes:
1. Duty factor D = t 1 / t 2
2. Peak T J = P DM x Z thJA + TA
0.1
0.00001
0.0001
0.001
0.01
0.1
1
10
100
t1 , Rectangular Pulse Duration (sec)
Fig 11. Maximum Effective Transient Thermal Impedance, Junction-to-Ambient
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4
IRLMS1503
Peak Diode Recovery dv/dt Test Circuit
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
+
D.U.T
ƒ
+
‚
-
-
„
+

RG
•
•
•
•
dv/dt controlled by RG
Driver same type as D.U.T.
ISD controlled by Duty Factor "D"
D.U.T. - Device Under Test
Driver Gate Drive
P.W.
Period
D=
+
-
V DD
P.W.
Period
VGS=10V
*
D.U.T. ISD Waveform
Reverse
Recovery
Current
Body Diode Forward
Current
di/dt
D.U.T. VDS Waveform
Diode Recovery
dv/dt
Re-Applied
Voltage
Body Diode
VDD
Forward Drop
Inductor Curent
Ripple ≤ 5%
ISD
* VGS = 5V for Logic Level Devices
Fig 13. For N-channel HEXFET® power MOSFET s
6
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IRLMS1503
Package Outline
Micro6ä
3.00 (.118 )
2.80 (.111 )
1.75 (.068 )
1.50 (.060 )
6
-A-
5
1
2
LEAD ASSIGNMENTS
4
3.00 (.118 )
2.60 (.103 )
3
0.95 ( .0375 )
6X
2X
RECOMMENDED FOOTPRINT
-B2X 0.95 (.0375 )
D
D
S
6
5
4
1
2
3
D
D
G
6X (1.06 (.042 )
2.20 (.087 )
0.50 (.019 )
0.35 (.014 )
6X 0.65 (.025 )
0.15 (.006 ) M C A S B S
O
O
0 -10
1.30 (.051 )
0.90 (.036 )
6X
1.45 (.057 )
0.90 (.036 )
-C-
0.10 (.004 )
6 SURFACES
0.15 (.006 )
MAX.
0.20 (.007 )
0.09 (.004 )
0.60 (.023 )
0.10 (.004 )
NOTES :
1. DIMENSIONING & TOLERANCING PER ANSI Y14.5M-1982.
2. CONTROLLING DIMENSION : MILLIMETER.
3. DIMENSIONS ARE SHOWN IN MILLIMETERS (INCHES).
Part Marking Information
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IRLMS1503
Tape & Reel Information
Micro6ä
8mm
FEED DIRECTION
4mm
NOTES :
1. OUTLINE CONFORMS TO EIA-481 & EIA-541.
178.00
( 7.008 )
MAX.
9.90 ( .390 )
8.40 ( .331 )
NOTES:
1. CONTROLLING DIMENSION : MILLIMETER.
2. OUTLINE CONFORMS TO EIA-481 & EIA-541.
Data and specifications subject to change without notice.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 03/04
8
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