ISSI ® IS61LV12824 128K x 24 HIGH-SPEED CMOS STATIC RAM WITH 3.3V SUPPLY FEATURES • High-speed access time: 8, 9, 10, 12 ns • CMOS low power operation — 756 mW (max.) operating @ 8 ns — 36 mW (max.) standby @ 8 ns • TTL compatible interface levels • Single 3.3V power supply • Fully static operation: no clock or refresh required • Three state outputs • Available in 119-pin Plastic Ball Grid Array (PBGA) and 100-pin TQFP packages. • Industrial temperature available DECEMBER 1999 DESCRIPTION The ISSI IS61LV12824 is a high-speed, static RAM organized as 131,072 words by 24 bits. It is fabricated using ISSI's highperformance CMOS technology. This highly reliable process coupled with innovative circuit design techniques, yields access times as fast as 8 ns with low power consumption. When CE1, CE2 are HIGH and CE2 is LOW (deselected), the device assumes a standby mode at which the power dissipation can be reduced down with CMOS input levels. Easy memory expansion is provided by using Chip Enable and Output Enable inputs, CE1, CE2, CE2 and OE. The active LOW Write Enable (WE) controls both writing and reading of the memory. The IS61LV12824 is packaged in the JEDEC standard 119-pin PBGA and 100-pin TQFP. FUNCTIONAL BLOCK DIAGRAM A0-A16 DECODER 128K x 24 MEMORY ARRAY I/O DATA CIRCUIT COLUMN I/O VCC GND I/O0-I/O23 CE2 CE1 CE2 OE WE CONTROL CIRCUIT ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc. Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 1 ISSI IS61LV12824 PIN CONFIGURATION - 119-pin PBGA 2 ® PIN DESCRIPTIONS 1 2 3 4 5 6 7 A0-A16 Address Inputs A NC A11 A14 A15 A16 A4 NC I/O0-I/O23 Data Inputs/Outputs B NC A12 A13 CE1 A5 A3 NC CE1, CE2 Chip Enable Input LOW C I/O16 NC CE2 NC CE2 NC I/O0 CE2 Chip Enable Input HIGH D I/O17 VCCQ GND GND GND VCCQ I/O1 OE Output Enable Input E I/O18 GND VCC GND VCC GND I/O2 WE Write Enable Input F I/O19 VCCQ GND GND GND VCCQ I/O3 NC No Connection G I/O20 GND VCC GND VCC GND I/O4 Vcc Power H I/O21 VCCQ GND GND GND VCCQ I/O5 VCCQ I/O Power J VCCQ GND VCC GND VCC GND VCCQ GND Ground K I/O22 VCCQ GND GND GND VCCQ I/O6 L I/O23 GND VCC GND VCC GND I/O7 M I/O12 VCCQ GND GND GND VCCQ I/O8 N I/O13 GND VCC GND VCC GND I/O9 P I/O14 VCCQ GND GND GND VCCQ I/O10 R I/O15 NC NC NC NC NC I/O11 T NC A10 A8 WE A0 A1 NC U NC A9 A7 OE A6 A2 NC Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 ISSI IS61LV12824 ® PIN CONFIGURATION 100-Pin TQFP NC NC A11 A12 A13 A14 A15 CE2 Vcc GND CE2 CE1 A16 A5 A4 A3 NC NC NC NC 1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 2 NC Vcc GND I/O0 I/O1 GND VccQ I/O2 I/O3 GND VccQ I/O4 I/O5 Vcc NC NC GND I/O6 I/O7 VccQ GND I/O8 I/O9 VccQ GND I/O10 I/O11 Vcc GND NC 3 4 5 6 7 8 9 NC NC NC NC A10 A9 A8 A7 OE GND Vcc WE A6 A0 A1 A2 NC NC NC NC NC Vcc GND I/O16 I/O17 GND VccQ I/O18 I/O19 GND VccQ I/O20 I/O21 Vcc NC NC GND I/O22 I/O23 VccQ GND I/O12 I/O13 VccQ GND I/O14 I/O15 Vcc GND NC 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 3 ISSI IS61LV12824 ® TRUTH TABLE Mode Not Selected Output Disabled Read Write WE CE1 CE2 CE2 OE I/O0-I/O23 Vcc Current X X X H H L H X X L L L X L X H H H X X H L L L X X X H L X High-Z ISB1, ISB2 High-Z DOUT DIN ICC ICC ICC ABSOLUTE MAXIMUM RATINGS(1) Symbol VCC VTERM TSTG TBIAS PT IOUT Parameter Power Supply Voltage Relative to GND Terminal Voltage with Respect to GND Storage Temperature Temperature Under Bias: Com. Ind. Power Dissipation DC Output Current Value –0.5 to 5.0 –0.5 to Vcc + 0.5 –65 to + 150 –10 to + 85 –45 to + 90 2.0 ±20 Unit V V °C °C °C W mA Note: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. OPERATING RANGE Range Commercial Industrial Ambient Temperature 0°C to +70°C –40°C to +85°C VCC (8, 9 ns) 3.3V + 10%, – 5% 3.3V + 10%, – 5% VCC (10, 12 ns) 3.3V ± 10% 3.3V ± 10% DC ELECTRICAL CHARACTERISTICS (Over Operating Range) Symbol Parameter Test Conditions Min. Max. Unit VOH Output HIGH Voltage VCC = Min., IOH = –4.0 mA 2.4 — V VOL Output LOW Voltage VCC = Min., IOL = 8.0 mA — 0.4 V VIH Input HIGH Voltage 2.2 VCC + 0.3 V –0.3 0.8 V Voltage(1) VIL Input LOW ILI Input Leakage GND ≤ VIN ≤ VCC –1 1 µA ILO Output Leakage GND ≤ VOUT ≤ VCC, Outputs Disabled –1 1 µA Note: 1. VIL (min.) = –0.3V DC; VIL (min.) = –2.0V AC (pulse width ≤ 2.0 ns). VIH (max.) = VCC + 0.3V DC; VIH (max.) = VCC + 2.0V AC (pulse width ≤ 2.0 ns). 4 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 ISSI IS61LV12824 ® POWER SUPPLY CHARACTERISTICS(1) (Over Operating Range) Symbol Parameter Test Conditions -8 ns -9 ns -10 ns -12 ns Min. Max. Min. Max. Min. Max. Min. Max. Unit ICC Vcc Dynamic Operating VCC = Max., Supply Current IOUT = 0 mA, f = fMAX Com. Ind. — — 210 — — — 200 220 — — 180 210 — — 170 190 mA ISB1 TTL Standby Current (TTL Inputs) VCC = Max., VIN = VIH or VIL, f = max. CE1, CE2, ≥ VIH, CE2 ≤ VIL Com. Ind. — — 70 — — — 60 70 — — 50 55 — — 50 55 mA CMOS Standby Current (CMOS Inputs) VCC = Max., Com. CE1, CE2 ≥ VCC – 0.2V, Ind. CE2 ≤ 0.2V, VIN ≥ VCC – 0.2V, or VIN ≤ 0.2V, f = 0 — — 10 — — — 10 20 — — 10 20 — — 10 20 mA ISB2 1 2 3 Note: 1. At f = fMAX, address and data inputs are cycling at the maximum frequency, f = 0 means no input lines change. 4 (1) CAPACITANCE Symbol Parameter CIN Input Capacitance COUT Input/Output Capacitance Conditions Max. Unit VIN = 0V 6 pF VOUT = 0V 8 pF 5 Note: 1. Tested initially and after any design or process changes that may affect these parameters. 6 AC TEST CONDITIONS 7 Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 2 ns 1.5V 8 See Figures 1 and 2 9 AC TEST LOADS 10 319 Ω 3.3V ZO = 50Ω OUTPUT 50Ω 1.5V Figure 1 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 11 OUTPUT 5 pF Including jig and scope 353 Ω 12 Figure 2 5 ISSI IS61LV12824 ® READ CYCLE SWITCHING CHARACTERISTICS(1) (Over Operating Range) -8 Symbol Parameter Min. Max. Min. -9 Max. -10 Min. Max. -12 Min. Max. Unit tRC Read Cycle Time 8 — 9 — 10 — 12 — ns tAA Address Access Time — 8 — 9 — 10 — 12 ns tOHA Output Hold Time 3 — 3 — 3 — 3 — ns tACE tACE2 CE1, CE2 Access Time CE2 Access Time 8 — — 9 — 10 — 12 ns OE Access Time — 4 — 4 — 4 — 4 ns (2) tHZOE OE to High-Z Output 0 3 0 3 0 3 0 3 ns (2) tLZOE OE to Low-Z Output 0 — 0 — 0 — 0 — ns tHZCE(2) CE1, CE2 to High-Z Output tHZCE2(2) CE2 to High-Z Output 0 4 0 5 0 5 0 6 ns tLZCE(2) CE, CE2 to Low-Z Output tLZCE2(2) CE2 to Low-Z Output 3 — 3 — 3 — 3 — ns tDOE Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 6 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 ISSI IS61LV12824 ® AC WAVEFORMS READ CYCLE NO. 1(1,2) (Address Controlled) (CE1 = CE2 = OE = VIL; CE2 = VIH) 1 t RC ADDRESS t AA t OHA DOUT 2 t OHA 3 DATA VALID PREVIOUS DATA VALID READ1.eps 4 READ CYCLE NO. 2(1,3) t RC 5 ADDRESS t AA t OHA 6 OE t HZOE t DOE 7 t LZOE CS1 CS2 t LZCS1 t LZCS2 DOUT 8 t ACS1 t ACS2 HIGH-Z t HZCS1 t HZCS2 9 DATA VALID CS2_RD2.eps Notes: 1. WE is HIGH for a Read Cycle. 2. The device is continuously selected. OE, CE1, CE2 = VIL. CE2 = VIH. 3. Address is valid prior to or coincident with CE1, CE2 LOW and CE2 HIGH transition. 10 11 12 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 7 ISSI IS61LV12824 ® WRITE CYCLE SWITCHING CHARACTERISTICS(1,3) (Over Operating Range) -8 Symbol Parameter Min. Max. Min. Write Cycle Time 8 — 9 CE1, CE2 to Write End CE2 to Write End 7 7 — — tAW Address Setup Time to Write End 7 tHA Address Hold from Write End tSA Address Setup Time -9 Max. -10 -12 Min. Max. Min. Max. — 10 — 12 — ns 8 8 — — 8 8 — — 9 9 — — ns — 8 — 8 — 9 — ns 0 — 0 — 0 — 0 — ns 0 — 0 — 0 — 0 — ns tPWE1 WE Pulse Width (OE = HIGH) 6 — 8 — 8 — 9 — ns tPWE2 WE Pulse Width (OE = LOW) 6 — 9 — 9 — 10 — ns tSD Data Setup to Write End 4.5 — 5 — 5 — 5 — ns tHD Data Hold from Write End 0 — 0 — 0 — 0 — ns tHZWE(2) WE LOW to High-Z Output — 3.5 — 3.5 — 3.5 — 3.5 ns tLZWE(2) WE HIGH to Low-Z Output 3 — 3 — 3 — 3 — ns tWC tSCE tSCE2 Unit Notes: 1. Test conditions assume signal transition times of 2 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V and output loading specified in Figure 1. 2. Tested with the load in Figure 2. Transition is measured ±200 mV from steady-state voltage. Not 100% tested. 3. The internal write time is defined by the overlap of CE1, CE2 LOW, CE2 HIGH and WE LOW. All signals must be in valid states to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the rising or falling edge of the signal that terminates the write. 8 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 ISSI IS61LV12824 ® WRITE CYCLE NO. 1 (CE Controlled, OE = HIGH or LOW) t WC 1 VALID ADDRESS ADDRESS t SCE1 t SCE2 t SA t HA 2 CE1 3 CE2 t AW t PWE1 t PWE2 WE t HZWE DOUT 4 t LZWE HIGH-Z DATA UNDEFINED t SD 5 t HD DATAIN VALID DIN CE2_WR1.eps WRITE CYCLE NO. 2(1) (WE Controlled: OE = HIGH during Write Cycle) 6 7 t WC ADDRESS VALID ADDRESS 8 t HA OE CE1 9 LOW HIGH CE2 10 t AW t PWE1 WE t HZWE t SA DOUT DATA UNDEFINED HIGH-Z t SD DIN 11 t LZWE 12 t HD DATAIN VALID CE2_WR2.eps Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 9 ISSI IS61LV12824 ® WRITE CYCLE NO. 3(1) (WE Controlled: OE I S LOW DURING WRITE CYLE) t WC ADDRESS VALID ADDRESS OE LOW CE1 LOW t HA HIGH CE2 t AW t PWE2 WE t SA DOUT DATA UNDEFINED t HZWE t LZWE HIGH-Z t SD DIN t HD DATAIN VALID CE2_WR3.eps Note: 1. The internal Write time is defined by the overlap of CE1 and CE2 = LOW, CE2 = HIGH and WE = LOW. All signals must be in valid states to initiate a Write, but any can be deasserted to terminate the Write. The Data Input Setup and Hold timing is referenced to the rising or falling edge of the signal that terminates the Write. 10 Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 ISSI IS61LV12824 ® 1 ORDERING INFORMATION Commercial Range: 0°C to +70°C Speed (ns) Order Part No. 8 Package ORDERING INFORMATION Industrial Range: –40°C to +85°C IS61LV12824-8B IS61LV12824-8TQ Plastic Ball Grid Array TQFP 9 IS61LV12824-9B IS61LV12824-9TQ Plastic Ball Grid Array TQFP 9 IS61LV12824-9BI IS61LV12824-9TQI Plastic Ball Grid Array TQFP 10 IS61LV12824-10B IS61LV12824-10TQ Plastic Ball Grid Array TQFP 10 IS61LV12824-10BI IS61LV12824-10TQI Plastic Ball Grid Array TQFP 12 IS61LV12824-12B IS61LV12824-12TQ Plastic Ball Grid Array TQFP 12 IS61LV12824-12BI IS61LV12824-12TQI Plastic Ball Grid Array TQFP Speed (ns) Order Part No. 2 Package 3 4 5 6 7 8 9 ISSI ® Integrated Silicon Solution, Inc. 2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: [email protected] www.issi.com Integrated Silicon Solution, Inc. — 1-800-379-4774 Rev. B 04/17/01 11 10 11 12