INTERSIL ISL95813

Single Phase Core Controller for VR12.6
ISL95813
Features
The ISL95813 single-phase controller provides a fully compliant
VR12.6 power supply solution for Intel™ microprocessors. It
provides a tightly regulated output voltage that is programmed
through a high speed serial bus interface with the CPU. This
interface also allows the CPU to acquire real-time information from
the voltage regulator (VR), which includes load current and VR
temperature.
• Full VR12.6 specification compliance
Based on Intersil's Robust Ripple Regulator (R3™) technology, the
PWM modulator provides faster transient response and settling
time when compared against traditional modulation schemes. Its
variable frequency topology also allows for natural period stretching
discontinuous conduction mode (DCM) for increased efficiency and
power savings in light load situations.
• Digitally selectable switching frequency:
- 425kHz, 550kHz, 700kHz with ECO and PRO options
The ISL95813 has several other key features that include: DCR
current sensing with single NTC thermal compensation; discrete
resistor current sensing; differential remote voltage feedback; and
user-programmable boot voltage, IMAX, TMAX, voltage transition
slew rate, and switching frequency.
• Enable and power-good monitor
• Wide input voltage range: 4.6V to 25V
• R3™ control architecture delivers excellent transient response
and power state mode transitions
• Current monitor (IMON) with temperature compensation
• VRHOT# indicator for CPU protection
• Enhanced light-load efficiency discontinuous conduction mode
operation
• Ultra-small 20 lead 3mmx4mm QFN package
Applications
• Notebook Computers
• Tablets, Ultrabooks™, and AIO
Related Literature
• AN1846 Designer’s Guide to the ISL95813 Evaluation Board
20
VR_ON
2200pF
PGOOD
IMON
470kΩ (NTC) 3.83kΩ NTC
27.4k Ω
PRGM1
1
16
2
15
3
VRHOT#
VIN
{4.6V TO 25V}
17
14
ISL95813
20 Ld 3x4 QFN
4
13
LG
BSC052N03LS
LOUT
PHASE
0.15µH
UG
BOOT
COUT
VR12.6
CPU
14x22µF
CERAMIC
0.22µF
BSC011N03LS
VCC
5
COMP
12
E-PAD
(GND)
6
5.9k Ω
7
FB
6800pF
8
9
11
10
PGRM2
124k Ω
1.82k Ω
3.65k Ω
2.61kΩ
0.056µF
82pF
1µF
ISUMP
499 Ω
18
ISUMN
VTT
19
RTN
113k Ω
SDA
SCLK
ALERT#
205kΩ
11kΩ
549 Ω
10k Ω (NTC)
FIGURE 1. TYPICAL 40Amax, 12.6, APPLICATION DIAGRAM
May 15, 2013
FN8449.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2013. All Rights Reserved
R3 Technologies and Intersil (and design) are trademarks owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
ISL95813
Ordering Information
PART NUMBER
(Notes 1, 2)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(Pb-Free)
PKG.
DWG. #
ISL95813HRZ
813H
-10 to +100
20 LD 3x4 QFN
L20.3x4
ISL95813IRZ
813I
-40 to +100
20 LD 3x4 QFN
L20.3x4
ISL95813EV1Z
Evaluation Board
NOTES:
1. Add “-T” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
2. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil
Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
3. For Moisture Sensitivity Level (MSL), please see device information page for ISL95813. For more information on MSL, please see tech brief TB363.
Pin Configuration
SCLK
ALERT#
SDA
PRGM1
ISL95813
(20 LD 3X4 QFN)
TOP VIEW
20
19
18
17
VR_ON
1
16
LG
PGOOD
2
15
PHASE
IMON
3
14
UG
VRHOT#
4
13
BOOT
NTC
5
12
VCC
COMP
6
11
PRGM2
7
8
9
10
FB
RTN
ISUMN
ISUMP
GND
Pin Descriptions
PIN
NAME
FUNCTION
1
VR_ON
Digital Input
2
PGOOD
Digital Output
Power-Good open-drain output indicating when VR is in regulation with no faults detected. Pull up
externally with a 680Ω resistor to VCCP or 1.9kΩ to 3.3V.
3
IMON
Analog Output:
[Small-signal]
VR output current monitor. IMON pin sources a current proportional to the regulator output current.
A resistor connected from this pin to ground will set a voltage that is proportional to the load
current. This voltage is sampled with an internal ADC to produce a digital IMON signal that can be
read through the serial communications bus.
4
VRHOT#
Digital Output
Open drain thermal overload output indicator. Can be considered part of communication bus with
CPU.
5
NTC
Analog Input:
[Small-Signal]
Thermistor input to VR_HOT# circuit. Used to monitor VR temperature.
6
COMP
Analog Output:
[Small-signal]
Output of the gm error-amplifier for loop control. Connect to ground through the compensation
network.
2
Enable input for controller. Connect to ground to disable the part. Connect to VCC to initiate
soft-start and regulation.
FN8449.0
May 15, 2013
ISL95813
Pin Descriptions (Continued)
PIN
NAME
FUNCTION
7
FB
Analog Input:
[Small-signal]
Output voltage feedback sensing input for regulation. Connect via resistor to VCCSENSE on CPU.
8
RTN
Analog Input:
[Small-signal]
Ground return for differential remote output voltage sensing.Connect via resistor to VCCSENSE on
CPU.
9
ISUMN
Analog Input:
[Small-signal]
VR Loadline, Droop, and DCR sensing input.
10
ISUMP
Analog Input:
[Small-signal]
VR Loadline, Droop, and DCR sensing input.
11
PRGM2
Analog Input:
[Small-signal]
ADC input to program switching frequency and boot voltage using a resistor to ground. See
“PROGRAM 2 Pin” on page 13 for all programming options.
12
VCC
Analog Input:
[Small-signal]
5V IC bias supply input. Bypass to ground with a high-quality 0.1µF ceramic capacitor.
13
BOOT
Analog Input:
[Power]
Floating high-side gate drive voltage supply. Connect to PHASE with a 0.1µF to 0.22µF high-quality
ceramic capacitor.
14
UG
Analog Output:
[Power]
Upper MOSFET gate drive. Connect with a wide trace to the gate of the upper switching MOSFET.
15
PHASE
Analog I/O:
[Power]
Switching node and upper MOSFET gate drive return path. Connect with a wide trace to the source
of the upper switching MOSFET, the drain of the lower switching MOSFET, and the output inductor.
16
LG
Analog Output:
[Power]
Lower MOSFET gate drive. Connect with a wide trace to the gate of the lower switching MOSFET.
17
PRGM1
Analog Input:
[Small-signal]
ADC input to program ICCMAX and FSEL bit using a resistor to ground. See “PROGRAM 1 Pin” on
page 13 for all programming options.
18
SDA
Digital I/O
19
ALERT#
Digital Output
Alert signal for CPU serial interface.
20
SCLK
Digital Input
Clock input for CPU serial interface.
e-pad
GND
Analog Input:
[Power]
Ground reference for IC as well as gate drive power ground return path. Connect to system ground
plane with multiple vias.
3
Data input/output for CPU serial interface.
FN8449.0
May 15, 2013
ISL95813
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +7V
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +28V
Boot Voltage (BOOT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +33V
Boot to Phase Voltage (BOOT-PHASE) . . . . . . . . . . . . . . . . -0.3V to +7V(DC)
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +9V(<10ns)
Phase Voltage (PHASE) . . . . . . . . . . . . . . . . -7V (<20ns Pulse Width, 10µJ)
UGATE Voltage (UGATE) . . . . . . . . . . . . . . . . . . . . PHASE-0.3V (DC) to BOOT
. . . . . . . . . . . . . . . . . . . . . PHASE-5V (<20ns Pulse Width, 10µJ) to BOOT
LGATE Voltage
. . . . . . . . . . . . . . . . . . . . . . . -2.5V (<20ns Pulse Width, 5µJ) to VDD + 0.3V
All Other Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to (VDD + 0.3V)
Open Drain Outputs, PGOOD, VR_HOT#, ALERT#. . . . . . . . . . -0.3V to +7V
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
20 Ld QFN Package (Notes 4, 5) . . . . . . . .
44
6
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Maximum Storage Temperature Range . . . . . . . . . . . . . .-65°C to +150°C
Maximum Junction Temperature (Plastic Package) . . . . . . . . . . . .+150°C
Storage Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Recommended Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V ±5%
Battery Voltage, VIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6V to 25V
Ambient Temperature
HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +100°C
IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +100°C
Junction Temperature
HRZ. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-10°C to +125°C
IRZ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +125°C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
4. θJA is measured in free air with the component mounted on a high effective thermal conductivity test board with “direct attach” features. See Tech
Brief TB379.
5. For θJC, the “case temp” location is the center of the exposed metal pad on the package underside.
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C or -40°C to +100°C, fSW = 700kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
INPUT POWER SUPPLY
+5V Supply Current
IVDD
VR_ON = 1V
3.5
5
mA
1
µA
90
150
µA
4.35
4.5
VR_ON = 0V
PS4 State
POWER-ON-RESET THRESHOLDS
VDD Power-On-Reset Threshold
VDDPORr
VDD rising
VDDPORf
VDD falling
4.00
VID = 1.50V to 2.30V
-0.5
4.15
V
V
SYSTEM AND REFERENCES
System Accuracy
HRZ
%Error (VOUT)
IRZ
%Error (VOUT)
%
VID = 1.00V to 1.49V
-8
+8
mV
VID = 0.50V to 0.99V
-10
+10
mV
VID = 1.50V to 2.30V
-1
+1
%
VID = 1.00V to 1.49V
-15
+15
mV
VID = 0.50V to 0.99V
Internal VBOOT
+0.5
+20
mV
HRTZ (Set by R_PROG2)
1.683
-20
1.7
1.717
V
IRTZ (Set by R_PROG2)
1.675
1.7
1.725
V
Maximum Output Voltage
VOUT(MAX)
VID = [11111111]
2.3
V
Minimum Output Voltage
VOUT(MIN)
VID = [00000001]
0.5
V
4
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ISL95813
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C or -40°C to +100°C, fSW = 700kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
395
425
455
kHz
510
550
590
kHz
CHANNEL FREQUENCY
425kHz Configuration
fSW_425k
550kHz Configuration
fSW_550k
700kHz Configuration
fSW_700k
1000kHz Configuration
fSW_1000k
Set by R_PROG1
650
700
750
kHz
Set by R_PROG1 (PRO PS2/PS3 only)
915
985
1055
kHz
IFB = 0A, HRZ
-0.2
+0.2
mV
IFB = 0A, IRZ
-0.3
+0.3
mV
AMPLIFIERS
Current-Sense Amplifier Input Offset
Error Amp DC Gain (Note 7)
Av0
Error Amp Gain-Bandwidth Product
(Note 7)
GBW
CL = 20pF
VOL
IPGOOD = 4mA
90
dB
18
MHz
POWER-GOOD AND PROTECTION MONITORS
PGOOD Low Voltage
PGOOD Leakage Current
IOH
PGOOD = 3.3V
PGOOD Delay
tpgd
VBOOT = 1.7V
0.15
0.4
1
1.2
V
µA
ms
ALERT# Low Voltage (Note 6)
7
12
Ω
VR_HOT# Low Voltage (Note 6)
7
12
Ω
ALERT# Leakage Current
1
µA
VR_HOT# Leakage Current
1
µA
1.5
Ω
1.5
Ω
1.5
Ω
0.9
Ω
GATE DRIVER
UGATE Pull-Up Resistance (Note 7)
RUGPU
200mA Source Current
1.0
UGATE Source Current (Note 7)
IUGSRC
UGATE - PHASE = 2.5V
2.0
UGATE Sink Resistance (Note 7)
RUGPD
250mA Sink Current
1.0
UGATE Sink Current (Note 7)
IUGSNK
UGATE - PHASE = 2.5V
2.0
LGATE Pull-Up Resistance (Note 7)
RLGPU
250mA Source Current
1.0
LGATE Source Current (Note 7)
ILGSRC
LGATE - GND= 2.5V
2.0
LGATE Sink Resistance (Note 7)
RLGPD
250mA Sink Current
0.5
LGATE Sink Current (Note 7)
ILGSNK
LGATE - GND = 2.5V
4.0
A
UGATE to LGATE Deadtime
tUGFLGR
UGATE falling to LGATE rising, no load
17
ns
LGATE to UGATE Deadtime
tLGFUGR
LGATE falling to UGATE rising, no load
29
ns
22
Ω
VR = 25V
0.2
µA
A
A
A
BOOTSTRAP DIODE
ON-Resistance
RF
Reverse Leakage
IR
PROTECTION
Overvoltage Threshold
OVH
ISUMN rising above setpoint for >1µs
Overcurrent Threshold
240
300
360
mV
56
60
64
µA
0.3
V
LOGIC THRESHOLDS
VR_ON Input Low
VIL
VR_ON Input High
VIH
HRZ
0.7
V
VIH
IRZ
0.75
V
THERMAL MONITOR
NTC Source Current
NTC = 1.3V
58
60
62
µA
VR_HOT# Trip Voltage
Falling
0.881
0.893
0.905
V
VR_HOT# Reset Voltage
Rising
0.924
0.936
0.948
V
5
FN8449.0
May 15, 2013
ISL95813
Electrical Specifications Operating Conditions: VDD = 5V, TA = -10°C to +100°C or -40°C to +100°C, fSW = 700kHz, unless otherwise
noted. Boldface limits apply over the operating temperature range for High Temp Commercial at -10°C to +100°C or Industrial Temp at -40°C to +100°C.
(Continued)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
(Note 6)
TYP
MAX
(Note 6)
UNITS
Therm_Alert Trip Voltage
Falling
0.92
0.932
0.944
V
Therm_Alert Reset Voltage
Rising
0.962
0.974
0.986
V
ISUMN pin current = 40µA
9.7
10
10.3
µA
ISUMN pin current = 20µA
4.8
5
5.2
µA
CURRENT MONITOR
IMON Output Current
IIMON
ICCMAX Alert Trip Voltage
VIMONMAX
ICCMAX Alert Reset Voltage
ISUMN pin current = 4µA
0.875
1
1.125
µA
Rising
1.185
1.2
1.215
V
Falling
1.122
1.14
1.152
V
-1
0
1
µA
3
5
µA
INPUTS
VR_ON Leakage Current
IVR_ON
VR_ON = 0V
VR_ON = 1V
SCLK, SDA Leakage
VR_ON = 0V, SCLK & SDA = 0V & 1V
-1
1
µA
VR_ON = 1V, SCLK & SDA = 1V
-5
1
µA
VR_ON = 1V, SCLK & SDA = 0V, SCLK
-42
µA
VR_ON = 1V, SCLK & SDA = 0V, SDA
-21
µA
SLEW RATE (For VID Change)
Fast Slew Rate
Set by R_PROG2
12
mV/µs
Slow Slew Rate
Default setting Fast Slew divided by 4
3
mV/µs
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits established by characterization and are not production tested.
6
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May 15, 2013
ISL95813
Gate Driver Timing Diagram
PWM
tLGFUGR
tFU
tRU
1V
UGATE
1V
LGATE
tRL
tFL
tUGFLGR
Typical Performance Waveforms (VIN = 19V, 700kHz, PRO)
VID = 1.8V
FIGURE 2. PS0, 1-35A LOAD RELEASE
VID = 1.8V
FIGURE 4. PS0, 1-35A LOAD INSERTION
53mV/µs
10A LOAD
FIGURE 6. PS0, SET VID FAST FROM 1.6V TO 1.8V
7
VID = 1.8V
FIGURE 3. PS0, 1-35A HIGH REP LOAD TRANSIENT
VID = 1.8V
FIGURE 5. PS3 TO PS0, 1-35A TRANSIENT
53mV/µs
10A LOAD
FIGURE 7. PS0, SET VID FAST FROM 1.8V TO 1.6V
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ISL95813
Typical Performance Waveforms (VIN = 19V, 700kHz, PRO)
13.5mV/µs
13.5mV/µs
10A LOAD
FIGURE 8. PS0, SET VID FAST FROM 1.6V TO 1.8V
10A LOAD
FIGURE 9. PS0, SET VID FAST FROM 1.8V TO 1.6V
FIGURE 10. PS4 EXIT TO 1.6V, IO = 1A, SLEWRATE = 53mV/µs
TEMP
MONITOR
NTC
T_MONITOR
VR_HOT#
PRGM1
IMAX
VBOOT
DROOP
PRGM2
PROG
VIN
VR_ON
A/D
IDROOP
VCC
SDA
D/A
DIGITAL
INTERFACE
ALERT#
SCLK
DAC
MODE
BOOT
DRIVER
UGATE
PHASE
COMP
+
RTN
Σ
+
DRIVER
+
_
FB
E/A
LGATE
R3
MODULATOR
IDROOP
ISUMP
+
ISUMN
_
CURRENT
SENSE
IMON
GND
OC FAULT
PGOOD
OV FAULT
FIGURE 11. BLOCK DIAGRAM
8
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ISL95813
Theory of Operation
turns off LGATE when the phase node voltage reaches zero to
prevent the inductor current from reversing direction.
R3™ Modulator
The R3™ Modulator is Intersil’s proprietary synthetic currentmode hysteretic controller and is a blend of fixed frequency PWM
and variable frequency hysteretic control technology. This
modulator topology offers high noise immunity and a rapid
transient response to dynamic load scenarios. Under static
conditions the desired switching frequency is maintained within
the entire specified range of input voltages, output voltages, and
load currents. During load transients the controller will increase
or decrease the PWM pulses and switching frequency to
maintain output voltage regulation. Figure 12 illustrates this
effect during a load insertion. As the window voltage starts to
climb from a load step the time between PWM pulses decreases
as fSW increases to keep the output within regulation.
WINDOW VOLTAGE VW
(WRT VCOMP)
SYNTHETIC CURRENT SIGNAL
If the load current reaches the critical conduction point the
inductor current will reach and stay at zero before the next phase
node pulse and the regulator is in discontinuous conduction
mode (DCM). Should the load current rise above the critical
conduction point, the inductor current will not cross 0A in a
switching cycle, and the regulator is in CCM although the
controller is in DE mode.Equation 1 below gives the formula for
critical conduction, where Icritical is the load current for critical
conduction and ΔIL is the ripple on the inductor current.
ΔI L
I critical = -------2
(EQ. 1)
Figure 14 shows the operation principle in diode emulation mode
at light load. The load gets incrementally lighter in the three cases
from top to bottom. The PWM on-time is determined by the VW
window size, therefore is the same, making the peak inductor
current the same in the three cases. The controller clamps the
synthetic current DE mode to make it mimic the inductor current. It
takes the synthesized current longer to hit the lower window
voltage, naturally stretching the switching period. The inductor
current triangles move further apart from each other such that the
inductor current average value is equal to the load current. By
reducing the switching frequency in DE mode switching losses are
decreased and light load efficiency is improved.
ERROR AMPLIFIER
VOLTAGE VCOMP
CCM/DCM BOUNDARY
VW
SYNTHETIC
CURRENT
PWM
IL
FIGURE 12. MODULATOR WAVEFORMS DURING LOAD TRANSIENT
VW
LIGHT DCM
SYNTHETIC
CURRENT
Diode Emulation and Period Stretching
IL
PHASE
VOUT
DEEP DCM
VOUT
VW
SYNTHETIC
CURRENT
UGATE
IL
LG ATE
FIGURE 14. PERIOD STRETCHING
IL
ECO and PRO Mode DCM
FIGURE 13. DIODE EMULATION
The ISL95813 can operate in diode emulation (DE) mode to
improve light load efficiency. In DE mode, the low-side MOSFET
conducts only when the current is flowing from source to drain and
does not allow reverse current, emulating a diode like a standard
buck regulator. As Figure 13 shows, when LGATE is on, the low-side
MOSFET conducts, creating negative voltage on the phase node
due to the voltage drop across the ON-resistance. The controller
monitors the current through monitoring the phase node voltage. It
9
The ISL95813 has the ability to set both ECO and PRO mode DCM
options for 700kHz switching applications. In ECO mode the time
from Upper Gate On to Lower Gate Off is set to 1/700kHz or
1.43µs. When PRO mode is selected the UG On to LG Off time is
reduced to 1/1MHz or 1.0µs. For applications where efficiency is
important ECO mode should be implemented as the longer
switching times reduce the amount of switching loss in the FETs.
PRO mode is ideal for applications that require lower DCM ripple
as the shorter gate times reduce the amount of output ripple.
Because of the reduced ripple in PRO mode the amount of output
FN8449.0
May 15, 2013
ISL95813
capacitance can be reduced, saving both board space and BOM
costs.
See “PROGRAM 1 RESISTOR VALUES” on page 13 for the
ECO/PRO programming resistor options.
TABLE 1. VID TABLE (Continued)
VID
VO (V)
Hex
7
6
5
4
3
2
1
0
0
0
0
0
1
1
0
1
0
D
0.62000
0
0
0
0
1
1
1
0
0
E
0.63000
0
0
0
0
1
1
1
1
0
F
0.64000
0
0
0
1
0
0
0
0
1
0
0.65000
0
0
0
1
0
0
0
1
1
1
0.66000
0
0
0
1
0
0
1
0
1
2
0.67000
0
0
0
1
0
0
1
1
1
3
0.68000
0
0
0
1
0
1
0
0
1
4
0.69000
0
0
0
1
0
1
0
1
1
5
0.70000
0
0
0
1
0
1
1
0
1
6
0.71000
0
0
0
1
0
1
1
1
1
7
0.72000
0
0
0
1
1
0
0
0
1
8
0.73000
0
0
0
1
1
0
0
1
1
9
0.74000
0
0
0
1
1
0
1
0
1
A
0.75000
0
0
0
1
1
0
1
1
1
B
0.76000
0
0
0
1
1
1
0
0
1
C
0.77000
Voltage Regulation and Load Line
Implementation
0
0
0
1
1
1
0
1
1
D
0.78000
0
0
0
1
1
1
1
0
1
E
0.79000
After the start-up sequence, the controller regulates the output
voltage to the value set by the VID information in Table 1. The
controller will control the no-load output voltage to an accuracy of
±0.5% over the VID voltage range. A differential amplifier allows
voltage sensing for precise voltage regulation at the
microprocessor die. Current silicon maximum VID is set as 2.3V,
and any VID command above 2.3V will be rejected.
0
0
0
1
1
1
1
1
1
F
0.80000
0
0
1
0
0
0
0
0
2
0
0.81000
0
0
1
0
0
0
0
1
2
1
0.82000
0
0
1
0
0
0
1
0
2
2
0.83000
0
0
1
0
0
0
1
1
2
3
0.84000
TABLE 1. VID TABLE
Start-up Timing
With the controller's VDD voltage above the POR threshold, the
start-up sequence begins when VR_ON exceeds the logic high
threshold. Figure 15 shows the typical start-up timing. The
controller uses digital soft-start to ramp-up DAC to the voltage
programmed by the SetVID command. PGOOD is asserted high
and ALERT# is asserted low at the end of the ramp up. Similar
results occur if VR_ON is tied to VDD, with the soft-start sequence
starting 1.1ms after VDD crosses the POR threshold.
VDD
SLEW RATE
VR_ON
DVID-SLOW
VID
COMMAND
VOLTAGE
V BOOT
1.1ms
DAC
PGOOD
…...
ALERT#
FIGURE 15. SOFT-START WAVEFORMS
VID
Hex
VR12.6
0
0
1
0
0
1
0
0
2
4
0.85000
VO (V)
0
0
1
0
0
1
0
1
2
5
0.86000
VR12.6
7
6
5
4
3
2
1
0
0
0
1
0
0
1
1
0
2
6
0.87000
0
0
0
0
0
0
0
0
0
0
0.00000
0
0
1
0
0
1
1
1
2
7
0.88000
0
0
0
0
0
0
0
1
0
1
0.50000
0
0
1
0
1
0
0
0
2
8
0.89000
0
0
0
0
0
0
1
0
0
2
0.51000
0
0
1
0
1
0
0
1
2
9
0.90000
0
0
0
0
0
0
1
1
0
3
0.52000
0
0
1
0
1
0
1
0
2
A
0.91000
0
0
0
0
0
1
0
0
0
4
0.53000
0
0
1
0
1
0
1
1
2
B
0.92000
0
0
0
0
0
1
0
1
0
5
0.54000
0
0
1
0
1
1
0
0
2
C
0.93000
0
0
0
0
0
1
1
0
0
6
0.55000
0
0
1
0
1
1
0
1
2
D
0.94000
0
0
0
0
0
1
1
1
0
7
0.56000
0
0
1
0
1
1
1
0
2
E
0.95000
0
0
0
0
1
0
0
0
0
8
0.57000
0
0
1
0
1
1
1
1
2
F
0.96000
0
0
0
0
1
0
0
1
0
9
0.58000
0
0
1
1
0
0
0
0
3
0
0.97000
0
0
0
0
1
0
1
0
0
A
0.59000
0
0
1
1
0
0
0
1
3
1
0.98000
0
0
0
0
1
0
1
1
0
B
0.60000
0
0
1
1
0
0
1
0
3
2
0.99000
0
0
0
0
1
1
0
0
0
C
0.61000
0
0
1
1
0
0
1
1
3
3
1.00000
10
FN8449.0
May 15, 2013
ISL95813
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID
VO (V)
Hex
7
6
5
4
3
2
1
0
0
0
1
1
0
1
0
0
3
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
0
0
1
1
0
1
0
0
1
1
1
0
0
1
1
0
0
1
0
0
0
VID
VO (V)
Hex
VR12.6
7
6
5
4
3
2
1
0
4
1.01000
0
1
0
1
1
0
1
1
5
B
1.40000
3
5
1.02000
0
1
0
1
1
1
0
0
5
C
1.41000
0
3
6
1.03000
0
1
0
1
1
1
0
1
5
D
1.42000
1
1
3
7
1.04000
0
1
0
1
1
1
1
0
5
E
1.43000
0
0
0
3
8
1.05000
0
1
0
1
1
1
1
1
5
F
1.44000
1
0
0
1
3
9
1.06000
0
1
1
0
0
0
0
0
6
0
1.45000
1
1
0
1
0
3
A
1.07000
0
1
1
0
0
0
0
1
6
1
1.46000
1
1
1
0
1
1
3
B
1.08000
0
1
1
0
0
0
1
0
6
2
1.47000
0
1
1
1
1
0
0
3
C
1.09000
0
1
1
0
0
0
1
1
6
3
1.48000
0
0
1
1
1
1
0
1
3
D
1.10000
0
1
1
0
0
1
0
0
6
4
1.49000
0
0
1
1
1
1
1
0
3
E
1.11000
0
1
1
0
0
1
0
1
6
5
1.50000
0
0
1
1
1
1
1
1
3
F
1.12000
0
1
1
0
0
1
1
0
6
6
1.51000
0
1
0
0
0
0
0
0
4
0
1.13000
0
1
1
0
0
1
1
1
6
7
1.52000
0
1
0
0
0
0
0
1
4
1
1.14000
0
1
1
0
1
0
0
0
6
8
1.53000
0
1
0
0
0
0
1
0
4
2
1.15000
0
1
1
0
1
0
0
1
6
9
1.54000
0
1
0
0
0
0
1
1
4
3
1.16000
0
1
1
0
1
0
1
0
6
A
1.55000
0
1
0
0
0
1
0
0
4
4
1.17000
0
1
1
0
1
0
1
1
6
B
1.56000
0
1
0
0
0
1
0
1
4
5
1.18000
0
1
1
0
1
1
0
0
6
C
1.57000
0
1
0
0
0
1
1
0
4
6
1.19000
0
1
1
0
1
1
0
1
6
D
1.58000
0
1
0
0
0
1
1
1
4
7
1.20000
0
1
1
0
1
1
1
0
6
E
1.59000
0
1
0
0
1
0
0
0
4
8
1.21000
0
1
1
0
1
1
1
1
6
F
1.60000
0
1
0
0
1
0
0
1
4
9
1.22000
0
1
1
1
0
0
0
0
7
0
1.61000
0
1
0
0
1
0
1
0
4
A
1.23000
0
1
1
1
0
0
0
1
7
1
1.62000
0
1
0
0
1
0
1
1
4
B
1.24000
0
1
1
1
0
0
1
0
7
2
1.63000
0
1
0
0
1
1
0
0
4
C
1.25000
0
1
1
1
0
0
1
1
7
3
1.64000
0
1
0
0
1
1
0
1
4
D
1.26000
0
1
1
1
0
1
0
0
7
4
1.65000
0
1
0
0
1
1
1
0
4
E
1.27000
0
1
1
1
0
1
0
1
7
5
1.66000
0
1
0
0
1
1
1
1
4
F
1.28000
0
1
1
1
0
1
1
0
7
6
1.67000
0
1
0
1
0
0
0
0
5
0
1.29000
0
1
1
1
0
1
1
1
7
7
1.68000
0
1
0
1
0
0
0
1
5
1
1.30000
0
1
1
1
1
0
0
0
7
8
1.69000
0
1
0
1
0
0
1
0
5
2
1.31000
0
1
1
1
1
0
0
1
7
9
1.70000
0
1
0
1
0
0
1
1
5
3
1.32000
0
1
1
1
1
0
1
0
7
A
1.71000
0
1
0
1
0
1
0
0
5
4
1.33000
0
1
1
1
1
0
1
1
7
B
1.72000
0
1
0
1
0
1
0
1
5
5
1.34000
0
1
1
1
1
1
0
0
7
C
1.73000
0
1
0
1
0
1
1
0
5
6
1.35000
0
1
1
1
1
1
0
1
7
D
1.74000
0
1
0
1
0
1
1
1
5
7
1.36000
0
1
1
1
1
1
1
0
7
E
1.75000
0
1
0
1
1
0
0
0
5
8
1.37000
0
1
1
1
1
1
1
1
7
F
1.76000
0
1
0
1
1
0
0
1
5
9
1.38000
1
0
0
0
0
0
0
0
8
0
1.77000
0
1
0
1
1
0
1
0
5
A
1.39000
1
0
0
0
0
0
0
1
8
1
1.78000
11
VR12.6
FN8449.0
May 15, 2013
ISL95813
TABLE 1. VID TABLE (Continued)
TABLE 1. VID TABLE (Continued)
VID
VO (V)
Hex
7
6
5
4
3
2
1
0
1
0
0
0
0
0
1
0
8
1
0
0
0
0
0
1
1
1
0
0
0
0
1
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
1
0
0
1
0
1
VID
VO (V)
Hex
VR12.6
7
6
5
4
3
2
1
0
2
1.79000
1
0
1
0
1
0
0
1
A
9
2.18000
8
3
1.80000
1
0
1
0
1
0
1
0
A
A
2.19000
0
8
4
1.81000
1
0
1
0
1
0
1
1
A
B
2.20000
0
1
8
5
1.82000
1
0
1
0
1
1
0
0
A
C
2.21000
1
1
0
8
6
1.83000
1
0
1
0
1
1
0
1
A
D
2.22000
0
1
1
1
8
7
1.84000
1
0
1
0
1
1
1
0
A
E
2.23000
0
1
0
0
0
8
8
1.85000
1
0
1
0
1
1
1
1
A
F
2.24000
0
0
1
0
0
1
8
9
1.86000
1
0
1
1
0
0
0
0
B
0
2.25000
0
0
0
1
0
1
0
8
A
1.87000
1
0
1
1
0
0
0
1
B
1
2.26000
1
0
0
0
1
0
1
1
8
B
1.88000
1
0
1
1
0
0
1
0
B
2
2.27000
1
0
0
0
1
1
0
0
8
C
1.89000
1
0
1
1
0
0
1
1
B
3
2.28000
1
0
0
0
1
1
0
1
8
D
1.90000
1
0
1
1
0
1
0
0
B
4
2.29000
1
0
0
0
1
1
1
0
8
E
1.91000
1
0
1
1
0
1
0
1
B
5
2.30000
1
0
0
0
1
1
1
1
8
F
1.92000
1
0
0
1
0
0
0
0
9
0
1.93000
1
0
0
1
0
0
0
1
9
1
1.94000
Rdroop
1
0
0
1
0
0
1
0
9
2
1.95000
Vdroop
1
0
0
1
0
0
1
1
9
3
1.96000
1
0
0
1
0
1
0
0
9
4
1.97000
1
0
0
1
0
1
0
1
9
5
1.98000
1
0
0
1
0
1
1
0
9
6
1.99000
1
0
0
1
0
1
1
1
9
7
2.00000
1
0
0
1
1
0
0
0
9
8
2.01000
1
0
0
1
1
0
0
1
9
9
2.02000
1
0
0
1
1
0
1
0
9
A
2.03000
1
0
0
1
1
0
1
1
9
B
2.04000
1
0
0
1
1
1
0
0
9
C
2.05000
1
0
0
1
1
1
0
1
9
D
2.06000
1
0
0
1
1
1
1
0
9
E
2.07000
1
0
0
1
1
1
1
1
9
F
2.08000
1
0
1
0
0
0
0
0
A
0
2.09000
1
0
1
0
0
0
0
1
A
1
2.10000
1
0
1
0
0
0
1
0
A
2
2.11000
1
0
1
0
0
0
1
1
A
3
2.12000
1
0
1
0
0
1
0
0
A
4
2.13000
1
0
1
0
0
1
0
1
A
5
2.14000
1
0
1
0
0
1
1
0
A
6
2.15000
1
0
1
0
0
1
1
1
A
7
2.16000
1
0
1
0
1
0
0
0
A
8
2.17000
12
VR12.6
VCCSENSE
FB
VR LOCAL
CATCH
VO
RESISTOR
Idroop
COMP
E/A
Σ VDAC DAC
VIDs
VID
RTN
VSSSENSE
INTERNAL
TO IC
X1
GND
CATCH
RESISTOR
FIGURE 16. DIFFERENTIAL SENSING AND LOAD LINE
IMPLEMENTATION
As the load current increases from zero, the output voltage will
droop from the VID table value by an amount proportional to the
load current to achieve the load line. The controller can sense the
inductor current through the intrinsic DC Resistance (DCR) of the
inductors as shown in the Typical Applications Diagram or through a
current sense resistor in series with the inductor (Figure 24). In both
methods, the capacitor Cn voltage represents the inductor total
current. A droop amplifier converts Cn voltage into an internal
current source with the gain set by resistor Ri. The current source is
used for load line implementation, current monitor and overcurrent
protection.
V Cn
I droop = ----------Ri
(EQ. 2)
When using inductor DCR current sensing, a single NTC element
is used to compensate the positive temperature coefficient of the
copper winding thus sustaining the load line accuracy with
reduced cost.
FN8449.0
May 15, 2013
ISL95813
Idroop flows through resistor Rdroop and creates a voltage drop as
shown in Equation 3.
V droop = R droop × I droop
(EQ. 3)
Vdroop is the droop voltage required to implement load line.
Changing Rdroop or scaling Idroop can both change the load line
slope. Since Idroop also sets the overcurrent protection level, it is
recommended to first scale Idroop based on OCP requirement,
then select an appropriate Rdroop value to obtain the desired
load line slope.
Differential Voltage Sensing
Figure 16 also shows the differential voltage sensing scheme.
VCCSENSE and VSSSENSE are the remote voltage sensing signals
from the processor die. A unity gain differential amplifier senses
the VSSSENSE voltage and add it to the DAC output. The error
amplifier regulates the inverting and the non-inverting input
voltages to be equal as shown in Equation 4:
VCC SENSE + V
droop
= V DAC + VSS SENSE
(EQ. 4)
Rewriting Equation 4 and substitution of Equation 3 gives
VCC SENSE – VSS SENSE = V DAC – R droop × I droop
(EQ. 5)
Equation 5 is the exact equation required for load line
implementation.
The VCCSENSE and VSSSENSE signals come from the processor die.
The feedback will be open circuit in the absence of the processor. As
Figure 16 shows, it is recommended to add a “catch” resistor to feed
the VR local output voltage back to the compensator, and add
another “catch” resistor to connect the VR local output ground to the
RTN pin. These resistors, typically 10Ω~100Ω, will provide voltage
feedback if the system is powered up without a processor installed.
CCM Switching Frequency
The PROG2 pin configures the CCM switching frequency. When
the ISL95813 is in continuous conduction mode (CCM), the
switching frequency is not absolutely constant due to the nature
of the R3™ modulator. Section “R3™ Modulator” on page 9
explains that the effective switching frequency will increase
during load insertion and will decrease during load release to
achieve fast response. On the other hand, the switching
frequency is relatively constant at steady state. Variation is
expected when the power stage condition, such as input voltage,
output voltage, load, etc. changes. The variation is usually less
than 15% and doesn’t have any significant effect on output
voltage ripple magnitude.
PROGRAM 1 Pin
PRGM1 programs ICCMAX register and switching frequency. For
proper operation, it is recommended the 1% resistor value called
out in the table be used in the final application.
TABLE 2. PROGRAM 1 RESISTOR VALUES
R_PROG1
(±3%, kΩ)
ICCMAX
(A)
1.0
17
5.76
21
9.31
28
13.3
33
17.4
35
21
40
24.9
17
28.7
21
33
28
42.2
33
49.9
35
57.6
40
64.9
17
73.2
21
80.6
28
90.9
33
102
35
113
40
124
17
137
21
154
28
169
33
187
35
205
40
fSW
(kHz)
425
550
700 ECO
700 PRO
PROGRAM 2 Pin
PRGM2 pin programs the both boot up voltage VBOOT, and the
VID Slew Rate. For proper operation, it is recommended the 1%
resistor value called out in the table be used in the final
application.
TABLE 3. PROGRAM 2 RESISTOR VALUES
13
R_PROG2 (±3%, kΩ)
VBOOT (V)
1.0
0
5.76
1.65
9.31
1.7
13.3
1.75
VID Slew
(mV/µs)
12
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TABLE 3. PROGRAM 2 RESISTOR VALUES (Continued)
R_PROG2 (±3%, kΩ)
VBOOT (V)
17.4
1.75
21
1.7
24.9
1.65
28.7
0
33
0
42.2
1.65
49.9
1.7
57.6
1.75
64.9
1.75
73.2
1.7
80.6
1.65
90.9
0
102
0
113
1.65
124
1.7
137
1.75
154
1.75
169
1.7
187
1.65
205
0
VID Slew
(mV/µs)
24
40
SetVID_fast command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a
minimum 12mV/µs slew rate or the fast slew rate set by
R_PROG2.
SetVID_slow command prompts the controller to enter CCM and
to actively drive the output voltage to the new VID value at a
minimum 3mV/µs slew rate.
SetVID_decay command prompts the controller to enter DE
mode. The output voltage, Vcore, will decay down to the new VID
value at a slew rate determined by the load as shown in
Equation 6.
I out
dV core
------------------- = ----------dt
C out
45
(EQ. 6)
Overvoltage protection is blanked during VID down transition in
DE mode until the output voltage is within 60mV of the VID value.
If the voltage decay rate is too fast, the controller will limit the
voltage slew rate at SetVID_slow slew rate.
ALERT# will be asserted low at the end of SetVID_fast and
SetVID_slow VID transitions.
S e t V ID _ d e c a y
53
S e t V ID _ f a s t/s lo w
Vo
V ID
80
t3
t1
t _ a le r t
t2
ALERT#
Power State Modes
FIGURE 17. SETVID DECAY PRE-EMPTIVE BEHAVIOR
Table 4 shows the power state operation mode.
TABLE 4. POWER STATE OPERATION MODE
POWER STATE
CONFIGURATION
PS0
1-phase CCM
PS1
1-phase CCM
PS2
1-phase DE
PS3
1-phase DE
PS4
Very low power state
For PS0 and PS1, the ISL95813 operates in CCM while in PS2
and PS3 the device enters DCM.
In PS4, ISL95813 enters a very low power state and shuts down
all the drivers and internal circuits. In this mode the controller
only accepts SetVID-fast and SetVID-slow commands, all other
SVID commands will be rejected. ISL95813 quiescent power is
about 0.5mW in PS4.
Dynamic Operation
The ISL95813 responds to VID changes by slewing to the new
voltage at a slew rate indicated in the SetVID command. There
are three SetVID slew rates, namely SetVID_fast, SetVID_slow
and SetVID_decay.
14
Figure 17 shows SetVID Decay Pre-Emptive behavior. The
controller receives a SetVID_decay command at t1. The VR
enters DE mode and the output voltage Vo decays down slowly.
At t2, before Vo reaches the intended VID target of the
SetVID_decay command, the controller receives a SetVID_fast (or
SetVID_slow) command to go to a voltage higher than the actual
Vo. The controller will react immediately and slew Vo to the new
target voltage at the slew rate specified by the SetVID command.
At t3, Vo reaches the new target voltage and the controller
asserts the ALERT# signal.
The R3™ modulator intrinsically has voltage feed-forward. The
output voltage is insensitive to a fast slew rate input voltage
change.
Current Monitor
The controller provides the current monitor function. IMON pin
reports the inductor current.
The IMON pin outputs a high-speed analog current source that is
1/4 of the droop current flowing out of the FB pin. Thus
becoming Equation 7:
I IMON = 0.25 × I droop
(EQ. 7)
As the Typical Applications Diagram shows in Figure 1, a resistor
Rimon is connected to the IMON pin to convert the IMON pin
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ISL95813
current to voltage. A capacitor should be paralleled with Rimon to
filter the voltage information. This voltage is sampled with an
internal ADC to produce a digital IMON signal that can be read
through the serial communications bus.
All the above fault conditions can be reset by toggling VR_ON low.
When VR_ON is brought back to its high operating levels a
soft-start will occur.
Table 5 summarizes the fault protections.
The IMON pin voltage range is 0V to 1.2V. The controller monitors
the IMON pin voltage and considers that ISL95813 has reached
ICCMAX when IMON pin voltage is 1.2V.
Adaptive Body Diode Conduction Time
Reduction
In DCM, the controller turns off the low-side MOSFET when the
inductor current approaches zero. During on-time of the low-side
MOSFET, the phase node sits at a negative voltage equal to the
MOSFET rDSON voltage drop. A phase comparator inside the
controller monitors the phase voltage during the on-time of the
low-side MOSFET and compares it against a threshold to
determine the zero-crossing point of the inductor current. Should
the inductor current not reach zero when the lower FET turns off,
it will then flow through the low-side MOSFET body diode,
decreasing the voltage on the phase node until the inductor
current completely decays to zero. When the inductor current
finally reaches 0A phase is considered to be in tri-state mode and
its voltage floats to the set VOUT value.
If the inductor current has crossed zero and reversed the
direction when the low-side MOSFET turns off, current will then
flow through the high-side MOSFET body diode, causing a voltage
spike on phase which will decay to the set VOUT voltage as phase
tri-states.
TABLE 5. FAULT PROTECTION SUMMARY
FAULT TYPE
FAULT DURATION
BEFORE
PROTECTION
PROTECTION ACTION
Overcurrent
120µs
Overvoltage
+300mV
Immediately
PWM tri-state,
PGOOD latched low
PGOOD latched low.
Actively pulls the
output voltage to
below VID value, then
tri-state.
FAULT
RESET
VR_ON
toggle or
VDD toggle
Supported Data And Configuration Registers
The controller supports the following data and configuration
registers.
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS
INDEX
REGISTER
NAME
DESCRIPTION
DEFAULT
VALUE
00h
Vendor ID
Uniquely identifies the VR vendor.
Assigned by Intel.
12h
01h
Product ID
Uniquely identifies the VR product.
Intersil assigns this number.
0Ch
02h
Product
Revision
Uniquely identifies the revision of the VR 04h
control IC. Intersil assigns this data.
05h
Protocol ID
Identifies what revision of SVID protocol 03h
the controller supports.
06h
Capability
The ISL95813 provides the designer with overcurrent, overvoltage,
and over-temperature protection.
Identifies the SVID VR capabilities and 81h
which of the optional telemetry registers
are supported.
10h
Status_1
The controller determines overcurrent protection (OCP) by
comparing the average value of the droop current Idroop with an
internal current source threshold as Table 5 shows. It declares OCP
when Idroop is above the threshold for 120µs.
Data register read after ALERT# signal. 00h
Indicating if a VR rail has settled, has
reached VR_HOT# condition or has
reached ICCMAX.
11h
Status_2
Data register showing Status_2
communication.
12h
Temperature Data register showing temperature
Zone
zones that have been entered.
00h
1Ch
Status_2_
LastRead
This register contains a copy of the
Status_2 data that was last read with
the GetReg (Status_2) command.
00h
21h
ICCMAX
Data register containing the ICCMAX the Set by
R_PROG1
platform supports, set at start-up by
resistors R_PROG1. The platform design
engineer programs this value during the
design process. Binary format in amps,
i.e., 100A = 64h
24h
SR-fast
Slew Rate Normal. The fastest slew rate Set by
R_PROG2
the platform VR can sustain. Binary
format in mV/µs. i.e., 0Ch = 12mV/µs.
The controller continues monitoring the phase voltage after turning
off the low-side MOSFET and adjusts the phase comparator
threshold voltage accordingly in iterative steps such that the lowside MOSFET body diode conducts for approximately 30ns to
minimize the body diode-related loss.
Protection
For over temperature and overcurrent faults, the controller takes
the same actions: de-assertion of PGOOD and turn-off of all the
high-side and low-side power MOSFETs. Any residual inductor
current will decay through the MOSFET body diodes or load.
The controller will declare an overvoltage fault and de-assert PGOOD
if the output voltage exceeds the VID set value by +300mV. The
controller will immediately declare an OV fault, toggle PGOOD to
ground. The low-side power MOSFET remains on until the output
voltage is pulled down below the VID set value before being shut
off, and placing phase into tri-state. If the output voltage rises
above the VID set value +300mV again, the protection process is
repeated. This behavior provides the maximum amount of
protection against shorted high-side power MOSFETs while
preventing output ringing below ground.
15
00h
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Key Component Selection
TABLE 6. SUPPORTED DATA AND CONFIGURATION
REGISTERS (Continued)
INDEX
25h
26h
REGISTER
NAME
SR-slow
VBOOT
DESCRIPTION
DEFAULT
VALUE
Default is 4x slower than normal. Binary Set by
R_PROG2
format in mV/us. i.e., 03h = 3mV/µs.
and
Can be configured by register 2Ah.
Register
2Ah
If programmed by the platform, the VR Set by
supports VBOOT voltage during start-up R_PROG2
ramp. The VR will ramp to VBOOT and
hold at VBOOT until it receives a new
SetVID command to move to a different
voltage.
Slow slew
01h = 1/2 of fast slew rate
rate selector 02h = 1/4 of fast slew rate
04h = 1/8 of fast slew rate
08h = 1/16 of fast slew rate
02h
2Bh
PS4 exit
latency
76h
2Ch
PS3 exit
latency
2Ah
Report 48µs
31h
32h
33h
VOUT max
This register is programmed by the
master and sets the maximum VID the
VR will support. If a higher VID code is
received, the VR will respond with “not
supported” acknowledge.
B5h
VID Setting
Data register containing currently
programmed VID voltage. VID data
format.
00h
Voltage
Offset
Rsum
ISUMP
L
Rntcs
Rp
Cn
Vcn
Rntc
Ri
C2h
Power State Register containing the current
programmed power state.
Phase
DCR
38h
2Dh Enable to
VR_Ready
latency
30h
Inductor DCR Current-Sensing Network
ISUMN
Io
FIGURE 18. DCR CURRENT-SENSING NETWORK
Figure 18 shows the inductor DCR current-sensing network for a
single phase solution. This loop monitors the voltage drop across
the DCR creating by current flowing in the inductor and feeds that
information to the ISL95813 for IMON and load line purposes.
The summed inductor current information is presented to the
capacitor Cn. Equations 8 thru 12 describe the frequency-domain
relationship between inductor total current Io(s) and Cn
voltageVCn(s):
00h
Sets offset in VID steps added to the VID 00h
setting for voltage margining. Bit 7 is a
sign bit, 0 = positive margin,
1 = negative margin. Remaining 7 bits
are # VID steps for the margin.
00h = no margin,
01h = +1 VID step
02h = +2 VID steps...
34h
Multi VR
Config
Data register that configures multiple
VRs behavior on the same SVID bus.
00h
35h
SetRegADR
Serial data bus communication address 00h
R ntcnet
⎛
⎞
V Cn ( s ) = ⎜ ------------------------------------------ × DCR⎟ × I o ( s ) × A cs ( s )
⎝ R ntcnet + R sum
⎠
(EQ. 8)
( R ntcs + R ntc ) × R p
R ntcnet = ---------------------------------------------------R ntcs + R ntc + R p
(EQ. 9)
s
1 + ------ωL
A cs ( s ) = ----------------------s
1 + ------------ω sns
(EQ. 10)
DCR
ω L = ------------L
(EQ. 11)
1
ω sns = -------------------------------------------------------R ntcnet × R sum
------------------------------------------ × C n
R ntcnet + R sum
(EQ. 12)
In the DCR network, transfer function Ac(s) has unity gain at DC. As
winding temperature increases, the DCR of the inductor increases
which causes a higher reading of the DC current flowing through the
inductor. To compensate for this effect, the resistance of the NTC
Rntc decreases as its temperature increases. Choosing the
remaining components of the DCR network correctly ensures that
the capacitor voltage Vcn accurately represents the total DC current
through the inductor over the entire operating temperature range.
It is recommended when designing the DCR network to maintain
Vcn as the highest feasible fraction of the voltage that is dropped
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ISL95813
across the inductor’s DCR in order to ensure the droop circuitry on
chip has a high signal level to operate with.
While final component values should be fine tuned for a given
application, a good starting point for the DCR temperature
compensation network is as follows: Rsum = 3.65kΩ, Rp = 11kΩ,
Rntcs = 2.61kΩ, and Rntc = 10kΩ (ERT-J1VR103J). To check the
operation of the compensation network apply the full load DC
current and record the output voltage both immediately and once
the circuit has reached its thermal equilibrium. A well designed
NTC network can limit the amount of drift on the output voltage
to within 2 mV.
io
Vo
FIGURE 20. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO SMALL
In order to achieve proper transient response it is also crucial that
VCn(s) represents real-time Io(s) of the controller. This is done by
matching the pole and zero present in Acs(s) to one another which
sets the transfer function to unity gain for all frequencies. To ensure
unity gain force ωL equal to ωsns and solve for Cn as seen in
Equation 13.
L
C n = --------------------------------------------------------------R ntcnet × R sum
------------------------------------------ × DCR
R ntcnet + R sum
io
(EQ. 13)
Vo
For example, with Rsum = 3.65kΩ, Rp = 11kΩ, Rntcs = 2.61kΩ,
Rntc = 10kΩ, DCR = 1mΩ, and L = 0.2µH, Equation 13 gives
Cn = 0.088µF.
With proper compensator design, Figure 19 shows the expected
load transient response waveforms. When the load current io has a
square change, the output voltage Vo also has a square response.
If Cn value is too large or too small, VCn(s) will not accurately
represent real-time io(s) and the transient response of the controller
will degrade. When Cn is too small, Vo will sag excessively as seen in
Figure 20 and potentially trigger a system failure. Figure 21 shows
the transient response when Cn is sized too large. In this case Vo will
reach its expected droop voltage much too slowly with respect to the
load insertion. Should a load release occur during this time there will
be excessive overshoot on Vo which may potentially hurt CPU
reliability.
io
Vo
FIGURE 19. DESIRED LOAD TRANSIENT RESPONSE WAVEFORMS
FIGURE 21. LOAD TRANSIENT RESPONSE WHEN Cn IS TOO LARGE
io
iL
Vo
RING
BACK
FIGURE 22. OUTPUT VOLTAGE RING BACK PROBLEM
Figure 22 gives an example of ring back on the output voltage
during load transient response. Ring back occurs when the load
current io has a fast step change, but the inductor current iL
cannot accurately track it. Instead, iL responds in a first order
fashion due to the nature of current loop. Instead of the output
accurately responding to the load insertion the parasitic ESR and
ESL properties of the output capacitors cause an abrupt dip in
the voltage. However, the controller regulates Vo according to the
droop current idroop, which is a real-time representation of iL;
therefore it pulls Vo back to the level dictated by iL, introducing
the ring back into the response. This phenomenon can be
mitigated through the use of very low ESR and ESL ceramic
capacitors for the output filter.
Figure 23 shows two circuits for ring back reduction that can be
used in conjunction with low parasitic output filter components if
need be. Normally Cn, the capacitor used to match the inductor
time constant, is implemented through the parallel combination
of two or more capacitors shown in Figure 23 as Cn.1 and Cn.2.
The first option to reduce ring back is to add resistor Rn in series
to Cn.1. At steady state operation Cn.1 + Cn.2 provide the desired
Cn capacitance calculated from Equation 11. At the beginning of
io change however, the effective capacitance of the matching
17
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ISL95813
network is less because Rn increases the impedance of the Cn.1
branch. As Figure 20 explains, Vo tends to dip when Cn is too
small which will reduce the amount of ring back seen during load
transients. This effect is more pronounced when Cn.1 is larger
than Cn.2 as well as when the value of Rn is increased. However,
when designing the final circuit, care should be taken not to
make Rn larger than necessary or make Cn.1 much larger than
Cn.2 or else excessive ripple will be seen on Vcn. It is
recommended to keep Cn.2 greater than 2200pF and Rn in the
range of only few ohms. The final values of Cn.1, Cn.2 and Rn
should be determined through tuning the load transient response
waveforms on an actual board to be used in the end application.
The second method for ring back reduction is to add the series
combination of Rip and Cip in parallel with Ri. These components
should be sized to provide a lower impedance path than Ri alone at
the beginning of an io transient. During steady state operation Rip
and Cip do not have any effect on the controller’s operation. Through
proper selection of Rip and Cip values, idroop can more closely
resemble io rather than iL, and ring back on the output voltage will
not be seen. The recommended value for Rip is 100Ω. while the
recommended range for Cip is 100pF to 2000pF though final values
should be tuned to the final end product board. It should be noted
that the Rip -Cip branch may distort the idroop signal by introducing
sharp spikes to the normally triangular waveform which may
adversely affect the average value detection and therefore may
affect OCP accuracy. Discretion is recommended when
implementing this second ring back reduction method in order to
maintain a robust system.
ISUMP
Resistor Current-Sensing Network
Phase
L
DCR
Rsen
Cn
Cn.1
Cn.2 Vcn
Rp
Rntc
Rn
OPTIONAL
ISUMN
Ri
Rip
Cip
OPTIONAL
FIGURE 23. OPTIONAL CIRCUITS FOR RING BACK REDUCTION
Vcn
Ri
ISUMN
Io
FIGURE 24. RESISTOR CURRENT-SENSING NETWORK
Above is an example of using a resistor sense method of sensing
load current instead of SCR sensing. In this method, the inductor
current creates a voltage across Rsen which is then filters and
averaged by the RC filter composed of Rsum and Cn. The results
voltage, Vcn, is then fed into the current sense amplifier on chip
through the ISUMP and ISUMN pins. No NTC network is needed in
this scenario because the value of the current sensing resistor, Rsen,
will not vary appreciably over temperature. The design equations for
this method of current sensing are given in Equations 14 through
16.
V Cn ( s ) = R sen × I o ( s ) × A Rsen ( s )
Rntcs
ISUMP
Rsum
1
A Rsen ( s ) = --------------------------s
1 + ----------------ω Rsen
1
ω Rsen = ----------------------------R sum × C n
(EQ. 14)
(EQ. 15)
(EQ. 16)
Recommended values for Rsum and Cn are 1kΩ and 5600pF
respectively. As with the DCR method, final values should be
tuned in on the actual application board.
Overcurrent Protection
Refer to Equation 2 on page 12 and Figures 18, 22 and 25;
resistor Ri sets the droop current Idroop. Table 5 shows the
internal OCP threshold. It is recommended to design Idroop
without using the Rcomp resistor.
For example, assume the OCP threshold is 60µA for 1-phase
solution. We will design Idroop to be 48µA at full load.
From Equation 8 in inductor DCR sensing applications assuming
DC conditions gives the relationship of Vcn(s) to Io(s) in
Equation 17.
R ntcnet
V Cn = ------------------------------------------ × DCR × I o
R ntcnet + R sum
18
(EQ. 17)
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Substituting of Equation 17 into Equation 2 yields Equation 18
which can then be solved for Ri.
R ntcnet
1
I droop = ----- × ------------------------------------------ × DCR × I o
R i R ntcnet + R sum
(EQ. 18)
R ntcnet × DCR × I o
R i = ---------------------------------------------------------------------( R ntcnet + R sum ) × I droop
(EQ. 19)
Expanding the Rntcnet term using Equation 9 and applying of the
OCP condition in Equation 19 gives the final expression for Ri in
Equation 20.
( R ntcs + R ntc ) × R p
---------------------------------------------------× DCR × I omax
R ntcs + R ntc + R p
R i = -----------------------------------------------------------------------------------------------------------------⎛ ( R ntcs + R ntc ) × R p
⎞
⎜ ---------------------------------------------------- + R sum⎟ × I droopmax
⎝ R ntcs + R ntc + R p
⎠
(EQ. 20)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given Rsum = 3.65kΩ,
Rp = 11kΩ, Rntcs = 2.61kΩ, Rntc = 10kΩ, DCR = 0.9mΩ,
Iomax = 33A and Idroopmax = 48µA, Equation 20 gives
Ri = 381Ω.
When resistor sensing methods are used, assuming DC
conditions in Equation 14 gives the following relationship
between Vcn and Io.
V Cn = R sen × I o
(EQ. 21)
Substituting Equation 21 into Equation 2 gives Equation 22:
1
I droop = ----- × R sen × I o
Ri
(EQ. 22)
Therefore
R sen × I o
R i = -----------------------I droop
Idroop into Equation 3 and solve for the DC load line, shown in
Equation 25:
R droop
R ntcnet
V droop
LL = ------------------- = ------------------- × ------------------------------------------ × DCR
Io
Ri
R ntcnet + R sum
For resistor sensing, substitute Equation 22 into Equation 3 to
get the load line slope expression:
R sen × R droop
V droop
LL = ------------------- = --------------------------------------Io
Ri
R sen × I omax
R i = -----------------------------------I droopmax
(EQ. 26)
To find the value of Rdroop, substitute Equation 19 into
Equation 25 and solve for Rdroop, or substitute Equation 23 into
Equation 26 and solve for Rdroop. Both methods give the same
result, which is shown in Equation 27:
Io
R droop = ---------------- × LL
I droop
(EQ. 27)
One can use the full load condition to calculate Rdroop. For
example, given Iomax = 33A, Idroopmax = 48µA and LL = 2.0mΩ,
Equation 27 gives Rdroop = 1.37kΩ.
It is recommended to start with the Rdroop value calculated by
Equation 27 and fine tune it on the actual board to get accurate
load line slope. One should record the output voltage readings at
no load and at full load for load line slope calculation. Reading
the output voltage at lighter load instead of full load will increase
the measurement error.
Compensator
Figure 19 shows the desired load transient response waveforms
while Figure 25 shows the equivalent circuit of a voltage regulator
(VR) with the droop function. A VR is equivalent to a voltage source
(VID) and output impedance Zout(s). If Zout(s) is equal to the load
line slope LL, i.e. constant output impedance, in the entire frequency
range, Vo will have square response when Io has a square change.
(EQ. 23)
Assuming the OCP conditions put in place previously in
Equation 23 gives Equation 24:
(EQ. 25)
Zout(s) = LL
VID
VR
i
o
LOAD
V
o
(EQ. 24)
where Iomax is the full load current, Idroopmax is the
corresponding droop current. For example, given Rsen = 1mΩ,
Iomax = 33A and Idroopmax = 48µA, Equation 24 gives
Ri = 687Ω.
As before, with the DCR and Rsense components, the final value
of Ri should be tuned to fit the final application.
Load Line Slope
For this section please refer to Figure 16 on page 12.
In order to calculate the load line in DCR sense applications start
by substituting Equation 8 into Equation 2 to give a more detailed
expression for Idroop. Next, substitute the new expression for
FIGURE 25. VOLTAGE REGULATOR EQUIVALENT CIRCUIT
A voltage regulator with an active droop function is a dual-loop
system consisting of a voltage loop and a current based droop
loop, of which neither is sufficient to describe the entire system
alone.
Figure 26 conceptually shows T1(s) measurement set-up and
Figure 27 conceptually shows T2(s) measurement set-up. The VR
senses the inductor current, multiplies it by a gain of the load line
slope, then adds it on top of the sensed output voltage and feeds it
to the compensator. T(1) is measured after the summing node,
and T2(s) is measured in the voltage loop before the summing
node.
T1(s) is the total loop gain of the voltage loop and the droop loop.
It always has a higher crossover frequency than T2(s) and has
more meaning of system stability. T2(s) is the voltage loop gain
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May 15, 2013
ISL95813
with closed droop loop. It has more meaning of output voltage
response. Only T2(s) can be actually measured in a laboratory
setting on the ISL95813 regulator.
Typically, one should design the compensator to get stable T1(s)
and T2(s) with sufficient phase margin, and output impedance
equal or smaller than the load line slope.
Q1
VIN
GATE Q2
DRIVER
IO
COUT
20Ω
EA
MOD.
VID
LOOP GAIN =
(EQ. 30)
Assuming Io = Iomax and rewriting Equation 30 gives Equation 31
for choosing the value of Rimon.
(EQ. 31)
For example, given LL = 2.0mΩ, Rdroop = 1.37kΩ, VRimon = 1.2V
at Iomax = 33A, Equation 31 gives Rimon = 100kΩ. The results
from Equation 29 should be treated as a starting point for the
design and the resistor value should be finalized on an actual
application board.
LOAD LINE SLOPE
COMP
0.25I o × LL
V Rimon = ------------------------------ × R imon
R droop
V Rimon × R droop
R imon = ---------------------------------------------0.25I o × LL
VO
L
Next, substitute Equation 29 into Equation 28 giving the final
expression for VRimon.
ISOLATION
TRANSFORMER
CHANNEL B
CHANNEL A
CHANNEL A
CHANNEL B
NETWORK
ANALYZER EXCITATION OUTPUT
A capacitor Cimon should be but in parallel with Rimon to filter the
IMON pin voltage. It is recommended to have a time constant long
enough to remove any switching frequency ripples from the IMON
signal.
Slew Rate Compensation Circuit For VID
Transition
FIGURE 26. LOOP GAIN T1(s) MEASUREMENT SET-UP
Rdroop
Vcore
VO
L
Cvid
Rvid
OPTIONAL
Q1
FB
VIN
GATE Q2
DRIVER
COUT
Ivid
IO
Idroop_vid
COMP
E/A
LOAD LINE SLOPE
20Ω
Σ VDAC DAC
VSSSENSE
EA
X1
VID
LOOP GAIN =
VID
RTN
COMP
MOD.
VIDs
ISOLATION
TRANSFORMER
CHANNEL B
CHANNEL A
CHANNEL A
CHANNEL B
NETWORK
ANALYZER EXCITATION OUTPUT
VSS
INTERNAL TO IC
VID
Vfb
FIGURE 27. LOOP GAIN T2(s) MEASUREMENT SET-UP
Current Monitor
Ivid
Refer to Equation 7 on page 14 for the IMON pin current
expression.
Looking at the “TYPICAL 40Amax, 12.6, APPLICATION DIAGRAM”
on page 1, the current flowing from the IMON pin goes through
Rimon creating a voltage VRimon. The expression for voltage is
expressed in Equation 28:
V Rimon = 0.25 × I droop × R imon
(EQ. 29)
20
Idroop_vid
(EQ. 28)
To expand this expression, first solve Equation 27 for Idroop giving
Equation 29:
Io
I droop = ------------------- × LL
R droop
Vcore
FIGURE 28. SLEW RATE COMPENSATION CIRCUIT FOR VID
TRANSITION
During a large VID transition, the DAC steps through the VIDs at a
controlled slew rate while maintaining an output voltage, Vcore, slew
rate of 10mV/µs.
FN8449.0
May 15, 2013
ISL95813
Figure 28 shows the waveforms of VID transition. During VID
transition, the output capacitor is being charged and discharged,
causing Cout x dVcore/dt current on the inductor. The controller
senses the inductor current increase during the up transition (as
the Idroop_vid waveform shows) and will droop the output voltage
Vcore accordingly, making Vcore slew rate slow. Similar behavior
occurs during the down transition. To get the correct Vcore slew
rate during VID transition, one can add the Rvid to Cvid branch,
whose current Ivid cancels Idroop_vid.
It’s recommended to choose the Rvid and Cvid values from the
reference design as a starting point. Then tweak the actual
values on the board to get the best performance.
During normal transient response, the FB pin voltage is held
constant, therefore is virtual ground in small signal sense. The
Rvid to Cvid network is between the virtual ground and the real
ground, and hence has no effect on transient response.
VR_HOT#/ALERT# Behavior
VR Temperature
Temp Zone
Bit 7 =1
7
1
Bit 6 =1
3% Hysteresis
10
1111 1111
0111 1111
0011 1111
Bit 5 =1
12
0001 1111
Temp Zone
Register
2
8
0001 1111 0011 1111 0111 1111 1111 1111 0111 1111 0011 1111 0001 1111
Status 1
3
= “011”
= “001”
Register = “001”
GerReg
Status1
SVID
ALERT#
VR_HOT#
4
5
13
6
14
9
GerReg
Status1
15
16
11
FIGURE 29. VR_HOT#/ALERT# BEHAVIOR
The ISL95813 sources 60µA of current out of the NTC pin at
1kHz with a 50% duty cycle. The current source flows through the
respective NTC resistor network on the pin and creates a voltage
that is monitored by the controller through an A/D converter
(ADC) to generate the TZONE value. Table 7 shows the
programming table for TZONE. The user needs to scale the NTC
resistor network such that it generates the NTC pin voltage that
corresponds to the left-most column. Do not use any capacitor to
filter the voltage.
Figure 29 shows how the NTC and the NTCG network should be
designed to get correct VR_HOT#/ALERT# behavior when the
system temperature rises and falls which is manifested as the NTC
pin voltage rising and falling. The series of events are:
1. The temperature rises so the NTC pin voltage drops. TZONE
value changes accordingly.
2. The temperature crosses the threshold where TZONE register
Bit 6 changes from 0 to 1.
3. The controller changes Status_1 register bit 1 from 0 to 1.
TABLE 7. TZONE VALUES
4. The controller asserts ALERT#.
VNTC
(V)
TMAX
(%)
TZONE
0.84
>100
FFh
0.88
100
FFh
0.92
97
7Fh
0.96
94
3Fh
1.00
91
1Fh
1.04
88
0Fh
1.08
85
07h
1.12
82
03h
1.16
79
01h
10. The temperature crosses the threshold where TZONE register
Bit 6 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when VR_HOT# gets asserted, to provide 3%
hysteresis.
1.2
76
01h
11. The controllers de-asserts VR_HOT# signal.
>1.2
<76
00h
12. The temperature crosses the threshold where TZONE register
bit 5 changes from 1 to 0. This threshold is 1 ADC step lower
than the one when ALERT# gets asserted during the
temperature rise to provide 3% hysteresis.
5. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register bit 6 flipping.
6. The controller clears ALERT#.
7. The temperature continues rising.
8. The temperature crosses the threshold where TZONE register
Bit 7 changes from 0 to 1.
9. The controllers asserts VR_HOT# signal. The CPU throttles
back and the system temperature starts dropping eventually.
13. The controller changes Status_1 register Bit 1 from 1 to 0.
14. The controller asserts ALERT#.
15. The CPU reads Status_1 register value to know that the alert
assertion is due to TZONE register Bit 5 flipping.
16. The controller clears ALERT#.
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Layout Guidelines
ISL95813
SYMBOL
LAYOUT GUIDELINES
BOTTOM PAD
GND
18, 19, 20
SCLK,
SDA,
ALERT#
Follow Intel recommendation.
1
VR_ON
No special consideration.
2
PGOOD
No special consideration.
3
IMON
No special consideration.
4
VR_HOT#
No special consideration.
5
NTC
6
COMP
7
FB
10
ISUMN
9
ISUMP
Connect this ground pad to the ground plane through low impedance path. Recommend use of at least 5 vias to
connect to ground planes in PCB internal layers.
The NTC thermistor needs to be placed close to the thermal source that is monitored to determine CPU Vcore thermal
throttling. Recommend placing it at the hottest spot of the CPU Vcore VR.
Place the compensator components in general proximity of the controller.
Place the current sensing circuit in general proximity of the controller.
Place capacitor Cn very close to the controller.
Place the NTC thermistor next to the inductor so it senses the inductor temperature correctly.
The power stage requires a pair of VSUMP and VSUMN signals to the controller. These two signal traces should run in
a parallel fashion with decent width (>20mil).
IMPORTANT: Sense the inductor current by routing the sensing circuit to the inductor pads. If possible, route the traces
on a different layer from the inductor pad layer and use vias to connect the traces to the center of the pads. If no via is
allowed on the pad, consider routing the traces into the pads from the inside of the inductor. The following drawings
show the two preferred ways of routing current sensing traces.
IN D U C T O R
IN D U C T O R
V ias
C U R R E N T-S E N S IN G T R A C E S
C U R R E N T-S E N S IN G T R A C E S
13
BOOT1
Use decent wide trace (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
14
UG
15
PHASE
16
LG
Use a decent width (>30mil). Avoid any sensitive analog signal trace from crossing over or getting close.
12
VCC
A capacitor decouples it to GND. Place it in close proximity of the controller.
17
PROG1
Connect a resistor to GND. Place it in close proximity of the controller.
11
PROG2
Connect a resistor to GND. Place it in close proximity of the controller.
8
RTN
Run these two traces in parallel fashion with a decent width (>30mil). Avoid any sensitive analog signal trace from
crossing over or getting close. Recommend routing PHASE trace to high-side MOSFET source pins instead of general
copper.
Place the RTN filter in close proximity of the controller for good decoupling.
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ISL95813
Package Outline Drawing
L20.3x4
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE
Rev 1, 3/10
3.00
0.10 M C A B
0.05 M C
A
B
4
20X 0.25
16X 0.50
+0.05
-0.07
17
A
16
6
PIN 1
INDEX AREA
6
PIN 1 INDEX AREA
(C 0.40)
20
1
4.00
2.65
11
+0.10
-0.15
6
0.15 (4X)
A
10
7
VIEW "A-A"
1.65
TOP VIEW
+0.10
-0.15
20x 0.40±0.10
BOTTOM VIEW
SEE DETAIL "X"
0.10 C
C
0.9± 0.10
SEATING PLANE
0.08 C
SIDE VIEW
(16 x 0.50)
(2.65)
(3.80)
(20 x 0.25)
C
(20 x 0.60)
0.2 REF
5
0.00 MIN.
0.05 MAX.
(1.65)
(2.80)
DETAIL "X"
TYPICAL RECOMMENDED LAND PATTERN
NOTES:
1. Dimensions are in millimeters.
Dimensions in ( ) for Reference Only.
2. Dimensioning and tolerancing conform to AMSE Y14.5m-1994.
3. Unless otherwise specified, tolerance : Decimal ± 0.05
4. Dimension applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
5. Tiebar shown (if present) is a non-functional feature.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 indentifier may be
either a mold or mark feature.
23
FN8449.0
May 15, 2013
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Revision History
The revision history provided is for informational purposes only and is believed to be accurate, but not warranted. Please go to the web to make sure that
you have the latest revision.
DATE
REVISION
May 15, 2013
FN8449.0
CHANGE
Initial Release
About Intersil
Intersil Corporation is a leader in the design and manufacture of high-performance analog, mixed-signal and power management
semiconductors. The company's products address some of the largest markets within the industrial and infrastructure, personal
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For the most updated datasheet, application notes, related documentation and related parts, please see the respective product
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www.intersil.com/en/support/ask-an-expert.html. Reliability reports are also available from our website at
http://www.intersil.com/en/support/qualandreliability.html#reliability
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9000 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time
without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be
accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third
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