INFINEON ISO1H802G

Datasheet, Version 2.4, September 2009
ISOFACE
TM
ISO1H802G
Coreless Transformer Isolated
Digital Output 8 Channel 0.625A
High-Side Switch
Power Management & Drives
N e v e r
s t o p
t h i n k i n g .
ISO1H802G
Revision History:
2009-09-16
Previous Version:
V2.3
2.0
Final Datasheet
2.1
Final Datasheet
2.2
Page 16 creepage, clearance distance and VISO adapted
2.3
Data for parallel channels and UL aproval added
2.4
Diagnostic output discontinued
Version 2.4
Edition 2009-09-16
Published by Infineon Technologies AG,
Am Campeon 1-12,
85579 Neubiberg, Germany
© Infineon Technologies AG 2009.
All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
Terms of delivery and rights to technical change reserved.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in
question please contact your nearest Infineon Technologies Office.
Infineon Technologies Components may only be used in life-support devices or systems with the express written
approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure
of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support
devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain
and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may
be endangered.
ISOFACETM
ISO1H802G
Coreless Transformer Isolated Digital
Output 8 Channel 0.625A High-Side Switch
Product Highlights
•
•
•
•
•
Coreless transformer isolated data interface
Galvanic isolation
8 High-side output switches 0.625A
µC compatible 8-bit serial peripheral
UL508 compliant
Features
Typical Application
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Interface CMOS 5V operation compatible
Serial Interface
High common mode transient immunity
Short circuit protection
Maximum current internally limited
Overload protection
Overvoltage protection (including load dump)
Undervoltage shutdown with autorestart and
hysteresis
Switching inductive loads
Common output disable pin
Thermal shutdown with restart
Thermal independence of seperate channels
ESD protection
Loss of GNDbb and loss of Vbb protection
Very low standby current
Reverse battery protection
RoHS compliant
•
Isolated switch for industrial applications (PLC)
All types of resistive, inductive and capacitive loads
µC compatible power switch for 24V DC
applications
Driver for solenoid, relays and resistive loads
Description
The ISO1H802G is a galvanically isolated 8 bit data
interface in PG-DSO-36 package that provides 8 fully
protected high-side power switches that are able to
handle currents up to 625 mA.
An serial µC compatible interface allows to connect the
IC directly to a µC system. The input interface is
designed to operate with 5V CMOS compatible levels.
The data transfer from input to output side is realized by
the integrated Coreless Transformer Technology.
Typical Application
VCC
VCC
Vbb
DIS
VCCP1.x
Control
Unit
CS
AD0
SCLK
WR
OUT0
Control
&
Protectio
n Unit
SI
P0.0
Vbb
CT
OUT1
Serial
Interface
for daisy chain
SO
reserved
µC (i.e
C166)
OUT7
GND
ISO1H802G
GNDCC
GNDbb
Type
On-state Resistance
Package
ISO1H802G
200mΩ
PG-DSO-36
Datasheet
3
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Pin Configuration and Functionality
1
Pin Configuration and Functionality
1.1
Pin Configuration
Pin
Symbol
1
N.C.
Not connected
2
VCC
Positive 5V logic supply
3
DIS
Output disable
4
CS
Chip select
5
SCLK
Serial Clock
6
SI
7
N.C.
Not connected
8
N.C.
Not connected
9
N.C.
Not connected
10
N.C.
Not connected
11
N.C.
Not connected
12
N.C.
Not connected
13
SO
Serial Data Output
Function
reserved -
15
GNDCC
16
N.C.
Not connected
17
N.C.
Not connected
18
N.C.
Not connected
19
GNDbb
20
N.C
21
OUT7
High-side output of channel 7
22
OUT7
High-side output of channel 7
23
OUT6
High-side output of channel 6
24
OUT6
High-side output of channel 6
25
OUT5
High-side output of channel 5
26
OUT5
High-side output of channel 5
27
OUT4
High-side output of channel 4
28
OUT4
High-side output of channel 4
29
OUT3
High-side output of channel 3
30
OUT3
High-side output of channel 3
31
OUT2
High-side output of channel 2
32
OUT2
High-side output of channel 2
33
OUT1
High-side output of channel 1
34
OUT1
High-side output of channel 1
35
OUT0
High-side output of channel 0
36
OUT0
High-side output of channel 0
TAB
Vbb
Datasheet
N.C.
VCC
DIS
CS
SCLK
SI
N.C.
N.C.
N.C.
N.C.
N.C.
N.C.
SO
reserved
GNDCC
N.C.
N.C.
N.C.
Serial Data input
14
Figure 1
Vbb
Input logic ground
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
TAB
TAB
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
OUT0
OUT0
OUT1
OUT1
OUT2
OUT2
OUT3
OUT3
OUT4
OUT4
OUT5
OUT5
OUT6
OUT6
OUT7
OUT7
N.C.
GNDbb
Vbb
.
Output driver ground
Not connected
Positive driver power supply voltage
Power SO-36 (430mil)
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Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Pin Configuration and Functionality
1.2
Pin Functionality
to Vbb and controlled by the corresponding data input.
VCC (Positive 5V logic supply)
TAB (Vbb, Positive supply for output driver)
The heatslug is connected to the positive supply port of
the output interface.
The VCC supplies the input interface that is
galvanically isolated from the output driver stage. The
input interface can be supplied with 5V.
DIS (Output disable)
The high-side outputs OUT0...OUT7 can be
immediately switched off by means of the low active pin
DIS that is an asynchronous signal. The input registers
are also reset by the DIS signal. The output remains
switched off after low-high transient of DIS, till new data
is written into the input interface.
Current Sink to GNDCC
CS (Chip select)
The system microcontroller selects the ISO1H802G by
means of the low active pin CS to activate the interface.
Current Source to VCC
SCLK (Serial shift clock)
SCLK (serial clock) is used to synchronize the data
transfer between the master and the ISO1H802G. Data
present at the SI pin are latched on the rising edge of
the serial clock input, while data at the SO pin is
updated after the falling edge of SCLK in serial mode.
Current Source to VCC
SI (Serial data input)
This pin is used to transfer data into the device. Data is
latched on the rising edge of the serial clock. Current
Sink to GNDCC
SO (Serial data output)
This pin is used when the serial interface is activated.
SO can be connected to a serial input of a further IC to
built a daisy-chain configuration. It is only actvated if CS
is in low state, otherwise this output is in high
impedance state.
GNDCC (Ground for VCC domain)
This pin acts as the ground reference for the input
interface that is supplied by VCC.
GNDbb (Output driver ground domain)
This pin acts as the ground reference for the output
driver that is supplied by Vbb.
OUT0 ... OUT7 (High side output channel 0 ... 7)
The output high side channels are internally connected
Datasheet
5
Version 2.4, 2009-09-16
Datasheet
6
reserved
SO
SI
SCLK
ISO1H802G
Serial
Input Interface
High-side Channel 7
Logic
Charge
Pump
Level shifter
Rectifier
Undervoltage
Shutdown with
Restart
Charge
Pump
Level Shifter
Rectifier
Common
Diagnostic
Output
High-side Channel
0
Logic
to Logic
Channel 1 - 6
to Logic
Channel 1 - 6
Serial
to
Parallel
Overvoltage
Protection
Temperature Sensor
Overload Protection
Current Limitation
Limitation of Unclamped
Inductive Load
Vbb
Channel 1 ... 6
Gate
Protection
from
Temperature
Sensor
Channel 1 - 6
Temperature Sensor
Overload Protection
Current Limitation
Limitation of Unclamped
Inductive Load
Gate
Protection
Voltage
Source
OUT7
OUT6
OUT5
OUT4
OUT3
OUT2
OUT1
OUT0
GNDbb
Blockdiagram
CS
CT
Figure 2
DIS
Logic
Blockdiagram
GNDCC
Undervoltage
Shutdown with
Restart
Vbb
2
Galvanic
Isolation
VCC
ISOFACETM
ISO1H802G
Blockdiagram
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Functional Description
3
Functional Description
3.1
Introduction
when solenoid loads are switched off. VON is then
clamped to 47V (min.).
The ISOface ISO1H802G includes 8 high-side power
switches that are controlled by means of the integrated
µC compatible SPI interface. The outputs
OUT0...OUT7 are controlled by the data of the serial
input SI. The IC can replace 8 optocouplers and the 8
high-side switches in conventional I/O-Applications as
a galvanic isolation is implemented by means of the
integrated coreless transformer technology. The µC
compatible interfaces allow a direct connection to the
ports of a microcontroller without the need for other
components. Each of the 8 high-side power switches is
protected
against
short
to
Vbb,
overload,
overtemperature and against overvoltage by an active
zener clamp.
Vbb
Vz
VON
OUTx
GNDbb
Figure 3
The diagnostic logic on the power chip recognizes the
overtemperature information of each power transistor.
3.2
Vbb
Inductive and overvoltage output
clamp (each channel)
Energy is stored in the load inductance during an
inductive load switch-off.
EL = 1 ⁄ 2 × L × IL
Power Supply
The IC contains 2 galvanic isolated voltage domains
that are independent from each other. The input
interface is supplied at VCC and the output stage is
supplied at Vbb. The different voltage domains can be
switched on at different time. The output stage is only
enabled once the input stage enters a stable state.
2
Ebb
EAS
ELoad
Vbb
Dx
OUTx
L
3.3
Vbb
Output Stage
GNDbb
EL
ZL
Each channel contains a high-side vertical power FET
that is protected by embedded protection functions.
RL
ER
The continuos current for each channel is 625mA (all
channels ON).
Figure 4
3.3.1
While demagnetizing the load inductance, the energy
dissipation in the DMOS is
Output Stage Control
Each output is independently controlled by an output
latch and a common reset line via the pin DIS that
disables all eight outputs and reset the latches. Serial
data input (SI) is read on the rising edge of the serial
clock SCLK. A logic high input data bit turns the
respective output channel ON, a logic low data bit turns
it OFF. CS must be low whilst shifting all the serial data
into the device. A low-to-high transition of CS transfers
the serial data input bits to the output buffer.
3.3.2
E AS = E bb + E L – E R = V ON ( CL ) × i L ( t )dt
with an approximate solution for RL > 0Ω:
IL × L
IL × RL 
E AS = ---------------- × ( V bb + V ON ( CL ) ) × ln  1 + -----------------------2 × RL
V ON ( CL ) 
3.3.3
Power Transistor Overvoltage
Protection
Power Transistor Overcurrent
Protection
The outputs are provided with a current limitation that
enters a repetitive switched mode after an initial peak
current has been exceeded. The initial peak short
circuit current limit is set to IL(SCp) at Tj = 125°C. During
the repetitive mode short circuit current limit is set to
IL(SCr). If this operation leads to an overtemperature
Each of the eight output stages has its own zener clamp
that causes a voltage limitation at the power transistor
Datasheet
Inductive load switch-off energy
dissipation (each channel)
7
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Functional Description
down by overtemperature, restart by
cooling
condition, a second protection level (Tj > 135°C) will
change the output into a low duty cycle PWM (selective
thermal shutdown with restart) to prevent critical chip
temperatures.
3.4
Reserved
3.5
Serial Interface
IN
t
VOUT
The ISO1H802G contains a serial interface that can be
directly controlled by the microcontroller output ports.
t
TJ
3.5.1
CS - Chip select. The system microcontroller selects
the ISO1H802G by means of the CS pin. Whenever the
pin is in a logic low state, data can be transferred from
the µC.
t
Figure 5
SPI Signal Description
Overtemperature detection
The following figures show the timing for a turn on into
short circuit and a short circuit in on-state. Heating up
of the chip may require several milliseconds,
depending on external conditions.
CS High to low transition:
IN
•Serial input data can be clocked in from then on
•SO changes from high impendance state to logic high
or low state corresponding to the SO bit-state
t
VOUT
CS Low to high transition:
Output short to GND
IL
IL(SCp)
t
IL(SCr)
•Transfer of SI bits from shift register into output
buffers, if number of clock signals was an integer
multiple of 8
t
Figure 6
Turn on into short circuit, shut down by
overtemperature, restart by cooling
•SO changes from the SO bit-state to high impendance
state
To avoid any false clocking the serial input pin SCLK
should be logic high state during high-to-low transition
of CS. When CS is in a logic high state, any signals at
the SCLK and SI pins are ignored and SO is forced into
a high impedance state. The integrated modulo counter
that counts the number of clocks avoids the take over
of invalid commands caused by a spike on the clock
line or wrong number of clock cycles. A command is
only taken over if after the low-to-high transition of the
CS signal the number of counted clock cycles is an
integer multiple of 8.
IN
t
VOUT
Normal
operation
IL
Output short to GND
IL(SCp)
t
IL(SCr)
SCLK - Serial clock. The system clock pin clocks the
internal shift register of the ISO1H802G. The serial
input (SI) accepts data into the input shift register on the
rising edge of SCLK while the serial output (SO) shifts
the output information out of the shift register on the
falling edge of the serial clock. It is essential that the
SCLK pin is in a logic high state whenever chip select
t
Figure 7
Datasheet
Short circuit in on-state, shut down
8
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Functional Description
3.5.2.2
CS makes any transition. The number of clock pulses
will be counted during a chip select cycle. The received
data will only be accepted, if exactly an integer multiple
of 8 clock pulses were counted during CS is active.
Daisy-chain Configuration
The connection of different ICs and a µC as shown in
Fig. 11 is called a daisy-chain. For this type of bustopology only one SPI interface of the µC for two or
more ICs is needed. All ICs share the same clock and
chip select port of the SPI master. That is all ICs are
active and addressed simultaneously. The data out of
the µC is connected to the SI of the first IC in the line.
Each SO of an IC is connected to the SI of the next IC
in the line.
SI - Serial input. Serial data bits are shifted in at this pin,
the most significant bit first. SI information is read in on
the rising edge of the SCLK. Input data is latched in the
shift register and then transferred to the control buffer
of the output stages.
SO - Serial output. SO is in a high impedance state until
the CS pin goes to a logic low state. The data of the
internal shift register are shifted out serially at this pin.
The most significant bit will appear at first. The further
bits will appear following the falling edge of SCLK.
SPI
1
CLK
Tx a1
Tx a2
SPI Bus Concepts
3.5.2.1
Independent Individual Control
Each IC with a SPI is controlled individually and
independently by an SPI master, as in a directional
point-to-point communication.The port requirements
for this topology are the greatest, because for each
controlled IC an individual SPI at the µC is needed
(SCLK, CS, SI). All ICs can be
addressed
simultaneously with the full SPI bandwidth.
SCLK
CS
SI
µC
SPI
1
SCLK
CS
SI
SO
SPI Interface
IC1
SPI
n
CLK
Tx n1
Tx n2
SCLK
CS
SI
SO
SPI Interface
ICn
µC
Datasheet
Output
lines
SPI Interface
ICn
Number of addressed ICs = n
Number of necessary control and data ports = 3
All ICs are addressed by the common chip select
Output
lines
Figure 9
SPI bus all ICs in a “daisy chain”
configuration
The µC feeds to data bits into the SI of IC1 (first IC in
the chain). The bits coming from the SO of IC1 are
directly shifted into the SI of the next IC. As long as the
chip select is inactive (logic high) all the IC SPIs ignore
the clock (SCLK) and input signals (SI) and all outputs
(SO) are in tristate. As long as the chip select is active
the SPI register works as a simple shift register. With
each clock signal one input is shifted into the SPI
register (SI), each bit in the shift register moves one
position further within the register, and the last bit in the
SPI shift register is shifted out of SO. This continuous
as long as the chip select is active (logic low) and clock
signals are applied. The data is then only taken over to
the output buffers of each IC when the CS signal
changes to high from low and recognized as valid data
by the internal modulo counter.
Output
lines
Number of addressed ICs = n
Number of necessary control and data ports = 3 n
Individual ICs are addressed by the chip select
Figure 8
Output
lines
SPI Interface
IC1
3.5.2
CLK
Tx a1
Tx a2
SCLK
CS
SI
SO
Individual independent control of each
IC with SPI
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Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Functional Description
3.6
Transmission Failure Detection
There is a failure detection unit integrated to ensure
also a stable functionality during the integrated
coreless transformer transmission. This unit decides
wether the transmitted data is valid or not. If four times
serial data coming from the internal registers is not
accepted the output stages are switched off until the
next valid data is received.
Datasheet
10
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Functional Description
3.7
Serial Interface Timing
Chipselect active
CS
SCLK
n+7
SI
SO
Figure 10
n+5
n+4
n+3
n+2
n+1
n
n-1
n-2
n-3
n-4
n-5
n-6
n-7
Serial interface
tp(SCLK)
tCSS
tCSH
≈
CS
n
n+6
tCSD
tSU
SI
Figure 11
≈ ≈ ≈
SCLK
tHD
MSB In
LSB In
Serial input timing diagram
≈≈
CS
SCLK
t SODIS
SO
Figure 12
Datasheet
≈ ≈
tVALID
MSB Out
LSB Out
Serial output timing diagram
11
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
4
Electrical Characteristics
Note: All voltages at pins 2to 14 are measured with respect to ground GNDCC (pin 15). All voltages at pin 20 to
pin 36 and TAB are measured with respect to ground GNDbb (pin 19). The voltage levels are valid if other
ratings are not violated. The two voltage domains VCC ,GNDCC and Vbb ,GNDbb are internally galvanic
isolated.
4.1
Absolute Maximum Ratings
Note: Absolute maximum ratings are defined as ratings, which when being exceeded may lead to destruction of
the integrated circuit. For the same reason make sure, that any capacitor that will be connected to pin 2
(VCC) and TAB (Vbb) is discharged before assembling the application circuit. Supply voltages higher than
Vbb(AZ) require an external current limit for the GNDbb pin, e.g. with a 15Ω resistor in GNDbb connection.
Operating at absolute maximum ratings can lead to a reduced lifetime.
Parameter
at Tj = -40 ... 135°C, unless otherwise specified
Symbol
Supply voltage input interface (VCC)
VCC
Limit Values
Unit
min.
max.
-0.5
6.5
1)
45
Supply voltage output interface (Vbb)
Vbb
-1
Continuous voltage at pin SI
VDx
-0.5
6.5
Continuous voltage at pin CS
VCS
-0.5
6.5
Continuous voltage at pin SCLK
VWR
-0.5
6.5
Continuous voltage at pin DIS
VDIS
-0.5
6.5
Continuous voltage at pin SO
VDx
-0.5
6.5
Continuous voltage at reserved pin
VReserved
-0.5
6.5
Load current (short-circuit current)
IL
---
self limited
Reverse current through GNDbb1)
IGNDbb
-1.6
---
Operating Temperature
Tj
-25
Storage Temperature
Tstg
-50
150
Ptot
---
3.3
Power Dissipation
2)
3)
Inductive load switch-off energy dissipation single
pulse, Tj = 125°C, IL = 0.625A
one channel active
all channel simultaneously active (each channel)
Load dump protection3) VloadDump4)=VA + VS
VIN = low or high
td = 400ms, RI = 2W, RL = 27W, VA = 13.5V
td = 350ms, RI = 2W, RL = 57W, VA = 27V
10
1
VLoaddump
V
-----
Electrostatic discharge voltage (Charge Device Model)
according to ESD STM5.3.1 - 1999
VESD
Continuous reverse drain current1)3), each channel
IS
W
J
---
VESD
A
internal limited °C
EAS
Electrostatic discharge voltage (Human Body Model)
according to JESD22-A114-B
V
90
117
kV
2
kV
1
---
4
A
1) defined by Ptot
2) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
3) not subject to production test, specified by design
4) VLoaddump is setup without the DUT connected to the generator per ISO7637-1 and DIN40839
Datasheet
12
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
4.2
Thermal Characteristics
Parameter
Symbol
at Tj = -25 ... 125°C, Vbb=15...30V, VCC= 4.5...5.5V,
unless otherwise specified
Thermal resistance junction - case
RthJC
Thermal resistance @ min. footprint
Thermal resistance @ 6cm² cooling area
Rth(JA)
1)
Rth(JA)
Limit Values
Unit Test Condition
min.
typ.
max.
-------
-------
1.5
K/W
50
38
1) Device on 50mm*50mm*1.5mm epoxy PCB FR4 with 6cm² (one layer, 70µm thick) copper area for drain connection. PCB
is vertical without blown air.
4.3
Load Switching Capabilities and Characteristics
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=
4.5...5.5V, unless otherwise specified
On-state resistance, IL = 0.5A, each channel
Tj = 25°C
Tj = 125°C
two parallel channels, Tj = 25°C:1)
four parallel channels, Tj = 25°C:1
Nominal load current
Device on PCB 38K/W, Ta = 85°C, Tj < 125°C
one channel:1)
two parallel channels:1)
four parallel channels:1)
Symbol
RON
Limit Values
Unit
min.
typ.
max.
-----
150
270
75
38
200
320
100
50
Test Condition
mΩ
IL(NOM)
0.7
1.1
2.2
A
Turn-on time to 90% VOUT2)
RL = 47Ω, VDx = 0 to 5V
ton
---
64
120
Turn-off time to 10% VOUT1)
RL = 47Ω, VDx = 5 to 0V
toff
---
89
170
Slew rate on 10 to 30% VOUT
RL = 47Ω, Vbb = 15V
dV/dton
---
1
2
Slew rate off 70 to 40% VOUT
RL = 47Ω, Vbb = 15V
-dV/dtoff
---
1
2
µs
V/µs
1) not subject to production test, specified by design
2) The turn-on and turn-off time includes the switching time of the high-side switch and the transmission time via the coreless
transformer in normal operating mode. During a failure on the coreless transformer transmission turn-on or turn-off time
can increase by up to 50µs.
4.4
Operating Parameters
Parameter
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=
4.5...5.5V, unless otherwise specified
Symbol
Common mode transient immunity1)
Magnetic field immunity
Voltage domain Vbb
(Output interface)
Datasheet
1)
Limit Values
Unit
min.
typ.
max.
dVISO/dt
-25
-
25
HIM
100
Vbb(under)
7
---
10.5
Undervoltage restart
Vbb(u_rst)
---
---
11
13
kV/µs DVISO = 500V
A/m
Undervoltage shutdown
Test Condition
IEC61000-4-8
V
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
Undervoltage hysteresis
∆Vbb(under)
Undervoltage current
Ibb(uvlo)
Operating current
0.5
---
1
2.5
mA
Vbb < 7V
IGNDL
-------
10
14
mA
All Channels
ON - no load
Leakage output current
(included in Ibb(off))
VDx = low, each channel
IL(off)
---
5
30
µA
Voltage domain VCC Operating voltage
(Input interface)
Undervoltage shutdown
VCC
4.5
5.5
V
VCC(under)
2.5
Undervoltage restart
VCC(u_rst)
Undervoltage hysteresis
∆VCC(under)
0.1
---
Undervoltage current
ICC(uvlo)
1
2
mA
Operating current
ICC(on)
---------
-------
4.5
6
mA
2.9
3
Vcc < 2.5V
1) not subject to production test
4.5
Output Protection Functions
Parameter1)
Symbol
at Tj = -25 ... 125°C, Vbb=15...30V, VCC=4.5...5.5V,
unless otherwise specified
Initial peak short circuit current limit, each channel IL(SCp)
Vbb = 30V, tm = 700µs
Tj = -25°C
Tj = 25°C
Tj = 125°C
two parallel channels:3)
four parallel channels:3)
Limit Values
min.
typ.
Unit Test Condition
max.
A
----0.7
--1.4
---
1.9
-----
twice the current of one channel
four times the current of one channel
Repetitive short circuit current limit3)
IL(SCr)
Tj = Tjt (see timing diagrams)
each channel:
two parallel channels:3)
four parallel channels:3)
---
Output clamp (inductive load switch off)
at VOUT = Vbb - VON(CL)
VON(CL)
47
53
60
V
Overvoltage protection
Vbb(AZ)
47
Tjt
135
-----
°C
∆Tjt
---
10
-------
Thermal overload trip temperature
Thermal hysteresis
2) 3)
3)
--1.1
1.1
1.1
K
1) Integrated protection functions are designed to prevent IC destruction under fault conditions described in the data sheet.
Fault conditions are considered as “outside” normal operating range. Protection functions are not designed for continuos
repetitive operation.
2) Higher operating temperature at normal function for each channel available
3) not subject to production test, specified by design
4.6
Datasheet
Reserved
14
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
4.7
Input Interface
Parameter
Symbol
at Tj = -25 ... 125°C, Vbb=15...30V, VCC= 4.5...5.5V,
unless otherwise specified
Limit Values
Unit Test Condition
min.
typ.
max.
Input low state voltage
(SI, DIS, CS, SCLK)
VIL
-0.3
---
0.3 x
VCC
Input high state voltage
(SI, DIS, CS, SCLK)
VIH
0.7 x
VCC
---
VCC+
0.3
Input voltage hysteresis
(SI, DIS, CS, SCLK)
VIHys
Output low state voltage
(SO)
VOL
-0.3
---
0.25 x V
VCC
Output high state voltage
(SO)
VOH
0.75 x
VCC
---
VCC+
0.3
Input pull down current
(SI , DIS)
IIdown
100
Input pull up current
(CS, SCLK)
-IIup
100
Output disable time (transition DIS to logic low)1)2)
Normal operation
Turn-off time to 10% VOUT
RL = 47Ω
tDIS
---
85
170
Output disable time (transition DIS to logic low)1)2)3)
Disturbed operation
Turn-off time to 10% VOUT
RL = 47Ω
tDIS
---
---
230
100
V
mV
CL < 50pF,
RL > 10kΩ
µA
µs
1) The time includes the turn-on/off time of the high-side switch and the transmission time via the coreless transformer.
2) If Pin DIS is set to low the outputs are set to low; after DIS set to high a new write cycle is necessary to set the output again.
3) The parameter is not subject to production test - verified by design/characterization
Datasheet
15
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
4.8
SPI Timing
Parameter
Symbol
at Tj = -25 ... 125°C, Vbb=15...30V, VCC= 4.5...5.5V,
unless otherwise specified
Limit Values
Unit Test Condition
min.
typ.
max.
fSCLK
DC
20
MHz
tp(SLCK)
50
tCSS
5
-----
ns
CS Setup time (falling edge of CS to falling edge of
SCLK)
-------
CS Hold time (rising edge of SCLK to rising edge
of CS)
tCSH
10
---
---
CS Disable time (CS high time between two
accesses)
tCSD
10
---
---
Data setup time (required time SI to rising edge of
SCLK)
tSU
6
---
---
Data hold time (falling edge of SCLK to SI)
tHD
6
---
---
---
---
20
Serial clock frequency
Serial clock period (1/fclk)
SO Output valid time
CL = 50pF
tVALID
SO Output disable time
tSODIS
4.9
20
Reverse Voltage
Parameter
Symbol
at Tj = -25 ... 125°C, Vbb=15...30V, VCC= 4.5...5.5V,
unless otherwise specified
Reverse voltage1)2)
RGND = 0 Ω
RGND = 150 Ω
-Vbb
Diode forward on voltage
IF = 1.25A, VDx = low, each channel
-VON
Limit Values
Unit Test Condition
min.
typ.
max.
-----
-----
1
45
---
---
1.2
V
1) defined by Ptot
2) not subject to production test, specified by design
Datasheet
16
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Electrical Characteristics
4.10
Isolation and Safety-Related Specification
Parameter
Value
Unit
Conditions
Rated dielectric isolation voltage VISO
500
VAC
1 - minute duration1)
Short term temporary overvoltage
1250
V
5s acc. DIN EN60664-1 1)
Minimum external air gap (clearance)
2.6
mm
shortest distance through air.
Minimum external tracking (creepage)
2.6
mm
shortest distance path along body.
Minimum Internal Gap
0.01
mm
Insulation distance through
insulation
1) not subject to production test, verified by characterization; Production Test with 1100V, 100ms duration
Approvals:
UL508, CSA C22.2 NO.14
Certificate Number: 20090514-E329661
4.11
Reliability
For Qualification Report please contact your local Infineon Technologies office!
Datasheet
17
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Package Outlines
Package Outlines
0.65
0.25 +0.13
15.74 ±0.1
(Heatslug)
6.3
(Mold)
5˚ ±3˚
0.02
2.8
0.1 C
B
0.25 +0.07
-
0 +0.1
1.1 ±0.1
11 ±0.15 1)
1.3
(Plastic Dual Small
Outline Package)
3.25 ±0.1
PG-DSO-36
3.5 MAX.
5
Heatslug
0.95 ±0.15
36x
0.25 M A B C
14.2 ±0.3
0.25 B
19
19
1
18
10
36
5.9 ±0.1
(Metal)
36
3.2 ±0.1
(Metal)
Bottom View
Index Marking
1 x 45˚
15.9 ±0.1 1)
(Mold)
1)
Figure 13
Datasheet
A
13.7 -0.2
(Metal)
Does not include plastic or metal protrusion of 0.15 max. per side
1
Heatslug
gps09181_1
PG-DSO-36
18
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Package Outlines
Datasheet
19
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Package Outlines
Datasheet
20
Version 2.4, 2009-09-16
ISOFACETM
ISO1H802G
Package Outlines
Datasheet
21
Version 2.4, 2009-09-16
Total Quality Management
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gleichermaßen der Lieferqualität und
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