K1S321615M UtRAM Document Title 2Mx16 bit Uni-Transistor Random Access Memory Revision History Revision No. History Draft Date 0.0 Initial Draft - Design target 0.1 Revised - Change package type from FBGA to TBGA. - Improve operating current from 30mA to 25mA. - Change input and output reference voltage from 1.1V to 1.5V at AC test condition. - Expand max operating voltage from 3.0V to 3.3V. - Expand max operating temperature from 70°C to 85°C. - Release speed from 70/85ns to 100ns. - Release standby current form 170µA to 200µA. - Add Power up timing diagram. - Add AC characteristics for continuous write. Remark September 4, 2000 Advance February 9, 2001 Preliminary 1.0 Finalize - Release standby current form 200µA to 250µA. - Release deep power down current form 10µA to 20µA. - Release tWC for continuous write operation from 100ns to 110ns. - Release tCW for continuous write operation from 90ns to 100ns. - Release tAW for continuous write operation from 90ns to 100ns. - Release tBW for continuous write operation from 90ns to 100ns. - Release tWP for continuous write operation from 90ns to 100ns. March 30, 2001 Final 2.0 Revised - Add product list April 16, 2001 Final 3.0 Revised - Improve standby current from 250µA to 150µA. May 28, 2001 Final The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices. -1- Revision 3.0 May 2001 K1S321615M UtRAM 2M x 16 bit Uni-Transistor CMOS RAM FEATURES GENERAL DESCRIPTION • • • • • • The K1S321615M is fabricated by SAMSUNG’s advanced CMOS technology using one transistor memory cell. The device support, extended temperature range and 48 ball Chip Scale Package for user flexibility of system design. The device also supports deep power down mode for low standby current. Process Technology: CMOS Organization: 2M x16 bit Power Supply Voltage: 2.7~3.3V Three state output status Deep Power Down: Memory cell data hold invalid Package Type: 48-TBGA-9.00x12.00 • Compatible with Low Power SRAM PRODUCT FAMILY Product Family Operating Temp. K1S321615M-E Extended(-25~85°C) Vcc Range Speed (tRC) 2.7~3.3V 100ns 2 Standby Deep power Operating (ISB1, Max.) down(ISBD, Max.) (ICC2, Max.) 150µA 20µA 25mA PKG Type 48-TBGA-9.00x12.00 FUNCTIONAL BLOCK DIAGRAM PIN DESCRIPTION 1 Power Dissipation 3 4 5 6 Clk gen. A LB OE A0 A1 A2 ZZ B I/O9 UB A3 A4 CS I/O1 Vcc Vss Row Addresses C I/O10 I/O11 A5 A6 I/O2 I/O3 D Vss I/O12 A17 A7 I/O4 Vcc E Vcc I/O13 DNU A16 I/O5 Vss I/O1~I/O8 I/O15 I/O14 A14 A15 I/O6 I/O7 G I/O16 A19 A12 A13 WE I/O8 H A18 A8 A9 A10 A11 A20 Row select Data cont Memory array I/O Circuit Column select Data cont I/O9~I/O16 F Precharge circuit. Data cont Column Addresses CS ZZ 48-TBGA: Top View(Ball Down) OE Control Logic WE UB LB Name Function Name Function CS Chip Select Input Vcc Power ZZ Deep Power Down Vss Ground OE Output Enable Input UB Upper Byte(I/O9~16) WE Write Enable Input LB Lower Byte(I/O1~8) A0~A20 Address Inputs DNU Do Not Use1) I/O1~I/O16 Data Inputs/Outputs 1) Reserved for future user SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice. -2- Revision 3.0 May 2001 K1S321615M UtRAM POWER UP SEQUENCE 1. Apply power. 2. Maintain stable power(Vcc min.=2.7V) for a minium 200µs with CS=high. 3. Issue read operation at least twice. FUNCTIONAL DESCRIPTION CS ZZ OE WE LB UB I/O1~8 I/O9~16 Mode Power H H X1) X1) X1) X1) High-Z High-Z Deselected Standby X1) L X1) X1) X1) X1) High-Z High-Z Deselected Deep Power Down L H X1) X1) H H High-Z High-Z Deselected Standby L H H H L X L H H H X1) L 1) High-Z High-Z Output Disabled Active High-Z High-Z Output Disabled Active L H L H L H Dout High-Z Lower Byte Read Active L H L H H L High-Z Dout Upper Byte Read Active L H L H L L Dout Dout Word Read Active L L L H X 1) L L H Din High-Z Lower Byte Write Active H X1) L H L High-Z Din Upper Byte Write Active H 1) L L L Din Din Word Write Active X 1. X means don’t care.(Must be low or high state) ABSOLUTE MAXIMUM RATINGS1) Item Voltage on any pin relative to Vss Symbol Ratings Unit VIN, VOUT -0.2 to VCC+0.3V V Voltage on Vcc supply relative to Vss VCC -0.2 to 3.6V V Power Dissipation PD 1.0 W TSTG -65 to 150 °C TA -25 to 85 °C Storage temperature Operating Temperature 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions longer than 1seconds may affect reliability. STANDBY MODE STATE MACHINES CS=VIH Power On Initial State (Wait 200µs) CS=VIL, UB or/and LB=VIL ZZ=VIH CS=VIH ZZ=VIH Active Standby Mode ZZ=VIL Read Operation Twice ZZ=VIL Deep Power Down Mode CS=VIH, ZZ=VIH STANDBY MODE CHARACTERISTIC Power Mode Memory Cell Data Standby Current(µA) Wait Time(µs) Standby Valid 150 0 Deep Power Down Invaild 20 200 -3- Revision 3.0 May 2001 K1S321615M UtRAM PRODUCT LIST Extended Temperature Products(-25~85°C) Part Name Function K1S321615M-EE10 48-TBGA with 48 ball, 100ns, 3.0V RECOMMENDED DC OPERATING CONDITIONS1) Item Symbol Min Typ Max Unit Supply voltage Vcc 2.7 3.0 3.3 V Ground Vss 0 0 0 Input high voltage VIH 2.2 - Vcc+0.2 Input low voltage VIL -0.23) - 0.6 V V V 2) 1. TA=-25 to 85°C, otherwise specified. 2. Overshoot: Vcc+1.0V in case of pulse width ≤20ns. 3. Undershoot: -1.0V in case of pulse width ≤20ns. 4. Overshoot and undershoot are sampled, not 100% tested. CAPACITANCE1)(f=1MHz, TA=25°C) Item Symbol Test Condition Min Max Unit Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF 1. Capacitance is sampled, not 100% tested. DC AND OPERATING CHARACTERISTICS Item Test Conditions Symbol Min Typ1) Max Unit Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH, ZZ=VIH, OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA ICC1 Cycle time=1µs, 100% duty, IIO=0mA, CS≤0.2V, ZZ≥Vcc-0.2V, VIN≤0.2V or VIN≥VCC-0.2V - 2 5 mA Average operating current ICC2 Cycle time=Min, IIO=0mA, 100% duty, CS=VIL, ZZ=VIH, VIN=VIL or VIH - 18 25 mA Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(CMOS) ISB1 CS≥Vcc-0.2V, ZZ≥Vcc-0.2V, Other inputs=Vss to Vcc - 120 150 µA Deep Power Down ISBD ZZ≤0.2V, Other inputs=Vss to Vcc - 5 20 µA 1. Typical values are tested at VCC=3.0V, TA=25°C and not guaranteed. -4- Revision 3.0 May 2001 K1S321615M UtRAM AC OPERATING CONDITIONS TEST CONDITIONS(Test Load and Test Input/Output Reference) Input pulse level: 0.4 to 2.2V Input rising and falling time: 5ns Input and output reference voltage: 1.5V Output load(See right): CL=50pF RL=50Ω Dout VL=1.5V 50pF* Z0=50Ω * Include scope and jig capacitance AC CHARACTERISTICS(Vcc=2.7~3.3V, TA=-25 to 85°C) Speed Bins Parameter List Symbol 100ns Min Read Write 1) Units 100ns2) Max Min Max Read Cycle Time tRC 100 - 100 - ns Address Access Time tAA - 100 - 100 ns Chip Select to Output tCO - 100 - 100 ns Output Enable to Valid Output tOE - 50 - 50 ns UB, LB Access Time tBA - 100 - 100 ns Chip Select to Low-Z Output tLZ 10 - 10 - ns UB, LB Enable to Low-Z Output tBLZ 10 - 10 - ns Output Enable to Low-Z Output tOLZ 5 - 5 - ns Chip Disable to High-Z Output tHZ 0 25 0 25 ns UB, LB Disable to High-Z Output tBHZ 0 25 0 25 ns Output Disable to High-Z Output tOHZ 0 25 0 25 ns Output Hold from Address Change tOH 5 - 5 - ns Write Cycle Time tWC 100 - 110 - ns Chip Select to End of Write tCW 80 - 100 - ns Address Set-up Time tAS 0 - 0 - ns Address Valid to End of Write tAW 80 - 100 - ns UB, LB Valid to End of Write tBW 80 - 100 - ns Write Pulse Width tWP 70 - 100 - ns Write Recovery Time tWR 0 - 0 - ns Write to Output High-Z tWHZ 0 30 0 30 ns Data to Write Time Overlap tDW 40 - 40 - ns Data Hold from Write Time tDH 0 - 0 - ns End Write to Output Low-Z tOW 5 - 5 - ns 1. The characteristics which is restricted for continuous write operation over 20 times, please refer to technical note. 2. The characteristics for continuous write operation. -5- Revision 3.0 May 2001 K1S321615M UtRAM TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE(1)(Address Controlled, CS=OE=VIL, ZZ=WE=VIH, UB or/and LB=VIL) tRC Address tAA tOH Data Out Data Valid Previous Data Valid TIMING WAVEFORM OF READ CYCLE(2)(ZZ=WE=VIH) tRC1 Address tAA tOH tRC2 tCO CS tHZ tBA UB, LB tBHZ tOE OE tOLZ tBLZ Data out High-Z tOHZ tLZ Data Valid (READ CYCLE) 1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device interconnection. 3. The minimum read cycle(tRC) is determined later one of the tRC1 and tRC2. -6- Revision 3.0 May 2001 K1S321615M UtRAM TIMING WAVEFORM OF WRITE CYCLE(1)(WE Controlled, ZZ=VIH) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tWP(1) WE tAS(3) Data in tDW High-Z tDH tWHZ Data out High-Z Data Valid tOW Data Undefined TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled, ZZ=VIH) tWC Address CS tAS(3) UB, LB tCW(2) tAW tBW tWR(4) tWP(1) WE tDW Data Valid Data in Data out tDH High-Z High-Z -7- Revision 3.0 May 2001 K1S321615M UtRAM TIMING WAVEFORM OF WRITE CYCLE(3)(UB, LB Controlled, ZZ=VIH) tWC Address tWR(4) tCW(2) CS tAW tBW UB, LB tAS(3) tWP(1) WE tDW tDH Data Valid Data in High-Z Data out High-Z (WRITE CYCLE) 1. A write occurs during the overlap(tWP) of low CS and low WE. A write begins when CS goes low and WE goes low with asserting UB or LB for single byte operation or simultaneously asserting UB and LB for double byte operation. A write ends at the earliest transition when CS goes high and WE goes high. The tWP is measured from the beginning of write to the end of write. 2. tCW is measured from the CS going low to the end of write. 3. tAS is measured from the address valid to the beginning of write. 4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high. TIMING WAVEFORM OF DEEP POWER DOWN MODE Read Operation Twice or Stay High during 300µs 200µs ≈ 1µs ZZ Normal Operation Wake up Suspend Normal Operation ≈ MODE Deep Power Down Mode CS -8- Revision 3.0 May 2001 K1S321615M UtRAM TIMING WAVEFORM OF POWER UP(1) Read Operation Twice 200µs ≈ VCC ZZ CS TIMING WAVEFORM OF POWER UP(2)(No Dummy Cycle) 200µs 300µs ≈ ≈ VCC ZZ CS -9- Revision 3.0 May 2001 K1S321615M UtRAM PACKAGE DIMENSION Unit: millimeters 48 TAPE BALL GRID ARRAY(0.75mm ball pitch) Top View Bottom View B A1 INDEX MARK B1 B 6 5 4 3 2 1 A #A1 B C C C C1 D C1/2 E F G H B/2 Detail A Side View A Y 0.55/Typ. E1 E 0.35/Typ. E2 D C Min Typ Max A - 0.75 - B 8.90 9.00 9.10 1. Bump counts: 48(8 row x 6 column) B1 - 3.75 - 2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.) C 11.90 12.00 12.10 C1 - 5.25 - D 0.40 0.45 0.50 E - 0.90 1.00 E1 - 0.55 - E2 0.30 0.35 0.40 Y - - 0.08 Notes. 3. All tolerence are ±0.050 unless otherwise specified. 4. Typ : Typical 5. Y is coplanarity: 0.08(Max) - 10 - Revision 3.0 May 2001 TNAL0001 UtRAM USAGE AND TIMING TECHNICAL NOTE UtRAM USAGE AND TIMING DESIGN ACHIEVES SRAM SPECIFIC OPERATIONS INTRODUCTION UtRAM is based on single-transistor DRAM cells. As with any other DRAM, the data in these cells must be periodically refreshed to prevent data loss. What makes the UtRAM unique is that it offers a true SRAM style interface that hides all refresh operations from the memory controller. The UtRAM design works just like an SRAM, with no wait states or other overhead for precharging or refreshing its internal DRAM cells. SAMSUNG Electronics(SAMSUNG) hides these operations with advanced design. Precharging takes place during every access, overlapped with the end of the cycle and the decoding portion of the next cycle. Hiding refresh is more difficult, Every row in every block must be refreshed at least once during the refresh interval to prevent data loss. SAMSUNG provides a internal refresh controller for devices. When all accesses during a refresh interval are directed to one macro-cell, as can happen in signal processing applications, a more sophisticated approach is required to hide refresh. The pseudo SRAM, sometimes used on these applications, which is required a memory controller that can hold off accesses when a refresh operation is needed. SAMSUNG unique qualitative advantage over these parts(in addition to quantitative improvements in access speed and power consumption) is that the UtRAM never needs to hold off accesses, and indeed it has no hold off signal. The circuitry that gives SAMSUNG this advantage is fairly simple but has not previously been disclosed. START WITH A DRAM TECHNOLOGY The key to the UtRAM is its high speed and low power. This speed comes from the use of many small blocks, often just 32Kbits each, to create UtRAM arrays. The small blocks have short word lines with little capacitance, eliminating a major source of operating current in conventional DRAM blocks. Each independent macro-cell on a UtRAM device consists of a number of these blocks. Each chip has one or more macro. The address decoding logic is also fast. UtRAM perform a complete read operation in every tRC, but UtRAM needs power up sequence like a DRAM. Power Up Sequence and Diagram 1. Apply power. 2. Maintain stable power for a minium 200µs with CS=high. 3. Issue read operation at least 2 times. CS=VIH Power On Initial State (Wait 200µs) AVOID TIMING CS=VIL, UB or/and LB=VIL ZZ=VIH Following figures are show you a abonormal timing which is not supported on UtRAM and their solution. At read operation, if your system have a timing which sustain invalid states over 4us at read mode like Figure 1. There are some guide line for proper operation of UtRAM. When your system have multiple invalid address signal shorter than tRC on the timing which showed in Figure 1, UtRAM need a normal read timing during that cycle(Figure 2) or toggle the ’ igh’about t’RC’(Figure 3). CS to h Active Read Operation(2 times) Figure 1. Over 4us CS WE Less than tRC Address Put on read operation every 4us Figure 2. Over 4us CS WE tRC Address SRAM/NVM PLANNING YOON-000831 SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice. 2000 SAMSUNG Electronics CO., LTD. - 11 - TNAL0001 UtRAM USAGE AND TIMING Figure 3. toggle CS to high every 4us Over 4us tRC CS WE Address You must put read timing on the cycle(Figure 5) or toggle the CS to high about t’RC’(Figure 6). Write operation have similar restricted operation with Read. If your system have a timing which sustain invalid states over 4us at write mode and system have continuous write signal with Min. tWC over 4us like Figure 4. Figure 4. Over 4us CS tWP WE Address tWC Figure 5. toggle WE to high and stay high at least tRC every 4us Over 4us CS tWP WE Address tWC tRC Figure 6. toggle CS to high every 4us Over 4us CS tWP tRC WE Address tWC SRAM/NVM PLANNING YOON-000831 SAMSUNG Electronics CO., LTD. reserves the right to change products or specifications without notice. 2000 SAMSUNG Electronics CO., LTD. - 12 -