SAMSUNG K4S561632D

K4S561632D
CMOS SDRAM
256Mbit SDRAM
4M x 16bit x 4 Banks
Synchronous DRAM
LVTTL
Revision 0.1
Aug. 2002
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
Revision History
Revision 0.0 (Jan., 2002)
-First generation
Revision 0.1(Aug.,2002)
- ICC6 of Low power is changed from 1.0 to 1.5 due to typo.
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
4M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
GENERAL DESCRIPTION
• JEDEC standard 3.3V power supply
The K4S561632D is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabri-
• LVTTL compatible with multiplexed address
cated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
• DQM for masking
Part No.
• Auto & self refresh
• 64ms refresh period (8K Cycle)
Max Freq.
Interface Package
K4S561632D-TC/L60
166MHz(CL=3)
K4S561632D-TC/L7C
133MHz(CL=2)
K4S561632D-TC/L75
133MHz(CL=3)
K4S561632D-TC/L1H
100MHz(CL=2)
K4S561632D-TC/L1L
100MHz(CL=3)
LVTTL
54pin
TSOP(II)
FUNCTIONAL BLOCK DIAGRAM
I/O Control
Data Input Register
LWE
LDQM
Bank Select
4M x 16
4M x 16
Output Buffer
4M x 16
Sense AMP
Row Decoder
ADD
Row Buffer
Refresh Counter
DQi
Column Decoder
Col. Buffer
LCBR
LRAS
A ddress Register
CLK
4M x 16
Latency & Burst Length
LCKE
Programming Register
LRAS
LCBR
LWE
LCAS
LWCBR
LDQM
Timing Register
CLK
CKE
CS
RAS
CAS
WE
L(U)DQM
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
PIN CONFIGURATION (Top view)
V DD
DQ0
V DDQ
DQ1
DQ2
V SSQ
DQ3
DQ4
V DDQ
DQ5
DQ6
V SSQ
DQ7
V DD
LDQM
WE
CAS
RAS
CS
BA0
BA1
A10/AP
A0
A1
A2
A3
V DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
V SS
DQ15
V SSQ
DQ14
DQ13
V DDQ
DQ12
DQ11
V SSQ
DQ10
DQ9
V DDQ
DQ8
V SS
N.C/RFU
UDQM
CLK
CKE
A12
A11
A9
A8
A7
A6
A5
A4
V SS
54Pin TSOP (II)
(400mil x 875mil)
(0.8 mm Pin pitch)
PIN FUNCTION DESCRIPTION
Pin
Name
Input Function
CLK
System cock
Active on the positive going edge to sample all inputs.
CS
Chip select
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM
CKE
Clock enable
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
A 0 ~ A 12
Address
Row/column addresses are multiplexed on the same pins.
Row address : RA 0 ~ RA12 , Column address : CA 0 ~ CA 8
BA 0 ~ BA 1
Bank select address
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
RAS
Row address strobe
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
CAS
Column address strobe
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
WE
Write enable
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
L(U)DQM
Data input/output mask
Makes data output Hi-Z, t SHZ after the clock and masks the output.
Blocks data input when L(U)DQM active.
D Q0 ~
Data input/output
Data inputs/outputs are multiplexed on the same pins.
V DD /VSS
Power supply/ground
Power and ground for the input buffers and the core logic.
V DDQ /VSSQ
Data output power/ground
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
N.C/RFU
No connection
/reserved for future use
This pin is recommended to be left No Connection on the device.
15
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
ABSOLUTE MAXIMUM RATINGS
Symbol
Value
Unit
Voltage on any pin relative to Vss
Parameter
V IN, V OUT
-1.0 ~ 4.6
V
Voltage on VDD supply relative to Vss
V DD, VDDQ
-1.0 ~ 4.6
V
T STG
-55 ~ +150
°C
Power dissipation
PD
1
W
Short circuit current
IOS
50
mA
Storage temperature
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, T A = -0 to 70°C)
Parameter
Symbol
Min
Typ
Max
Unit
Note
V DD , VDDQ
3.0
3.3
3.6
V
4
Input logic high voltage
V IH
2.0
3.0
V DD+0.3
V
1
Input logic low voltage
V IL
-0.3
0
0.8
V
2
Output logic high voltage
VO H
2.4
-
-
V
IOH = -2mA
Output logic low voltage
V OL
-
-
0.4
V
IOL = 2mA
ILI
-10
-
10
uA
3
Supply voltage
Input leakage current
Notes : 1. V IH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.
2. V IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.
3. Any input 0V ≤ V IN ≤ V DDQ .
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
4. The VDD condition of K4S561632C-60 is 3.135V~3.6V.
CAPACITANCE
(V DD = 3.3V, T A = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)
Pin
Clock
RAS , CAS, WE, CS, CKE, DQM
Symbol
Min
Max
Unit
Note
C CLK
2.5
4.0
pF
1
C IN
2.5
5.0
pF
2
Address
C ADD
2.5
5.0
pF
2
D Q 0 ~ DQ 15
C OUT
4.0
6.5
pF
3
Notes : 1. -75/7C only specify a maximum value of 3.5pF
2. -75/7C only specify a maximum value of 3.8pF
3. -75/7C only specify a maximum value of 6.0pF
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
DC CHARACTERISTICS
(Recommended operating condition unless otherwise noted, T A = 0 to 70°C)
Parameter
Symbol
Operating current
(One bank active)
Precharge standby current in power-down mode
Precharge standby current in non power-down
mode
Active standby current in
power-down mode
Active standby current in
non power-down mode
(One bank active)
ICC1
ICC2 P
ICC2 PS
ICC2N
ICC2 NS
ICC3 P
ICC3 PS
ICC3N
ICC3 NS
Version
Test Condition
Burst length = 1
tRC ≥ tRC(min)
IO = 0 mA
-60
-7C
-75
-1H
-1L
150
110
100
100
100
CKE ≤ V IL (max), tCC = 10ns
2
CKE & CLK ≤ V IL (max), tCC = ∞
2
CKE ≥ V IH(min), CS ≥ V I H(min), tCC = 10ns
Input signals are changed one time during 20ns
20
Unit
Note
mA
1
mA
mA
CKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞
Input signals are stable
10
CKE ≤ V IL (max), tCC = 10ns
6
CKE & CLK ≤ V IL (max), tCC = ∞
6
CKE ≥ V IH(min), CS ≥ V I H(min), tCC = 10ns
Input signals are changed one time during 20ns
30
mA
CKE ≥ V IH(min), CLK ≤ V IL(max), t CC = ∞
Input signals are stable
25
mA
mA
Operating current
(Burst mode)
ICC4
IO = 0 mA
Page burst
4banks Activated.
tCCD = 2CLKs
180
140
140
130
130
mA
1
Refresh current
ICC5
tRC ≥ tRC(min)
220
220
200
190
190
mA
2
Self refresh current
ICC6
CKE ≤ 0.2V
C
3
mA
3
L
1.5
mA
4
Notes :
1. Measured with outputs open.
2. Refresh period is 64ms.
3. K4S561632D-TC**
4. K4S561632D-TL**
5. Unless otherwise noticed, input swing level is CMOS(V I H/VIL =VDDQ /VSSQ ).
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
AC OPERATING TEST CONDITIONS (V DD = 3.3V ± 0.3V, TA = 0 to 70°C)
Parameter
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Value
Unit
2.4/0.4
V
1.4
V
tr/tf = 1/1
ns
1.4
V
See Fig. 2
3.3V
Vtt = 1.4V
1200Ω
50Ω
V OH (DC) = 2.4V, I O H = -2mA
V OL (DC) = 0.4V, I OL = 2mA
Output
Output
Z0 = 50Ω
50pF
870Ω
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
Notes : 1. The DC/AC Test Output Load of K4S561632C-TC(L)60 is 30pF.
2. The VDD condition of K4S561632C-TC(L)60 is 3.135V~3.6V.
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
Parameter
Version
Symbol
-60
-7C
-75
-1H
-1L
Unit
Note
Row active to row active delay
tRRD(min)
12
15
15
20
20
ns
1
RAS to CAS delay
tRCD(min)
18
15
20
20
20
ns
1
tR P(min)
18
15
20
20
20
ns
1
tRAS (min)
42
45
45
50
50
ns
1
Row precharge time
Row active time
tRAS(max
Row cycle time
tRC(min)
Last data in to row precharge
tRDL (min)
Last data in to Active delay
100
ns
1
2
CLK
2, 5
tDAL (min)
2 CLK + tRP
-
5
Last data in to new col. address delay
tCDL (min)
1
CLK
2
Last data in to burst stop
tBDL (min)
1
CLK
2
Col. address to col. address delay
tCCD(min)
1
CLK
3
ea
4
Number of valid output
data
60
CAS latency=3
CAS latency=2
60
us
65
70
2
-
70
1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
and then rounding off to the next higher integer.
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5.In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
AC CHARACTERISTICS
(AC operating conditions unless otherwise noted)
Parameter
-60
Symbol
Min
CLK cycle
time
CAS latency=3
CLK to valid
output delay
CAS latency=3
Output data
hold time
CAS latency=3
6
tCC
CAS latency=2
-7C
Max
1000
tSAC
CAS latency=2
tOH
CAS latency=2
Min
7.5
-75
Max
1000
7.5
Min
7.5
-1H
Max
1000
10
Min
10
-1L
Max
1000
10
Min
10
Unit
Note
ns
1
ns
1,2
ns
2
Max
1000
12
5
5.4
5.4
6
6
-
5.4
6
6
7
2.5
3
3
3
3
-
3
3
3
3
CLK high pulse width
tCH
2.5
2.5
2.5
3
3
ns
3
CLK low pulse width
tCL
2.5
2.5
2.5
3
3
ns
3
Input setup time
tSS
1.5
1.5
1.5
2
2
ns
3
Input hold time
tSH
1
0.8
0.8
1
1
ns
3
CLK to output in Low-Z
tSLZ
1
1
1
1
1
ns
2
CLK to output
in Hi-Z
CAS latency=3
tSHZ
CAS latency=2
5
5.4
5.4
6
6
-
5.4
6
6
7
ns
Notes : 1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
DQ BUFFER OUTPUT DRIVE CHARACTERISTICS
Parameter
Symbol
Condition
Min
Output rise time
trh
Measure in linear
region : 1.2V ~ 1.8V
Output fall time
tfh
Output rise time
Output fall time
Typ
Max
Unit
Notes
1.37
4.37
Volts/ns
3
Measure in linear
region : 1.2V ~ 1.8V
1.30
3.8
Volts/ns
3
trh
Measure in linear
region : 1.2V ~ 1.8V
2.8
3.9
5.6
Volts/ns
1,2
tfh
Measure in linear
region : 1.2V ~ 1.8V
2.0
2.9
5.0
Volts/ns
1,2
Notes : 1. Rise time specification based on 0pF + 50 Ω to V SS, use these values to design to.
2. Fall time specification based on 0pF + 50 Ω to V DD, use these values to design to.
3. Measured into 50pF only, use these values to characterize to.
4. All measurements done with respect to V SS.
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
IBIS SPECIFICATION
66MHz and 100MHz/133MHz Pull-up
0
I O H Characteristics (Pull-up)
(V)
3.45
3.3
3.0
2.6
2.4
2.0
1.8
1.65
1.5
1.4
1.0
0.0
0.0
-21.1
-34.1
-58.7
-67.3
-73.0
-77.9
-80.8
-88.6
-93.0
100MHz
133MHz
Max
I (mA)
-2.4
-27.3
-74.1
-129.2
-153.3
-197.0
-226.2
-248.0
-269.7
-284.3
-344.5
-502.4
0.5
1
1.5
2
2.5
3
3.5
0
66MHz
Min
-100
I (mA)
-200
-0.7
-7.5
-13.3
-27.5
-35.5
-41.1
-47.9
-52.4
-72.5
-93.0
mA
Voltage
100MHz
133MHz
Min
I (mA)
-300
-400
-500
-600
Voltage
IO H Min (100MHz)
IO H Min (66MHz)
I O H Max (66 and 100MHz)
66MHz and 100MHz/133MHz Pull-down
I O L Characteristics (Pull-down)
(V)
0.0
0.4
0.65
0.85
1.0
1.4
1.5
1.65
1.8
1.95
3.0
3.45
100MHz
133MHz
Min
I (mA)
0.0
27.5
41.8
51.6
58.0
70.7
72.9
75.4
77.0
77.6
80.3
81.4
100MHz
133MHz
Max
I (mA)
0.0
70.2
107.5
133.8
151.2
187.7
194.4
202.5
208.6
212.0
219.6
222.6
250
66MHz
Min
I (mA)
0.0
17.7
26.9
33.3
37.6
46.6
48.0
49.5
50.7
51.5
54.2
54.9
200
150
mA
Voltage
100
50
0
0
0.5
1
1.5
2
2.5
3
3.5
Voltage
IOL Min (100MHz)
IOL Min (66MHz)
I OL Max (100MHz)
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
Minimum VDD clamp current
(Referenced to V DD )
V DD Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
0.0
0.0
0.0
0.0
0.0
0.0
0.0
0.23
1.34
3.02
5.06
7.35
9.83
12.48
15.30
18.31
20
15
mA
V DD (V)
0.0
0.2
0.4
0.6
0.7
0.8
0.9
1.0
1.2
1.4
1.6
1.8
2.0
2.2
2.4
2.6
10
5
0
0
1
2
3
Voltage
I (mA)
Minimum V SS clamp current
V SS Clamp @ CLK, CKE, CS, DQM & DQ
I (mA)
-57.23
-45.77
-38.26
-31.22
-24.58
-18.37
-12.56
-7.57
-3.37
-1.75
-0.58
-0.05
0.0
0.0
0.0
0.0
-3
-2
-1
0
0
-10
-20
mA
V SS (V)
-2.6
-2.4
-2.2
-2.0
-1.8
-1.6
-1.4
-1.2
-1.0
-0.9
-0.8
-0.7
-0.6
-0.4
-0.2
0.0
-30
-40
-50
-60
Voltage
I (mA)
Rev. 0.1 Aug. 2002
K4S561632D
CMOS SDRAM
SIMPLIFIED TRUTH TABLE
Command
Register
Mode register set
Auto refresh
Refresh
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
H
X
L
L
L
L
X
OP code
L
L
L
H
X
X
H
Entry
Self
refresh
Exit
H
H
Bank active & row addr.
H
X
Read &
column address
Auto precharge disable
H
X
Write &
column address
Auto precharge disable
L
H
H
H
H
X
X
X
L
L
H
H
X
V
L
H
L
H
X
V
X
X
L
H
L
L
H
X
X
L
L
H
L
H
H
L
L
X
Exit
Entry
H
L
H
L
H
L
Precharge power down mode
Exit
L
V
Column
address
(A 0 ~ A8 )
L
X
X
All banks
Entry
L
DQM
H
No operation command
H
H
H
X
X
X
L
V
V
V
X
X
X
X
H
X
X
X
L
H
H
H
H
X
X
X
L
V
V
V
X
X
H
X
X
X
L
H
H
H
3
3
Column
address
(A 0 ~ A8 )
H
H
Clock suspend or
active power down
3
Row address
H
H
Note
1,2
X
Auto precharge enable
Bank selection
A 11,A 12,
A9 ~ A 0
3
Auto precharge enable
Burst stop
A 10/AP
L
L
Precharge
BA 0,1
X
V
L
X
H
4
4,5
4
4,5
6
X
X
X
X
X
X
X
V
X
X
X
7
(V=Valid, X=Don't care, H=Logic high, L=Logic low)
Notes : 1. OP Code : Operand code
A 0 ~ A11 & BA 0 ~ BA 1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA 1 : Bank select addresses.
If both BA 0 and BA 1 are "Low" at read, write, row active and precharge, bank A is selected.
If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected.
If BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank C is selected.
If both BA 0 and BA 1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA 0 and BA 1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 0.1 Aug. 2002