K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
Document Title
512K x 8 bit NAND Flash Memory
Revision History
Revision No. History
Draft Date
Remark
Preliminary
Initial issue.
April 10th 1998
1.0
1. Changed Operating Voltage 2.7V ~ 5.5V → 3.0V ~ 5.5V
July 14th 1998
1.1
Data Sheet 1999
1. Added CE don’t care mode during the data-loading and reading
April 10th 1999
1.2
1. Changed device name
- KM29W040AT -> K9F4008W0A-TCB0
- KM29W040AIT -> K9F4008W0A-TIB0
Sep. 15th 1999
1.3
1.Powerup sequence is added
: Recovery time of minimum 1µs is required before internal circuit gets
ready for any command sequences
≈
0.0
~ 2.5V
Jul. 23th 2001
~ 2.5V
High
≈
VCC
WP
1µ
≈
WE
2. AC parameter tCLR(CLE to RE Delay, min 50ns) is added.
3. AC parameter tAR is devided into tAR1, tAR2
ALE to RE Delay
tAR
250
(before revision)
-
ns
(after revision)
ALE to RE Delay(ID Delay)
tAR1
20
-
ns
ALE to RE Delay(Read Cycle)
tAR2
250
-
ns
Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site.
http://www.intl.samsungsemi.com/Memory/Flash/datasheets.html
The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right
to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have
any questions, please contact the SAMSUNG branch office near you.
1
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
512K x 8 Bit NAND Flash Memory
FEATURES
GENERAL DESCRIPTION
• Voltage Supply: 3.0V~5.5V
• Organization
- Memory Cell Array : 512K x 8 bit
- Data Register
: 32 x 8 bit
• Automatic Program and Erase (Typical)
- Frame Program : 32 Byte in 500µs
- Block Erase : 4K Byte in 6ms
• 32-Byte Frame Read Operation
- Random Access : 15µs(Max.)
- Serial Frame Access : 120ns(Min.)
• Command/Address/Data Multiplexed I/O port
• Low Operation Current (Typical)
- 10µA Standby Current
- 10mA Read/ Program/Erase Current
• Reliable CMOS Floating-Gate Technology
- Endurance : 100K Program/Erase Cycles
• Package
- 44(40) - Lead TSOP Type II (400mil / 0.8 mm pitch)
The K9F4008W0A is a 512Kx8bit NAND Flash Memory. Its
NAND cell structure provides the most cost-effective solution
for Digital Audio Recording. A Program operation programs a
32-byte frame in typical 500µs and an Erase operation erase a
4K-byte block in typical 6ms. Data in a frame can be read out at
a burst cycle rate of 120ns/byte. The I/O pins serve as the ports
for address and data input/output as well as for command
inputs. The on-chip write controller automates the program and
erase operations, including program or erase pulse repetition
where required, and performs internal verification of cell data.
PIN CONFIGURATION
PIN DESCRIPTION
The K9F4008W0A is an optimum solution for flash memory
application that do not require the high performance levels or
capacity of larger density flash memories. These application
include data storage in digital Telephone Answering
Devices(TAD) and other consumer applications that require
voice data storage.
Pin Name
I/O0 ~ I/O7
CLE
VSS
CLE
ALE
WE
WP
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O0
I/O1
I/O2
I/O3
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
VCC
CE
RE
R/B
GND
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
N.C
I/O7
I/O6
I/O5
I/O4
VCC
Data Inputs/Outputs
Command Latch Enable
ALE
Address Latch Enable
CE
Chip Enable
RE
Read Enable
WE
Write Enable
WP
Write Protect
GND
Ground Input
R/B
Ready/Busy output
VCC
Power
VSS
Ground
N.C
No Connection
44(40) TSOP (II)
NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.
Do not leave VCC, VSS or GND inputs disconnected.
2
Pin Function
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
Figure 1. FUNCTIONAL BLOCK DIAGRAM
X-Buffers
Latches
& Decoders
A7 - A18
4M Bit
NAND Flash ARRAY
32Byte x 4Frames x 4096Rows
Y-Buffers
Latches
& Decoders
A0 - A6
Page Register & S/A
Y-Gating
Command
Command
Register
CE
RE
WE
I/O Buffers & Latches
Control Logic
& High Voltage
Generator
I/O0
Global Buffers
I/O7
CLE ALE WP
Figure 2. ARRAY ORGANIZATION
Good Block
1Block = 32 Rows
= 4K Bytes
The 1st Block (4KB)
4K Rows
(=128 Blocks)
1
4
3
2
1 Frame = 32 Bytes
1 Row = 4 Frames = 128 Bytes
1 Block = 32 Rows = 4K Bytes
1 Device = 32Bytes x 4Frames x 32Rows x 128Blocks
= 4Mbits
8 bit
128Bytes
I/O0 ~ I/O7
Frame Register
32 Bytes
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
I/O6
I/O7
1st Cycle
A0
A1
A2
A3
A4
A5
A6
A7
2nd Cycle
A8
A9
A10
A11
A12
A13
A14
A15
3rd Cycle
A16
A17
A18
X*
X*
X*
*X
*X
(1)
NOTE : *(1) : X can be VIL or VIH
* The device ignores any additional input of address cycles than reguired.
3
Column Address (A0-A4)
Frame Address (A5-A6)
Row Address (A7-A11)
Block Address (A12-A18)
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
PRODUCT INTRODUCTION
The K9F4008W0A is a 4M bit memory organized as 4096 rows by 1024 columns. A 256-bit data register is connected to memory cell
arrays accommodating data transfer between the registers and the cell array during frame read and frame program operations. The
memory array is composed of unit NAND structures in which 8 cells are connected serially.
Each of the 8 cells reside in a different row. A block consists of the 32 rows, totaling 4096 unit NAND structures of 8bits each. The
array organization is shown in Figure 2. The program and read operations are executed on a frame basis, while the erase operation is
executed on a block basis. The memory array consists of 128 separately erasable 4K-byte blocks.
The K9F4008W0A has addresses multiplexed into 8 I/O pins. This scheme not only reduces pin count but allows systems upgrades to
higher density flash memories by maintaining consistency in system board design. Command, address and data are all written
through I/O′s by bringing WE to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and
Address Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. All commands require one bus
cycle except for Block Erase command which requires two cycles. For byte-level addressing, the 512K byte physical space requires a
19-bit address, low row address and high row address. Frame Read and frame Program require the same three address cycles following by a command input. In the Block Erase operation, however, only the two row address cycles are required.
Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of
the K9F4008W0A.
Table 1. COMMAND SETS
Function
1st. Cycle
2nd. Cycle
Read
00h
-
Reset
FFh
-
Frame Program
80h
10h
Block Erase
60h
D0h
Status read
70h
-
Read ID
90h
-
Caution : Any undefined command inputs are prohibited except for above command set of Table 1.
4
Acceptable Command during Busy
O
O
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
PIN DESCRIPTION
Command Latch Enable(CLE)
The CLE input controls the path activation for commands sent to the command register. When active high, commands are latched
into the command register through the I/O ports on the rising edge of the WE signal.
Address Latch Enable(ALE)
The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of
WE with ALE high.
Chip Enable(CE)
The CE input is the device selection control. When CE goes high during a read operation the device is returned to standby mode.
However, when the device is in the busy state during program or erase, CE high is ignored, and does not return the device to
standby mode.
Write Enable(WE)
The WE input controls writes to the I/O port. Commands, address and data are latched on the rising edge of the WE pulse.
Read Enable(RE)
The RE input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge
of RE which also increments the internal column address counter by one.
I/O Port : I/O0 ~ I/O7
The I/O pins are used to input command, address and data, and to output data during read operations. The I/O pins float to high-z
when the chip is deselected or when the outputs are disabled.
Write Protect(WP)
The WP pin provides inadvertent write/erase protection during power transitions. The internal high voltage generator is reset when
the WP pin is active low.
Ready/Busy(R/B)
The R/B output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is
in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip
is deselected or when outputs are disabled.
5
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
ABSOLUTE MAXIMUM RATINGS
Parameter
Symbol
Rating
Unit
VIN
-0.6 to +7.0
V
Voltage on any pin relative to VSS
Temperature Under Bias
K9F4008W0A-TCB0
-10 to +125
TBIAS
K9F4008W0A-TIB0
°C
-40 to +125
Storage Temperature
TSTG
°C
-65 to +150
NOTE :
1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <20ns.
Maximum DC voltage on input/output pins is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions
as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
RECOMMENDED OPERATING CONDITIONS
(Voltage reference to GND, K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C)
Parameter
Symbol
Min
Typ.
Max
Unit
Supply Voltage
VCC
Supply Voltage
VSS
3.0
-
5.5
V
0
0
0
V
DC AND OPERATING CHARACTERISTICS(Recommended operating conditions otherwise noted.)
Parameter
Operating
Current
Symbol
Test Conditions
tRC=120ns,CE=VIL, IOUT=0mA
Vcc = 3.0V ~ 3.6V
Vcc = 3.6V ~ 5.5V
Min
Typ
Max
Min
Typ
Max
Burst Read Cycle
ICC1
-
5
10
-
10
20
Program
ICC2
-
-
5
10
-
10
20
Erase
ICC3
-
-
5
10
-
10
20
Stand-by Current(TTL)
ISB1
CE=VIH, WP=0V/VCC
-
-
1
-
-
1
Stand-by Current(CMOS)
ISB2
CE=VCC-0.2, WP=0V/VCC
-
10
50
-
10
50
Input Leakage Current
ILI
VIN=0 to 5.5V
-
-
±10
-
-
±10
Output Leakage Current
ILO
VOUT=0 to 5.5V
-
-
±10
-
-
±10
Input High Voltage, All
inputs
VIH
-
2.4
-
2.4
-
Input Low Voltage, All inputs
VIL
-
-0.3
-
0.6
-0.3
-
0.8
Output High Voltage Level
VOH
IOH=-400µA
2.4
-
-
2.4
-
-
Output Low Voltage Level
VOL
IOL=2.1mA
-
-
0.4
-
-
0.4
Output Low Current(R/B)
IOL(R/B)
VOL=0.4V
8
10
-
8
10
-
6
VCC+
0.3
Unit
mA
µA
VCC+
0.5
V
mA
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
VALID BLOCK
Parameter
Valid Block Number
Symbol
Min
Typ.
Max
Unit
NVB
125
-
128
Block
NOTE :
1. The K9F4008W0A may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid
blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase
or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.
2. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not require Error Correction.
AC TEST CONDITION
(K9F4008W0A-TCB0:TA=0 to 70°C, K9F4008W0A-TIB0:TA=-40 to 85°C, VCC=3.0V ~ 5.5V unless otherwise noted)
Value
Parameter
Vcc=3.0V ~ 3.6V
Input Pulse Levels
Vcc=3.6V ~ 5.5V
0.4V to 2.6V
0.4V to 2.6V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL GATE and CL = 100pF
CAPACITANCE(TA=25°C, Vcc=5.0V, f=1.0MHz)
Symbol
Test Condition
Min
Max
Unit
Input / Output Capacitance
Item
CI/O
VIL=0V
-
10
pF
Input Capacitance
CIN
VIN=0V
-
10
pF
NOTE : Capacitance is periodically sampled and not 100% tested.
MODE SELECTION
CLE
ALE
CE
H
L
L
H
H
L
WE
RE
WP
L
H
X
L
H
X
L
L
H
H
H
L
H
H
H
H
Data Input
X
Sequential Read & Data Output
L
L
L
L
L
L
H
Mode
Read Mode
Write Mode
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/VCC(2)
Command Input
Address Input(3clock)
Command Input
Address Input(3clock)
Stand-by
NOTE : 1. X can be VIL or VIH
2. WP should be biased to CMOS high or CMOS low for standby.
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
tPROG
-
0.5
1
ms
Number of Partial Program Cycles in the Same Frame
Nop
-
-
10
cycles
Block Erase Time
tBERS
-
6
10
ms
Program Time
7
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
AC Timing Characteristics for Command / Address / Data Input
Parameter
Symbol
Min
Max
Unit
CLE Set-up Time
tCLS
50
-
ns
CLE Hold Time
tCLH
50
-
ns
CE Setup Time
tCS
50
-
ns
CE Hold Time
tCH
50
-
ns
WE Pulse Width
tWP
60
-
ns
ALE Setup Time
tALS
50
-
ns
ALE Hold Time
tALH
50
-
ns
Data Set-up Time
tDS
40
-
ns
Data Hold Time
tDH
20
-
ns
Write Cycle Time
tWC
120
-
ns
WE High Hold Time
tWH
40
-
ns
AC Characteristics for Operation
Parameter
Symbol
Min
Max
Unit
tR
-
15
µs
ALE to RE Delay(ID Delay)
tAR1
20
-
ns
Data Transfer from Cell to Register
ALE to RE Delay(Read Cycle)
tAR2
250
-
ns
CE low to RE low (ID read)
tCR
250
-
ns
CLE to RE Delay
tCLR
50
-
ns
Ready to RE Low
tRR
100
-
ns
RE Pulse Width
tRP
60
-
ns
WE High to Busy
tWB
-
200
ns
Read Cycle Time
tRC
120
-
ns
RE Access Time
tREA
-
50
ns
RE High to Output Hi-Z
tRHZ
0
30
ns
CE High to Output Hi-Z
tCHZ
-
50
ns
RE High Hold Time
tREH
40
-
ns
tIR
0
-
Output Hi-Z to RE Low
ns
(1)
CE High to Ready(in case of interception by CE at read)
tCRY
-
RE Low to Status Output
tRSTO
-
60
ns
CE Low to Status Output
tCSTO
-
70
ns
WE High to RE Low
tWHR
50
-
ns
tWHRID
100
-
ns
tRST
-
5/10/500
µs
RE access time(Read ID)
Device Resetting Time(Read/Program/Erase)
NOTE : 1. The time to Ready depends on the value of the pull-up resistor tied R/B pin.
8
100+tr(R/B)
ns
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
NAND Flash Technical Notes
Invalid Block(s)
Invalid blocks are defined as blocks that contain one or more invalid bits whose reliability is not guaranteed by Samsung. The information regarding the invalid block(s) is called as the invalid block information. The invalid block information is written to the 1st or the 2nd
page of the invalid block(s) with 00h data. Devices with invalid block(s) have the same quality level or as devices with all valid blocks
and have the same AC and DC characteristics. An invalid block(s) does not affect the performance of valid block(s) because it is isolated from the bit line and the common source line by a select transistor. The system design must be able to mask out the invalid
block(s) via address mapping. The 1st block, which is placed on 00h block address, is fully guaranteed to be a valid block, does not
require Error Correction.
Identifying Invalid Block(s)
All device locations are erased(FFh) except locations where the invalid block information is written prior to shipping. Since the invalid
block information is also erasable in most cases, it is impossible to recover the information once it has been erased. Therefore, the
system must be able to recognize the invalid block(s) based on the original invalid block information and create the invalid block table
via the following suggested flow chart(Figure 1). Any intentional erasure of the original invalid block information is prohibited.
Start
Set Block Address = 0
Increment Block Address
Create (or update)
Invalid Block(s) Table
No
Check "FFh" ?
*
Check "FFh" on the 1st and 2nd page
Yes
No
Last Block ?
Yes
End
Figure 1. Flow chart to create invalid block table.
9
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
K9F4008W0A Technical Notes(Continued)
Error in program or erase operation
Over its life time, the additional invalid blocks may develop with NAND Flash memory. Refer to the qualification report for the actual
data.The following possible failure modes should be considered to implement a highly reliable system. In the case of status read failure after erase or program, block replacement should be done. Because program status fail during a page program does not affect
the data of the other pages in the same block, block replacement can be executed with a page-sized buffer by finding an erased
empty block and reprogramming the current target data and copying the rest of the replaced block. To improve the efficiency of memory space, it is recommended that the read or verification failure due to single bit error be reclaimed by ECC without any block
replacement. The said additional block failure rate does not include those reclaimed blocks.
Failure Mode
Detection and Countermeasure sequence
Block
Erase Failure
Read after Erase --> Block Replacement
Frame
Program Failure
Status Read after Program --> Block Replacement
Single Bit
Program Failure
("1" --> "0")
Block Verify after Program --> Block Replacement
Block Replacement
1st
∼
(n-1)th
nth
{
Block A
2
an error occurs.
(page)
1st
∼
(n-1)th
Buffer memory of the controller.
{
Block B
1
nth
(page)
* Step1
When an error happens in the nth page of the Block ’A’during erase or program operation.
* Step2
Copy the nth page data of the Block ’A’in the buffer memory to the nth page of another free block. (Block ’B’)
* Step3
Then, copy the data in the 1st ~ (n-1)th page to the same location of the Block ’B’.
* Step4
Do not erase or program to Block ’A’by creating an ’invalid Block’table or other appropriate scheme.
During Erase operation ;
When the error occurs after an erase operation, prevent future accesses to this bad block
(again by creating a table within the system or other appropriate scheme.)
10
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
System Interface Using CE don’t-care.
For a easier system interface, CE may be inactive during the data-loading or sequential data-reading as shown below. The internal
32byte page registers are utilized as seperate buffers for this operation and the system design gets more flexible. In addition, for
voice or audio applications which use slow cycle time on the order of u-seconds, de-activating CE during the data-loading and reading would provide significant savings in power consumption.
Figure 3. Program Operation with CE don’t-care.
CLE
CE don’t-care
≈
≈
CE
WE
ALE
I/O0~7
80h
Start Add.(3Cycle)
Data Input
Data Input
10h
(Max. 60ns)
tCS
tCH
tCEA
CE
CE
tREA
RE
tWP
WE
I/O0~7
out
Timing requirements : If CE is is exerted high during sequential
data-reading, the falling edge of CE to valid data(tCEA) must
be kept greater than 60ns.
Figure 4. Read Operation with CE don’t-care.
CLE
CE don’t-care
Must be held
low during tR.
≈
CE
RE
ALE
tR
R/B
WE
I/O0~7
00h
Data Output(sequential)
Start Add.(3Cycle)
11
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
* Command Latch Cycle
CLE
tCLS
tCLH
tCS
tCH
CE
tWP
WE
tALH
tALS
ALE
tDH
tDS
Command
I/O0~7
* Address Latch Cycle
tCLS
CLE
tCS
tWC
tWC
CE
tWP
tWP
tWP
WE
tWH
tWH
tALH
tALS
ALE
tDS
I/O0~7
tDH
A0~A7
12
tDS
tDH
A8~A15
tDS
tDH
A16~A18
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
* Input Data Latch Cycle
tCLH
CLE
tCH
CE
tWC
tALS
tWP
≈
ALE
tWP
tWP
WE
tDS
I/O0~7
tWH
tDH
tDS
tDH
tDS
DIN 31
DIN 1
DIN 0
tDH
* Burst Read Cycle After Frame Access(CLE=L, WE=H, ALE=L)
tRC
tRP
tREA
tRHZ*
tREH
tREA
≈
CE
tREA
RE
tRHZ*
Dout
I/O0~7
Dout
≈
tRHZ
Dout
tRR
R/B
NOTES : Transition is measured±200mV from steady state voltage with load.
This parameter is sampled and not 100% tested.
13
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
* Status Read Cycle
tCLR
CLE
tCLH
tREA
CE
tCH
tWP
WE
tCSTO
tCHZ
tWHR
RE
tDH
tDS
tIR
Status Output
70h
I/O0~7
tRHZ
tRSTO
READ OPERATION(READ ONE FRAME)
CLE
CE
WE
tCHZ
tWB
tAR2
ALE
tR
tRHZ
tRC
≈
RE
I/O0~7
00h
A 0 ~ A7
Column
Address
R/B
A8 ~ A15
Dout N
A16 ~ A18
Row
Address
Busy
14
Dout N+1
Dout N+2
Dout N+3
≈ ≈
tRR
Dout 32
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
READ OPERATION(INTERCEPTED BY CE)
CLE
CE
WE
tWB
tCHZ
tAR2
ALE
tR
RE
tRR
I/O0~7
00h
A0~A7
Column
Address
A16~A18
A8~A15
Dout N
Dout N+1
Dout N+2
Dout N+3
Row
Address
Busy
R/B
PROGRAM OPERATION
CLE
CE
tWC
tWC
≈
tWC
WE
tWB
tPROG
ALE
80h
A0 ~ A7 A8 ~ A15 A16 ~ A18
Sequential Data Column
Input Command Address
Row
Address
Din
Din
N
N+1
1 up to 32 Byte Data
Serial Input
10h
15
70h
I/O0
Read Status
Command
Program
Command
≈
R/B
Din
31
≈
I/O0~7
≈ ≈
RE
I/O0=0 Successful Program
I/O0=1 Error in Program
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
BLOCK ERASE OPERATION
CLE
CE
WE
tWB
tBERS
ALE
RE
I/O0~7
60h
A8~A15
A16~A18
DOh
Busy
R/B
Auto Block Erase Setup Command
Erase Command
16
≈
Block
Address
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
DEVICE OPERATION
FRAME READ
Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also initiated by writing 00h to the command register along with three address cycles. The three cycle address input must be given for
access to each new frame.
The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the data
registers in less than 15µs(tR). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once
the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying
low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address
within the frame(column 32).
Figure 3. Read Operation
CLE
CE
WE
ALE
RE
R/B
I/O0~7
Busy(Seek Time)
00h
Start Add.(3Cycle)
Data Output(Sequential)
A0~A7 & A8~A18
Seek Time
0
31
17
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
FRAME PROGRAM
The device is programmed on a frame basis. The addressing may be done in random order in a block. A frame program cycle consist
of a serial data loading period in which up to 32 bytes of data must be loaded into the device, and a nonvolatile programming period
in which the loaded data is programmed into the appropriate cells.
The sequential data loading period begins by inputting the frame program setup command(80h), followed by the three cycle address
input and then sequential data loading. The bytes other than those to be programmed do not need to be loaded.
The frame Program confirm command(10h) initiates the programming process. Writing 10h alone without previously entering the
serial data will not initiate the programming process. The internal write controller automatically executes the algorithms and timings
necessary for program and verify, thereby freeing the CPU for other tasks. The CPU can detect the completion of a program cycle by
monitoring the R/B output, or the Status bit(I/O6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the frame Program is complete, the Write Status Bit(I/O0) may be checked. The internal
write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in Read Status
command mode until another valid command is written to the command register.
Figure 4. Frame Program Operation
tPROG
R/B
I/O0~7
Address & Data Input
80h
10h
A0~A7 & A8~A18
32 Byte Data
FRAME PROGRAM
While the frame size of the device is 32 Bytes, not all the bytes in a frame have to be programmed at once. The device supports partial frame programming in which a frame may be partially programmed up to 10 separate program operations. The program size in
each of the 10 partial program operations is freely determined by the user and do not have to be equal to each other or to any preset
size. However, the user should ensure that the partial program units within a frame do not overlap as "0" data cannot be changed to
"1" data without an erase operation. To perform a partial frame program operation, the user only writes the partial frame data that is
to programmed. Just as in the standard frame program operation, an 80h command is followed by start address data. However, only
the partial program data need be divided when programming a frame in 10 partial program operations.
Figure 5. Example of Dividing a Frame into 10 Partial Program Units
1st partial program start address (00h)
2nd partial program start address (04h)
3rd partial program start address (06h)
:
:
:
:
:
:
9th partial program start address (18h)
10th partial program start address (1Fh)
FA
A2
43
CB
81
28
E0
2A
D5
- - - - - - 32
B5
7D
6F
AA
E1
D7
C0
Single
Frame
10th partial frame program data
9th partial frame program data
:
:
:
:
:
:
3rd partial frame program data
2nd partial frame program data
1st partial frame program data
18
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
BLOCK ERASE
The Erase operation is done 4K Bytes(1 block) at a time. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A12 to A18 are valid while A8 to A11 is ignored. The Erase Confirm command(D0h) following the
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase, erase-verify and pulse
repetition where required.
Figure 6. Block Erase Operation
tBERS
R/B
I/O0~7
60h
Address Input(2Cycle)
D0h
Block Add. : A8~A18
READ STATUS
The device contains a Status Register which may be read to find out whether program or erase operation is complete, and whether
the program or erase operation completed successfully. After writing 70h command to the command register, a read cycle outputs the
contents of the Status Register to the I/O pins on the falling edge of CE or RE, whichever occurs last. This two line control allows the
system to poll the progress of each device in multiple memory connections even when R/B pins are common-wired. RE or CE does
not need to be toggled for updated status. Refer to table 2 for specific Status Register definitions. The command register remains in
Status Read mode until further commands are issued to it. Therefore, if the status register is read during a random read cycle, the
required read command(00h) should be input before serial page read cycle.
Table2. Read Status Register Definition
I/O #
Status
I/O0
Program
Definition
"0" : Successful Program
"1" : Error in Program
I/O1
"0"
I/O2
"0"
I/O3
Reserved for Future Use
I/O4
"0"
"0"
"0"
I/O5
"0"
I/O6
Device Operation
I/O7
Write Protect
19
"0" : Busy
"1" : Ready
"0" : Protected
"1" : Not Protected
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
RESET
The device offers a reset feature, executed by writing FFh to the command register. When the device is in Busy state during the
read, program or erase mode, the reset operation will abort these operation. In the case of Reset during Program or Erase operations,
the contents of memory cells being altered are no longer valid, as the data will be partially programmed or erased. The device enters
the Read mode after completion of Reset operation as shown Table 3. If the device is already in reset state a new reset command will
not be accepted to by the command register. The R/B pin transitions to low for tRST after the Reset command is written. Reset command is not necessarily for normal device operation. Refer to Figure 7 below.
Figure 7. RESET Operation
tRST
R/B
I/O0~7
FFh
Table3. Device Status
Operation Mode
After Power-up
After Reset
Read
Read
20
K9F4008W0A-TCB0, K9F4008W0A-TIB0
FLASH MEMORY
Figure 9. Read ID Operation
tCLR
CLE
tCEA
CE
tWHR
WE
tAR1
ALE
RE
I/O0~7
tREA
90h
Add. Input(1Cycle)
A0~A7:"0"
21
Dout(ECh)
Dout(A4H)
Maker code
Device code
Package Dimensions
FLASH MEMORY
READY/BUSY
The device has a R/B output that provides a hardware method of indicating the completion of a frame program, erase or read seek
completion. The R/B pin is normally high but transitions to low after program or erase command is written to the command register or
a random read is begin after address loading. It returns to high when the internal controller has finished the operation. The pin is an
open-drain driver thereby allowing two or more R/B outputs to be Or-tied. Because pull-up resistor value is related to tr(R/B) and current drain during busy(ibusy) , an appropriate value can be obtained with the following reference chart(Fig 10). Its value can be
determined by the following guidance.
Rp
ibusy
VCC
Ready Vcc
R/B
open drain output
2.0V
0.8V
Busy
tf
tr
GND
Device
Fig 10 Rp vs tr ,tf & Rp vs ibusy
@ Vcc = 3.3V, Ta = 25°C , CL = 100pF
tr,tf [s]
Ibusy
300n
200n
290
3m
1.65
189
1.1
2m
4.2
4.2
4.2
2K
3K
Rp(ohm)
4K
tr
96
100n
4.2
0.825
tf
1K
Rp value guidance
Rp(min) =
3.2V
VCC(Max.) - VOL(Max.)
IOL + ΣIL
=
8mA + ΣIL
where IL is the sum of the input currents of all devices tied to the R/B pin.
Rp(max) is determined by maximum permissible limit of tr
22
1m
Ibusy [A]
381
3.3
Package Dimensions
FLASH MEMORY
DATA PROTECTTION
The device is designed to offer protection from any involuntary program/erase during power-transitions. An internal voltage detector
disables all functions whenever Vcc is below about 2V. WP pin provides hardware protection and is recommended to be kept at VIL
during power-up and power-down and recovery time of minimum 1µs is required before internal circuit gets ready for any command
sequences as shown in Figure 11. The two step command sequence for program/erase provides additional software protection.
≈
Figure 11. AC Waveforms for Power Transition
~ 2.5V
~ 2.5V
High
≈
VCC
≈
WP
WE
≈
10µs
23
Package Dimensions
FLASH MEMORY
PACKAGE DIMENSIONS
44(40) LEAD PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(II)
44(40) - TSOP2 - 400F
Unit :mm/Inch
0~8°
0.25
TYP
0.010
#23(21)
#1
10.16
0.400
11.76±0.20
0.463±0.008
0.45~0.75
0.018~0.030
#44(40)
0.50
0.020
#22(20)
+0.10
0.15 -0.05
1.00±0.10
0.039±0.004
18.81
Max.
0.741
18.41±0.10
0.725±0.004
1.20
Max.
0.047
+0.004
0.006 -0.002
(
0.805
)
0.032
0.35±0.10
0.014±0.004
0.05
Min.
0.002
0.10
MAX
0.004
0.80
0.0315
24