JAN. 2000
Ver 0.1
DATA SHEET
KB2514
Preliminary
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
VIDEO AMP MERGED OSD PROCESSOR
32-DIP-600A
The KB2514 is a very high frequency video amplifier &
wide range OSD processor 1 chip system with I2C Bus
control used in monitors. It contains 3 matched R/G/B video
amplifiers with OSD processor and provides flexible
interfacing to I2C Bus controlled adjustment systems.
FUNCTIONS
•
R/G/B video amplifier
•
OSD processor
•
I2C bus control
•
Cut-off brightness control
•
R/G/B sub contrast/cut-off control
•
Half tone
ORDERING INFORMATION
Device
Package
Operating Temperature
KB2514
32-DIP-600A
-20 °C − +75 °C
FEATURES
VIDEO AMP PART
OSD PART
•
3-channel R/G/B video amplifier, 150MHz @f-3dB
•
Built in 1K-byte SRAM
•
I2C bus control items
- Contrast control: -38dB
- Sub contrast control for each channel: -12dB
- Brightness control
- OSD contrast control: -38dB
- Cut-off brightness control (AC coupling)
- Cut-off control for each channel (AC coupling)
- Switch registers for SBLK and video half tone and
CLP/BLK polarity selection and INT/EXT CLP selection
•
256 ROM fonts (each font consists of 12 × 18
dots.)
•
Full screen memory architecture
•
Wide range PLL available (15kHz ~ 90kHz,
Reference 800 X 600)
•
Programmable vertical height of character
•
Programmable vertical and horizontal
positioning
•
Built in ABL (automatic beam limitation)
•
•
Built in video input clamp, BRT clamp
Character color selection up to 16 different
colors (in a units of character)
•
Built in video half tone (3mode) function on OSD
pictures
•
Programmable background color (up to 16
colors)
•
Capable of 8.0Vp-p output swing
•
Character blinking and shadowing
•
Improvement of rise & fall time (2.2ns)
•
Character scrolling
•
Cut-off brightness control
•
•
Built in blank gate with spot killer
72MHz pixel frequency from on-chip PLL
(Reference 800 X 600)
•
Clamp pulse generator
•
Full white pattern generation function
•
OSD intensity
•
BLK, CLP polarity selection
•
Clamp gate with anti OSD sagging
1
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
BLOCK DIAGRAM
9
VDD 31
ROM
(448 x 18 x 12)
Font Data
VREF1
Data Receiver
Ctrl Data
Frame Ctrl
ROM Ctrl
4
R/G/B OSD H/V/CLK Ctrl H/V/CLK Ctrl
FBLK
Intensity
Timing Controller Frame Ctrl
5
Latches
ABL
8
CONT_CAP
7
VFLB
3
VCO_IN_P
30 SDA
2
I C bus
decoder D/A
RGB OSD
FBL
BLK
BLK
Int
INTE
HT DET.
CLP
1
Control
Register
ROM Ctrl
VREF
OSD
PLL
V_Pulse
9
Multi (3 mode)
Half Tone
VSSA
32 HFLB
H_Pulse
Display
Display Ctrl Controller
Band
Gap.Ref
2
16
CLK
Output Stage
VDDA
RAM Data
12
VCC3 11
GND3
ROM
(480 x 16)
ROM
Address
Ctrl Font
VSS 28
6
16
Clamp
Pulse
Gen.
29 SCL
R cut off
V/I
27 RCT
G cut off
V/I
26 GCT
B cut off
V/I
25 BCT
HFLB
ABL
10 CLP_IN
Video
Input
Clamp
RIN 12
Video
Half Tone
SW
CLP
GND1 15
R OSD
FBLK
OSD
Input
Cilp.
Sub
Cont.
Control
I2C
OSD
Half Tone
SW
HT DET.
FBLK
Video
Contrast
Amp
Out
I2C
OSD
Cont.
Control
I2C
Sub
Cont.
Control
+
24 R OUT
BLK
Birght
Control
I2C Cont. Cntl
I2C
I2C
CLP
VCC1 13
GIN 14
22 VCC2
23 R CLP
19 GND2
20 G CLP
G-CHANNEL
21 G OUT
G OSD
CLP
HT DET.
I2C
FBLK
CLP
BLK
17 B CLP
BIN 16
B-CHANNEL
18 B OUT
B OSD
CLP
HT DET.
FBLK
I2C
Figure 1. Functional Block Diagram
2
CLP
BLK
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
PIN CONFIGURATION
VFLB
HFLB 32
2
VSSA
VDD 31
3
VCO_IN_P
SDA 30
4
VREF1
SCL 29
5
VREF
VSS 28
6
VDDA
RCT 27
7
CONT_CAP
GCT 26
8
ABL_IN
9
GND3
KB2514
KB2502
1
BCT 25
ROUT 24
10 CLP_IN
RCLP 23
11 VCC3
VCC2 22
12 RIN
GOUT 21
13 VCC1
GCLP 20
14 GIN
GND2 19
15 GND1
BOUT 18
16 BIN
BCLP 17
Figure 2. Pin Configuration
3
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 1. Pin Configuration
4
Pin No.
Symbol
I/O
Configuration
1
VFLB
I
Vertical flyback signal
2
VSSA
-
Ground (PLL part)
3
VCO_IN_P
I
This voltage is generated at the external loop filter and goes into the
input stage of the VCO.
4
VREF1
O
Charge pump output
5
VREF
O
PLL regulator filter
6
VDDA
-
+5V supply voltage for PLL part
7
CONT_CAP
-
Contrast control for AMP part
8
ABL
-
Auto beam limit.
9
GND3
-
Ground for video AMP part(for AMP control)
10
CLP_IN
-
Video clamp pulse input
11
VCC3
-
+12V supply voltage for video AMP part(for AMP control)
12
RIN
I
Video signal input (red)
13
VCC1
-
+12V supply voltage for video AMP(for main video signal process)
14
GIN
I
Video signal input (green)
15
GND1
-
Ground for video AMP part(for main video signal process)
16
BIN
I
Video signal input (blue)
17
BCLP
-
B output clamp cap
18
BOUT
O
Video signal output (blue)
19
GND2
-
Ground for video AMP part(for video output drive)
20
GCLP
-
G output clamp cap
21
GOUT
O
Video signal output (green)
22
VCC2
-
+12V supply voltage for video AMP part(for video output drive)
23
RCLP
-
R output clamp cap
24
ROUT
O
Video signal output (red)
25
BCT
-
B cut-off output
26
GCT
-
G cut-off output
27
RCT
-
R cut-off output
28
VSS
-
Ground for digital part
29
SCL
I
Serial clock (I2C)
30
SDA
I/O
Serial data (I2C)
31
VDD
-
+5V supply voltage for digital part
32
HFLB
I
Horizontal flyback signal
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
PIN DESCRIPTION
Table 2. Pin Description
Pin No
Pin Name
1
VFLB
Schematic
Description
FLB signal is in TTL level
VFLB
HFLB
32
HFLB
Multi polarity input
3
VCO_IN_P
PLL loop filter output
4
VPEF1
BandGap ref. output
5
VREF
7
Contrast cap
(CONT_CAP)
Contrast cap range
(0.1uF ~ 5uF)
4.0K
I2C Data
Vref
100µA
8
ABL_IN
ABL input DC range
(1 ~ 4.5V)
VCC
100K
2K
Vref
Vref
250µA
5
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 2. Pin Description (Continued)
Pin No
Pin Name
10
CLP_IN
Schematic
Description
Multi polarity input
VCC
50K
Clamp gate pulse TTL level
input
10K
12
Red video input
(RIN)
Max input video signal is 0.7
Vpp
VCC
VCC
14
Green video input
(GIN)
16
Blue video input
(BIN)
Video_In
0.2K
12K
17
Blue (B clamp cap)
20
Green (G clamp cap)
Brightness controlling actives by
charging and discharging of the
external cap. (0.1µF)
(During clamp gate)
0.2K
CLP
23
6
Red (R clamp)
0.2K
Iclamp
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 2. Pin Description (Continued)
Pin No
Pin Name
18
Blue video output
(BOUT)
Schematic
Description
Video signal output
VCC
0.05K
21
Green video output
(GOUT)
0.5K
0.04K
24
Red video output
(ROUT)
27
Red cut-off control
(RCT)
26
Video_Out
Isink
Cut-off control output
0.2K
CTX
Green cut-off control
(GCT)
0-600uA 0-200uA 50uA
25
Blue cut-off control
(BCT)
29
SCL
100uA
Serial clock input port of I2C bus
SCL
30
Serial data input port of I2C bus
SDA
SDA
SCL
ACK
7
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
ABSOLUTE MAXIMUM RATINGS (see 1)
(Ta = 25 °C)
Table 3. Absolute Maximum Ratings
No
1
Item
Value
Symbol
Maximum supply voltage
Unit
Min
Typ
Max
VCC
-
-
13.2
VDD
-
-
6.5
-
75
°C
150
°C
2
Operating temperature (see 2)
Topr
-20
3
Storage temperature
Tstg
-65
4
Operating supply voltage
VCCop
11.4
12.0
12.6
VDDop
4.75
5.00
5.25
PD
-
-
5
Power dissipation
V
V (see 3)
W
THERMAL & ESD PARAMETER
Table 4. Thermal & ESD Parameter
Value
No
8
Item
Symbol
Min
Typ
Max
Unit
1
Thermal resistance
(junction-ambient)
θja
-
48
-
°C/W
2
Junction temperature
Tj
-
150
-
°C
3
Human body model
(C = 100p, R = 1.5k)
HBM
2
-
-
KV
4
Machine model
(C = 200p, R = 0)
MM
300
-
-
V
5
Charge device model
CDM
800
-
-
V
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
ELECTRICAL CHARACTERISTICS
DC ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = VDDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors =
470Ω, except OSD part current 35mA, unless otherwise stated)
Table 5. DC Electrical Characteristics
Value
Parameter
Supply current
Symbol
Conditions
ICC (see 4)
Unit
Min
Typ
Max
100
125
130
mA
Minimum supply current
ICC min
VCC = 11.4V
95
110
120
mA
Maximum supply current
ICC max
VCC = 12.6V
105
130
140
mA
ABS supply current
ICC abs
VCC = 13.2V
-
-
175
mA
Video input bias voltage
V bias
1.8
2.1
2.4
V
V blackpor
1.20
1.50
1.80
V
∆ V blackpor
∆ 10
-
-
%
2.2
2.7
3.2
V
∆ 10
-
-
%
-
0.2
0.5
V
∆ 10
-
-
%
Video black level voltage (POR)
Black level voltage channel difference (POR)
(see 5)
Video black level voltage (FFH)
V blackff
Black level voltage channel difference (FFH)
∆ V blackff
Video black level voltage (00H)
V black00
Black level voltage channel difference (00H)
04 = FFH (see 13)
04 = 00H
∆ V black00
Spot killer voltage
Vspot
VCC = Var.
9.20
10.4
11.2
V
Cut-off current (FFH)
ICTff
Pin25, 26, 27 = 12V
09 ~ 0B: FFH
0C: 00H
500
625
750
µA
Cut-off current (00H)
ICT00
Pin25, 26, 27 = 12V
09 ~ 0C: 00H
-
2.0
5.0
µA
Cut-off brightness current (FFH)
ICTBRTff
Pin25, 26, 27 = 12V
09 ~ 0B: 00H
0C: FFH
100
180
260
µA
Cut-off brightness current (80H)
ICTBRT80
Pin25, 26, 27 = 12V
09 ~ 0B: 00H
0C: 80H
50
90
130
µA
ICS1
Pin25, 26, 27 = 12V
09 ~ 0C: 00H
0E: 11H
25
50
75
µA
Cut-off offset current 1
9
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 5. DC Electrical Characteristics(Continued)
Value
Parameter
Symbol
Conditions
Cut-off offset current 2
ICS2
Pin25, 26, 27 = 12V
09 ~ 0C: 00H
0E: 12H
Soft BLK output voltage
Vsblk
0D: 80H
0E: 14H
Clamp cap voltage (POR)
Vcap
Total external cut-off current range
Red
cut-off
Creen
cut-off
Blue
cut-off
Cut-Off Brightness
600uA
200uA
CS2
Cut-Off Offset
Switch
10
100uA
CS1
50uA
150uA
Unit
Min
Typ
Max
50
100
130
µA
-
0.2
0.5
V
6.0
7.0
8.0
V
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
AC ELECTRICAL CHARACTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = VDDA = 5V, ABL input voltage = 5V, HFLB input signal = S3, load resistors =
470Ω, Vin = 0.7Vpp manually adjust video output pins 18, 21 and 24 to 4V DC for the AC test (see 11) unless
otherwise stated (see 12))
Table 6. AC Electrical Characteristics
Value
Parameter
Contrast max. output voltage
Symbol
Vcff
Contrast max. output channel difference
∆ Vcff
Contrast center output voltage
Vc80
Conditions
03, 05, 06, 07 = FFH
04, 08 ~ 0C = 80H
RGB input = S1
Unit
Min
Typ
Max
5.0
5.7
6.4
Vpp
∆ 10
-
-
%
2.5
2.85
3.2
Vpp
∆ Vc80
03, 04, 08 ~ 0C = 80H
05, 06, 07 = FFH
RGB input = S1
∆ 10
-
-
%
Contrast max. - Center attenuation
C
C = 20log (Vc80/Vcff)
-8
-6
-4
dB
Sub contrast center output voltage
Vd80
2.3
2.6
2.9
Vpp
Sub contrast center output channel
difference
∆ Vd80
03 = FFH
04 ~ 0C = 80H
RGB input = S1
∆ 10
-
-
%
Contrast center output channel difference
Sub contrast min. output voltage
Sub contrast min. output channel difference
Sub contrast max. - min. attenuation
ABL control range
Vd00
∆ Vd00
D
ABL
03 = FFH, 05 ~ 07: 00H
04, 08 ~ 0C = 80H
RGB input = S1
1.3
1.6
1.9
Vpp
∆ 10
-
-
%
D = 20log (Vd00/Vcff)
-14
-12
-10
dB
(see 15)
-12
-10
-8
dB
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
RGB input = S2
-
2.2
2.8
ns
-
2.2
2.8
ns
POR
HFLB: S4
-
6.0
12.0
ns
-
8.0
15.0
ns
R/G/B video rising time (see 7)
tr (video)
R/G/B video falling time (see 7)
tf (video)
R/G/B blank output rising time (see 7)
tr (blank)
R/G/B blank output falling time (see 7)
tf (blank)
R/G/B video band width (see 7, 8)
f (-3dB)
(see 16)
150
-
-
MHz
Video AMP 50MHz cross talk
CT_50M
(see 17)
-
-25
-20
dB
(see 18)
-
-15
-10
dB
(see7, 9)
Video AMP 130MHz cross talk
CT_130M
(see7, 9)
Absolute gain match
Avmatch (see 6)
-1
-
1
dB
Gain change between amplifier
Avtrack (see 7)
-1
-
1
dB
11
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
OSD ELECTRICAL CHARCTERISTICS
(Tamb = 25 °C, VCC = 12V, VDD = VDDA = 5V, HFLB input voltage = S3, load rosistors = 470Ω, V-AMP test
registor’s FBLK, OSD input conditions unless otherwise stated)
Table 7. OSD Electrical Chaacteristics
Value
Parameter
Symbol
OSD contrast max. output voltage
Vocff
OSD contrast max. output channel
difference
∆ Vocff
OSD contrast center output voltage
Voc80
OSD contrast center output channel
difference
∆ Voc80
R/G/B OSD rising time
tr (OSD)
R/G/B OSD falling time
tf (OSD)
HT video level
HTvideo
HT video output channel difference
HT OSD level
HT OSD output channel difference
12
∆ HTvideo
HTosd
∆ HTosd
Conditions
08 = FFH
OSD RGB output conditions
08 = 80H
OSD RGB output conditions
08: FFH
ABL = 6V
RGB input = S1
03, 05 ~ 08: FFH
0D: 01H
OSD black conditions input
HTvideo = 20log(Vhtvideo/Vcff)
ABL = 6V
05 ~ 08: FFH
0D: 0FH
OSD white condition input
HTosd = 20log (Vhtosd/Vocff)
Unit
Min
Typ
Max
5.4
6.4
7.4
Vpp
∆ 10
-
-
%
2.7
3.2
3.7
Vpp
∆ 10
-
-
%
-
4.0
5.0
ns
-
4.0
5.0
ns
-6.0
-4.5
-3.0
dB
∆ 15
-
-
%
-7.0
-5.5
-4.0
dB
∆ 15
-
-
%
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
OPERATION TIMINGS
Table 8. Operation Timings
Parameter
Symbol
Min
Typ
Max
Unit
Horizontal flyback signal frequency
fHFLB
-
-
120
kHz
Vertical flyback signal frequency
fVFLB
-
-
200
Hz
fSCL
-
-
300
kHz
Hold time for start condition
ths
500
-
-
ns
Set up time for stop condition
tsus
500
-
-
ns
Low duration of clock
tlow
400
-
-
ns
High duration of clock
thigh
400
-
-
ns
Hold time for data
thd
0
-
-
ns
Set up time for data
tsud
500
-
-
ns
Time between 2 access
tss
500
-
-
ns
Fall time of SDA
tfSDA
-
-
20
ns
Rise time of both SCL and SDA
trSDA
-
-
-
ns
Input Signal HFLB, VFLB
2
I C Interface SDA, SCL (Refer to Figure 3)
SCL clock frequency
tss
thd
SDA
ths
tsud
SCL
tsus
thigh
tlow
Figure 3. I2C Bus Timing Diagram
13
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
OSD PART ELECTRICAL CHARACTERISTICS
OSD PART DC ELECTRICAL CHARACTERISTICS
(Ta = 25 °C, VDDA = VDD = 5V)
Table 9. OSD Part DC Electrical Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Supply voltage
VDD
4.75
5.00
5.25
V
Supply current
(no load on any output)
IDD
-
-
25
mA
Input voltage
VIH
0.8VDD
-
-
V
VIL
-
-
VSS + 0.4
V
VOH
0.8VDD
-
-
V
VOL
-
-
VSS + 0.4
V
IIL
-10
-
10
µA
Output voltage
(lout = ±1mA)
Input leakage current
VCO input voltage
14
VVCO
2.5
V
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
NOTES:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
Absolute maximum rating indicates the limit beyond which damage to the device may occur.
Operating ratings indicate conditions for which the device is functional but do not guarantee specific performance limits.
For guaranteed specifications and test conditions, see the electrical characteristics. The guaranteed specifications appl
y
only for the test conditions listed. Some performance characteristics may degrade when the device is not operated under
the listed test conditions.
VCC supply pins 11, 13, and 22 must be externally wired together to prevent internal damage during VCC power on/off
cycles.
The supply current specified is the quiescent current for VCC1/VCC2 and VCC3 with RL = ∞, The supply current
for VCC2 (pin 22) also depends on the output load.
Output voltage is dependent on load resistor. Test circuit uses RL = 470Ω
Measure gain difference between any two amplifiers Vin = 700mVpp.
When measuring video amplifier bandwidth or pulse rise and fall times, a double sided full ground plane printed circuit
board without socket is recommended. Video amplifier 50MHz cross talk test also requires this printed circuit board. The
reason for a double sided full ground plane PCB is that large measurement variations occur in single sided PCBs.
Adjust input frequency from 10MHz (AV max reference level) to the -3dB frequency (f -3dB).
Measure output levels of the other two undriven amplifiers relative to the driven amplifier to determine channel separation.
Terminate the undriven amplifier inputs to simulate generator loading. Repeat test at fin = 50MHz for cross talk 50MHz.
A minimum pulse width of 200 ns is guaranteed for a horizontal line of 15kHz. This limit is guaranteed by design. if a lower
line rate is used a longer clamp pulse may be required.
During the AC test the 4V DC level is the center voltage of the AC output signal. For example. If the output is 4Vpp the
signal will swing between 2V DC and 6V DC.
These parameters are not tested on each product which is controlled by an internal qualification procedure.
The conditions block’s 03, 04, 05... etc. signify sub address’0F03, 0F04, 0F05... etc.
Sub address 0F03, 0F05 ~ 0F07: FFH
0F04, 0F08 ~ 0F0C: 80H
RGB input = S1,
When the ABL input voltage is 0V, the R/G/B’s output voltage is VR/VG/VB and uses the formula ABLR = 20log (VR/V
cffR)
OSD TST mode = High, CLP operation off,
RGB input = S5 (frequency sweep),
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
S5’s frequency 1MHz → 130MHz sweep, -3dB point = 20log (V130MHz/V1MHz)
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
OSD TST mode = High, CLP operation off,
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
R input = S5 (50MHz)
CT_50M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR)
OSD TST mode = High, CLP operation off,
RGB input clamp cap = 2.1V DC,
RGB clamp cap (pin 23/20/17) = Vcap voltage (7.0V),
03, 05 ~ 07: FFH
04, 08 ~ 0C: 80H
0F: 80H
R input = S5 (130MHz)
CT_150M = 20log (VoutG/VoutR) or 20log (VoutB/VoutR)
15
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
TEST SIGNAL FORMAT
Table 10. Test Signal Format
Signal
Name
Input Signal Formal
Signal Description
S1
Video gain measurement
Video
[V]
Video = 1MHz/0.7Vpp
Sync = 50kHz
Sync
4uS
[t]
S2
Video Tr/Tf measurement
[V]
0.7
Vpp
f = 200kHz
f = 200kHz
V = 0.7Vpp
Duty = 50%
[t]
Duty = 50%
S3
HFLB (posi & nega.) input
[V]
f = 50kHz
t = 2uS
V = 0V/5V
t = 2uS
[t]
f = 50kHz
S4
OSD level measurement
[V]
f = 200kHz
5V
Blank Tr/Tf measurement
0V
f = 50kHz
V = 0V/5V
[t]
Duty = 50%
S5
Crosstalk test
[V]
Bandwidth measurement
Vi
Vref
1MHz/10MHz/50MHz/
130MHz
[t]
Vref = input clamp voltage
Vi = 0.7Vpp
•
S1, S2 signal’s low level must be synchronized with the S3 signal’s sync. term.
•
The input signal level uses the IC pin as reference.
16
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
TEST CIRCUIT
VDD = 5.0V
33
BNC1
33
1
VFLB
HFLB 32
2
VSSA
VDD 31
3
VCO_IN_P
SDA 30
33
BNC3
BNC2
5.6K 10uF
100u
1
1MΩ
2 SW1
33pF
33
4.7K
33
4.7K
BNC5
4
VREF1
SCL 29
5
VREF
VSS 28
6
VDDA
RCT 27
7
CONT_CAP
GCT 26
8
ABL_IN
BCT 25
9
GND3
ROUT 24
10
CLP_IN
RCLP 23
11
VCC3
VCC2 22
12
RIN
GOUT 21
13
VCC1
GCLP 20
14
GIN
GND2 19
15
GND1
BOUT 18
16
BIN
BCLP 17
27K
BNC5
2K
1u
2K
100u
100
2K
ABL
KB2514
1u
33
470
0.1u
BNC6
100u
75
0.1u
470
100u
BNC7
75
0.1u
0.1u
470
BNC8
75
0.1u
0.1u
BNC9
Magnetic core
VSS = 12.0V
Figure 4. Test Circuit
17
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
FUNCTIONAL DESCRIPTIONS
DATA TRANSMISSION
The interface between KB2514 and MCU follows the I2C protocol. After the starting pulse, the transmission takes
place in the following order: Slave address with R/W bit, 2-byte register address, 2-byte data, and stop condition.
an acknowledge signal is received for each byte, excluding only the start/stop condition. The 2-byte register
address is composed of an 8-bit row address, and an 8-bit column address. The order of transmission for a 2-byte
register address is 'Row address → Column address'. The 2 bytes of data is because KB2514 has a 16-bit base
register configuration. KB2514's slave address is BAh. It is BBh in read mode, and BAh in write mode.
•
Address Bit Pattern for Display Registers Data
(a) row address bit pattern
R3 - R0: Valid data for row address
A15
A14
A13
A12
A11
A10
A9
A8
X
X
X
X
R3
R2
R1
R0
(b) Column address bit pattern
C4 - C0: Valid data for column address
A7
A6
A5
A4
A3
A2
A1
A0
X
X
X
C4
C3
C2
C1
C0
X:Don't care bit
•
Data Transmission Format
Start → Slave address → ACK → Row address → ACK → Column address → ACK
Data byte N → ACK → Data byte N+1 → ACK → Stop
Figure 5. Data Transmission Format at Writing Operation
Start → Slave address → ACK → Row address → ACK → Column address → ACK → Stop
Start → Slave address → ACK → Data byte N → ACK → Data byte N+1 → ACK → Stop
Figure 6. Data Transmission Format at Reading Operation
18
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
•
KB2514
SDA / SCL Signal At Communication
SCL
R/W
SDA
START
IIC SLAVE ADDRESS
A15 A14 A13 A12 A11 A10 A9
ACK
A8
A7
MSB ADDRESS
A6
A5
ACK
A4
A3
A2
A1
A0
LSB ADDRESS
ACK
SCL
...
SDA
D7
D6
D5 D4 D3 D2 D1
DATA BYTE N(MSB DATA)
D0
D7
ACK
D6
D5 D4 D3 D2 D1
DATA BYTE N(LSB DATA)
D0
D7
D6
ACK
D5 D4 D3 D2 D1 D0
DATA BYTE N(MSB DATA)
ACK
...
STOP
Figure 7. SDA line and SCL line (Write Operation)
SCL
R/W
SDA
START
IIC SLAVE ADDRESS
START
IIC SLAVE ADDRESS
A15 A14 A13 A12 A11 A10 A9
ACK
A8
MSB ADDRESS
A7
A6
A5
ACK
A4
A3
A2
A1
A0
LSB ADDRESS
ACK
STOP
SCL
SDA
D15 D14 D13 D12 D11 D10
R/W
ACK
D9
DATA BYTE N(MSB)
D7
D8
D6
D5
ACK
D4
D3
D2
D1
DATA BYTE N(LSB)
D0
ACK STOP
Figure 8. SDA line and SCL line (Read Operation)
19
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
MEMORY MAP
27 2829
00 01 02
Row 00
Row 01
Character & Attribute Registers [Display RAM]
(30 x15 Character Display)
Row 12
Row 13
Row 14
Frame Control Registers
Row 15
00 01 02 03
Row 16
Video-AMP Control Registers
0001 02 03 04 05
Figure 9. Memory Map of Display Registers
The display RAM's address of the row and column number are assigned in order. The display RAM is composed of
3 register groups (character & attribute register, frame control register and V-AMP control register).
The display area in the monitor screen is 30 column × 15 row, so the related character & attribute registers are also
30 column × 15 row. Each register has a character address and characteristics corresponding to the display
location on the screen, and one register is composed of 16 bits. The lower 8 bits select the font from the 256 ROM
fonts, and the upper 8 bits give font characteristics to the selected font.
The frame control registers are in the 16th row. It controls OSD's display location, character height and scroll in
units of frame.
The V-AMP control registers are also located in the 17th row.
20
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
REGISTER DESCRIPTION
Character & Attribute Register: Row00 ~ 14, Column00 ~ 29
F
E
Blink SHA
CTL1
D
C
B
A
9
8
7
6
5
4
3
2
1
0
RB
RG
RR
CB
CG
CR
C7
C6
C5
C4
C3
C2
C1
C0
CTL0
Extended Code
Character Attribute
Character Code (256 fonts)
Frame Control Register 0: Row15, Column00
F
E
D
C
B
A
9
-
-
-
-
-
-
-
8
7
6
5
4
3
FullW EX-EN BGEN ScrEN ScrT BliEN
2
1
0
BliT
Erase
EN
2
1
0
Frame Control Register 1: Row15, Column01
F
E
CP1 CP0
D
Fpll
C
B
A
9
8
7
6
5
4
3
HF2 HF1 HF0 dot1 dot0 HPOLVPOL CH5 CH4 CH3 CH2 CH1 CH0
PLL Control
Polarity
Character Height Control
Frame Control Register 2: Row15, Column02
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
HP7 HP6 HP5 HP4 HP3 HP2 HP1 HP0 VP7 VP6 VP5 VP4 VP3 VP2 VP1 VP0
Horizontal Start Posiotion
Vertical Start Posiotion
Frame Control Register 3: Row15, Column03
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
Blink SHA RINT CINT Blink SHA RINT CINT Blink SHA RINT CINT Blink SHA RINT CINT
CTL11
CTL10
CTL01
CTL00
21
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Video AMP Control Register: Row 16, Column 00 - 05
Column 00
F
E
D
C
B
A
9
8
7
BRT7 BRT6 BRT5 BRT4 BRT3 BRT2 BRT1 BRT0 VC7
6
5
4
3
2
1
0
VC6
VC5
VC4
VC3
VC2
VC1
VC0
1
0
Brightness Control
Contrast Control
Column 01
F
E
D
C
B
A
9
8
7
6
5
4
3
2
GSB7 GSB6 GSB5 GSB4 GSB3 GSB2 GSB1 GSB0 RSB7 RSB6 RSB5 RSB4 RSB3 RSB2 RSB1 RSB0
G SUB Contrast Control
R SUB Contrast Control
Column 02
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
OSD7 OSD6 OSD5 OSD4 OSD3 OSD2 OSD1 OSD0 BSB7 BSB6 BSB5 BSB4 BSB3 BSB2 BSB1 BSB0
OSD Contrast Control
B SUB Contrast Control
Column 03
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
GWB7 GWB6 GWB5 GWB4 GWB3 GWB2 GWB1 GWB0 RWB7 RWB6 RWB5 RWB4 RWB3 RWB2 RWB1 RWB0
G Cut-off Control
R Cut-off Control
Column 04
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
0
CUT7 CUT6 CUT5 CUT4 CUT3 CUT2 CUT1 CUT0 BWB7 BWB6 BWB5 BWB4 BWB3 BWB2 BWB1 BWB0
Cut-off Brightness Control
B Cut-off Control
Column 05
F
E
D
C
CLPS CLPP BLKP CS2
B
A
9
8
7
6
5
4
3
2
1
0
CS1
HG3
HR3
HB3
SB
HG2
HR2
HB2
HG1
HR1
HB1
HT
’- ’; Don’t care bit
Figure 10. Register Description
22
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 11. Register Description
Registers
Bits
Character &
Attribute Registers
(Row 00 ~ 14,
Column 00 ~ 29)
C7 ~ C0
(Bit 7 ~ 0)
Description
Character code address
This is the address of 256 ROM fonts.
CB, CG, CR
(Bit A ~ 8)
Character color
The character color is chosen from 16 colors using these 3 bits and the
frame control register 3’s CINT bit.
RB, RG, RR
(Bit D ~ B)
Raster color is determined by these bits.
The raster color is chosen from out of 16 colors using these 3 bits and the
frame control register 3’s RINT bit.
SHA / CTL0
(Bit E)
Character shadowing / CTL0(Extended Code)
If you set the frame control register 0’s EX-EN bit to '0', this bit carries out
character shadowing feature.( If SHA bit is '1', the character shadowing is
shown)
If you set the frame control register 0’s EX-EN bit to '1', this bit is used for
extended code.
Blink / CTL1
(BIt F)
Character blinking / CTL1(Extended Code)
If you set the frame control register 0’s EX-EN bit to '0', this bit carries out
character blinking feature.( If Blink bit is '1', the character blinking feature is
shown)
If you set the frame control register 0’s EX-EN bit to '1', this bit is used for
extended code.
If you set the Frame Control Register 0’s 'EX-EN' bit as '1', the Character & Attribute Register’s 'SHA' and 'Blink'
bits are used to call the Extended Code.
In other words, the combination of SHA and Blink bits can call four kind Extended Code 'CTL00', 'CTL01',
'CTL10' and 'CTL11', the CINT, RINT, SHA and Blink features can be carried out in a unit of character fonts.
23
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 11. Register Description(Continued)
Registers
Frame Control
Registers - 0
(Row15,
Column00)
Bits
Description
EN
(Bit 0)
OSD enable
OSD is enabled when this bit is '1'. In other words, if this bit isn't '1'OSD is
not output inspite of writing control data. We recommend that you enable
the OSD after setting the control registers (such as the character & attribute
register) because of video and OSD output timing.
Erase
(Bit 1)
RAM erasing
If this bit is '1', the RAM data (character & attribute registers) is erased. The
time spent in carrying out this operation is called erasing time, which can be
calculated as follows.
Erasing time = RAM clock × 480 (RAM cell no.)
RAM clock = 12 dot clock
Dot clock = 1/(dot frequency)
Dot frequency = Horizontal frequency × resolution (mode)
Therefore, the maximum erasing time value is:
(Erasing Time)MAX = (12 × 480) / (15k × 320) = 1.2ms
24
BliT
(Bit 2)
Blink time control
If this bit is '1', blink time is 0.5sec, and if not, 1sec.
BliEN
(Bit 3)
Blinking enable
Blinking effect is controlled by this bit.
If this bit is ’1’, blinking effect is enabled.
If this bit is '0', a full OSD screen blinking effect is disabled.
ScrT
(Bit 4)
Scroll time control
If this bit is '1', scroll time is 0.5sec, and if not, 1sec.
ScrEN
(Bit 5)
Scroll enable
Scrolling effect is controlled by this bit. If this bit is '1', scrolling effect is
enabled. You must remember that scrolling can be turned on/off only when
OSD is enabled/disabled.
BGEN
(Bit 6)
Back ground enable
If the BGEN bit is '1' and the raster color is black, the raster is transparent.
That is, the video back ground is shown. If not, the OSD raster covers the
video’s back ground. Refer to other color effect.
EX-EN
(Bit 7)
Extended code enable
If the EX-EN bit is '1', the Character & Attribute register’s Blink, SHA bits
carry out Extended Code features instead of Blink and SHA features.
FullW
(Bit 8)
Full white pattern enable
If the FullW bit is '1', the full white pattern is displayed in the screen.
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 11. Register Description(Continued)
Registers
Frame Control
Registers - 1
(Row15,
Column01)
Bits
Description
CH5 ~ CH0
(Bit 5 ~ 0)
Character height control
While the purpose of VZ[1:0] (vertical character height) is to control the
absolute size of the character, the purpose of CH[5:0] (Character Height) is
to output OSD of a uniform size even if the resolution changes. If you adjust
the value in the range of CH = 18 ~ CH = 63, each line's repeating number
is decided (standard height CH = 18 is the reference value), by which the
line is repeated. For more information on repeating number selection, refer
to character height.
VPOL
(Bit 6)
Polarity of vertical fly back signal
If this bit is '1', VFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
HPOL
(Bit 7)
Polarity of horizontal fly back signal
If this bit is '1', HFLB's polarity is positive, and if '0', it is negative. In other
words, this bit is set to '1' if active high, and '0' if active low.
dot1, dot0
(Bit 9, 8)
Resolution control (dots/line)
Dot1
Dot0
No. of Dots
0
0
320 dots/line
0
1
480 dots/line
1
0
640 dots/line
1
1
800 dots/line
As shown above, the number of dots per horizontal line is decided by a
combination of these two bits.
HF2~HF0
(Bit C ~ A)
FPLL
(Bit D)
Horizontal frequency
PLL's horizontal frequency is decided by the combination of these 3 bits.
This is related to the selection of DOT[1:0], so you can't numerically
express the frequency range with only the HF[2:0] selection. For more
information, please refer to HF Bits Selection.
Full range PLL
If this bit is '1', the OSD_PLL block's VCO operates at full range (4.8MHz 96MHz). If it is '0', it operates within the region decided by the HF bit [C:A]
explained above. if you can’t optimize OSD screen decided by the HF bit in
the high region, you may set the FPLL bit to '1'.
25
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 11. Register Description(Continued)
Registers
Frame Control
Registers - 1
(Row15,
Column01)
Bits
Description
CP1, CP0
(Bit F, E)
Charge pump output current control
This is the PLL block's internal phase detector output status, converted into
current. Refer to PLL control.
CP1
CP0
Charge Pump Current
0
0
0.50 mA
0
1
0.75 mA
1
0
1.00 mA
1
1
1.25 mA
The output is decided by the combination of these two bits.
The purpose of bits 'HPOL', and 'VPOL' is to provide flexibility when using the KB2514 IC. No matter which polarity
you choose for the input signal, the IC will handle them identically, so you can select active high or active low
according to your convenience.
26
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Tabel 4. Register Description (Continued)
Registers
Frame Control
Registers - 2
(Row 15,
Column 02)
Frame Control
Registers - 3
(Row 15,
Column 03)
Bits
Description
VP7 ~ VP0
(Bit 7 ~ 0)
Vertical start position control ( = VP[7:0] × 4)
Signifies top margin height from the V-Sync reference edge.
HP7 ~ HP0
(Bit F ~ 8)
Horizontal start position control ( = HP[7:0] × 6)
Signifies delay of the horizontal display from the H-Sync reference edge to
the character's 1st pixel location.
CTL 00
(Bit 3 ~ 0)
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E and F
bits are '0', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
CTL 01
(Bit 7 ~ 4)
Extended code
In case the EX-EN bit is ’1’and the Character & Attribute register’s E bit is
'1' and F bit is '0', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
CTL 10
(Bit B ~ 8)
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E bit is
'0' and F bit is '1', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
27
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Tabel 4. Register Description (Continued)
Registers
Frame Control
Registers - 3
(Row 15,
Column 03)
28
Bits
Description
CTL 11
(Bit F ~ C)
Extended code
In case the EX-EN bit is '1' and the Character & Attribute register’s E and F
bits are '1', these bits have meanings.
If you set the CINT(character color intensity) bit '1', the character color
intensity feature is carried out.
If you set the RINT(raster color intensity) bit '1', the raster color intensity
feature is carried out.
If you set the SHA(character shadowing) bit '1', the character shadowing
feature is carried out.
If you set the Blink(character blinking) bit '1', the character blinking feature
is carried out.
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Tabel 4. Register Description (Continued)
Registers
V-AMP Control
Registers - 0
(Row 16,
Column 00)
V-AMP Control
Registers - 1
(Row 16,
Column 01)
V-AMP Control
Registers - 2
(Row 16,
Column 02)
V-AMP Control
Registers - 3
(Row 16,
Column 03)
V-AMP Control
Registers - 4
(Row 16,
Column 04)
Bits
VC7 ~ VC0
(Bit7 ~ 0)
Description
The contrast adjustment is made by contrdling simultaneously the gain
of three internal variable gain amplifiers.
The contrast adjustment allows to cover a typical range of 38dB.
BRT7 ~ BRT0
(BitF ~ 8)
The brightness adjustment controls to add the same black level
(pedestal) to the 3-channel R/G/B signals after contrast amplifier.
RSB7 ~ RSB0
(Bit7 ~ 0)
R channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
GSB7 ~ GSB0
(BitF ~ 8)
G channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
BSB7 ~ BSB0
(Bit7 ~ 0)
B channel SUB contrast control.
The SUB contrast adjustment is used to adjust the white balance, and
the gain of each channel is controlled.
The SUB contrast adjustment allows you to cover a typical tange of
12dB.
OSD7 ~ OSD0
(BitF ~ 8)
The OSD contrast adjustment is made by contrdling simultaneously the
gain of three internal variable gain amplifiers.
The OSD contrast adjustment allows to cover a typical range of 38dB.
RWB7 ~ RWB0
(Bit7 ~ 0)
R channel cut-off control.
The cut-off adjustment is used to adjust the raster white balance.
GWB7 ~ GWB0
(BitF ~ 8)
G channel cut-off control.
The cut-off adjustment is used to adjust the raster white balance.
BWB7 ~ BWB0
(Bit7 ~ 0)
B channel cut-off control.
The cut-off adjustment B used to adjust the raster white balance.
CUT7 ~ CUT0
(BitF ~ 8)
The cut-off brightness adjustment is made by simultaneously controlling
the external cut-off current.
29
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Tabel 4. Register Description (Continued)
Registers
V-AMP Control
Registers - 5
(Row 16,
Column 05)
Bits
HT
(Bit 0)
HG1 ~ HB1
(Bit3 ~ 1)
HG2 ~ HB2
(Bit6 ~ 4)
SB
(Bit 7)
30
Description
Video & OSD half tone enable.
If you set this bit to '1', the half tone function is on.
Then you can see the video signal & OSD raster.
HG1 ~ HB1 bits select OSD raster color 1 to be half tone.
To carry out half tone function, set the HT bit to '1'.
OSD
G
R
B
Raster
Color 1
POR
0
0
0
0
Black
O
0
1
0
0
1
Blue
0
1
0
0
1
0
Red
0
1
1
0
1
1
Magenta
1
0
0
1
0
0
Green
1
0
1
1
0
1
Cyan
1
1
0
1
1
0
Yellow
1
1
1
1
1
1
White
HG1
HR1
HB1
0
0
0
HG2 ~ HB2 bits select OSD raster color 2 to be half tone.
To carry out half tone function, set the HT bit to '1'.
OSD
G
R
B
Raster
Color 2
POR
0
0
0
0
Black
O
0
1
0
0
1
Blue
0
1
0
0
1
0
Red
0
1
1
0
1
1
Magenta
1
0
0
1
0
0
Green
1
0
1
1
0
1
Cyan
1
1
0
1
1
0
Yellow
1
1
1
1
1
1
White
HG2
HR2
HB2
0
0
0
Soft blanking enable
If you set this bit '1', the R/G/B outputs go to GND.
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Tabel 4. Register Description (Continued)
Registers
V-AMP Control
Registers - 5
(Row 16,
Column 05)
Bits
HG3 ~ HB3
(BitA ~ 8)
CS2 ~ CS1
(BitC ~ B)
Description
HG3 ~ HB3 bits select OSD raster color 3 to be half tone.
To carry out half tone function, set the HT bit to '1'.
OSD
G
R
B
Raster
Color 3
0
0
0
0
Black
0
1
0
0
1
Blue
1
1
0
0
1
0
Red
1
1
1
0
1
1
Magenta
0
0
0
1
0
0
Green
0
0
1
1
0
1
Cyan
0
1
0
1
1
0
Yellow
0
1
1
1
1
1
White
HG3
HR3
HB3
1
0
1
POR
O
Cut-off offset current control
CS2
CS1
Cut-off Offset Current
0
0
100µA
0
1
150µA
1
0
0µA
1
1
50µA
POR
O
BLKP
(Bit D)
Polarity of horizontral fly back signal
If this bit is '0', HFLB’s polarity is negative, and if '1', it is positive.
CLPP
(Bit E)
Polarity of clamp pulse signal
If this bit is '0', CLP’s polarity is positive, and if '1', it is negative.
This bit has meaning only if the CLPS bit is set to '1'.
CLPS
(Bit F)
Clamp pulse generation enable
If this bit is '0', clamp signal is made using the HFLB signal, so there is
no need to supply the clamp signal.
and if '1' you must supply external clamp signal.
31
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
VIDEO AMP PART ADDRESS MAP
Register sub address
Table 12. Video AMP Part Address Map
SUB
Address
[Hex]
Function
F
E
D
C
B
A
9
8
7
6
5
4
3
2
1
POR
Value
[Hex]
0
1000
Brightness control
Contrast control
8080
1001
SUB contrast control (G)
SUB contrast control (R)
8080
1002
OSD contrast control
SUB contrast control (B)
8080
1003
Cut-off control (G)
Cut-off control (R)
8080
1004
Cut-off brightness control
Cut-off control (B)
8080
CLPS
1005
CLPP
BLKP
CS2
CS1
HG3
HR3
HB3
SB
HG2
HR2
HB2
HG1
HR1
HB1
HT
1800
Contrast Register (SUB ADRS: 00H) (Vin = 0.7Vpp, bright: 80H, subcont: FFH)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
Contrast (Vpp)
Gain (dB)
00
0
0
0
0
0
0
0
0
0
-
80
1
0
0
0
0
0
0
0
2.85
-
FF
1
1
1
1
1
1
1
1
5.2
-
Increment/bit
int. Value (Hex)
O
0.0223
Brightness Register (3-ch) (SUB ADRS: 00H) (cont: 80H, subcont: 80H)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
Brightness (Vpp)
00
0
0
0
0
0
0
0
0
0.2
80
1
0
0
0
0
0
0
0
1.5
FF
1
1
1
1
1
1
1
1
2.7
Increment/bit
Int. Value (Hex)
O
0.01055
SUB Contrast Register (R/G/B-ch) (SUB ADRS: 01/02H)
(Vin = 0.7Vpp, bright: 40H, cont: FFH)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
00
0
0
0
0
0
0
0
0
-
80
1
0
0
0
0
0
0
0
-
FF
1
1
1
1
1
1
1
1
-
Increment/bit
32
SUB Contrast
(Vpp)
Gain
(dB)
Int. Value
(Hex)
O
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
OSD Contrast Register (SUB ADRS: 02H) (VOSD = TTL, bright: 80H, subcont: 80H)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
OSD Contrast
(Vpp)
Gain
(dB)
00
0
0
0
0
0
0
0
0
0
-
80
1
0
0
0
0
0
0
0
3.2
-
FF
1
1
1
1
1
1
1
1
6.4
-
Increment/bit
Int. Value
(Hex)
O
0.025
Cut-Off Brightness Register (3-ch) (SUB ADRS: 04H)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
Cut-Off Brightness (µA)
00
0
0
0
0
0
0
0
0
0
80
1
0
0
0
0
0
0
0
100
FF
1
1
1
1
1
1
1
1
200
Increment/bit
Int. Value (Hex)
O
0.781
Cut-Off Register (R/G/B-ch) (SUB ADRS: 03/04H)
(cont = 80H, subcont: 80H)
Hex
B7
B6
B5
B4
B3
B2
B1
B0
Cut-Off EXT (µA)
00
0
0
0
0
0
0
0
0
0
80
1
0
0
0
0
0
0
0
300
FF
1
1
1
1
1
1
1
1
600
Increment/bit
Int. Value (Hex)
O
2.344
33
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
ADDRESSING
•
ROM Fonts
KB2514 provides 256 Rom fonts for displaying OSD Icons, which allows the use of multi-language OSD Icons.
Font $000 is reserved for blank data.
0
1
E
F
00
$000
$001
$00E
$00F
01
$010
$011
$01E
$01F
Fonts
0E
$0E0
$0E1
$0EE
$0EF
0F
$0F0
$0F1
$0FE
$0FF
Figure 11. Composition of the ROM Fonts
34
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
COLORING
If you have an Intensity feature, the number of possible colors you can express becomes doubled. In other words,
the number of colors you can represent with three colors blue, green, and red is 8 ( = 23), but with the intensity
feature, it is 16 ( = 24).
•
Character Color
Character color is assinged for each font, and the 4 components for expressing a color are listed below.
Blue
Character & attribute register's CB bit[A]
Green
Character & attribute register's CG bit[9]
Red
Character & attribute register's CR bit[8]
Intensity
•
If the EX-EN bit is '1' and the Frame Control Register 3 CTL’s CINT bit called by Character &
Attribute register’s Blink, SHA bits is '1', the character intensity feature is enabled.
Raster Color
Blue
Character & Attribute register's RB bit[D]
Green
Character & Attribute register's RG bit[C]
Red
Character & Attribute register's RR bit[B]
Intensity
If the EX-EN bit is '1' and the Frame Control Register 3 CTL’s RINT bit called by Character &
Attribute register’s Blink, SHA bits is '1', the RASTER intensity feature is enabled.
According to the 'EX-EN', 'RINT' and 'CINT' bits setting, raster and character color intensity can be assigned in
units of character.
Notes for When Making KB2514 Fonts
Address 000h is appointed as blank data. RAM's initial values are all 0, and all bits are written as 0 when you
erase the RAM, so blank data means the initial value. In other words, blank data means 'do nothing'. You don't
need to write any data for the space font, except for 000h. It just needs to be an undotted area.
35
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
•
Other Color Effet
The Frame Control Register 0 'BGEN' bit's function is shown in the Figure below. If you set the 'BGEN' bit as '0'
after selecting A's raster color as black, the raster color black will be displayed. But if you set the 'BGEN' bit as
'1', after selecting B's raster color as black, the raster color black becomes invisible, so the video back ground
color (gray) is displayed as if it is the raster color.
Black
Gray
Light Blue
BGEN bit = 0 & Rastor Color = Black
A
B
BGEN bit = 1 & Rastor Color = Black
C
BGEN bit = 1 & Rastor Color = Light Blue
Gray
Figure 12. Color Effect by BGEN Bit
36
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
HEIGHT/POSITIONING
•
Character Height
The purpose of CH[5:0] (Character Height) is to output a uniformly sized OSD even if the resolution changes.
To express a Character Height of CH = 18 ~ CH = 63 after receiving CH[5:0]'s input from the frame control
register-1, decide on each line's repeating number (Standard Height CH = 18) and repeat the lines.
The following Figure shows two examples of a height-controlled character. height control is carried out by
repeating some of the lines.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
: added
line
Standard font
in high vertical resolution
Standard Font(12*18)
Height-controlled font
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
Standard Font(12*18)
: added
line
Standard font
in more higher vertical resolution
Height-controlled font
Figure 13. Character Height
37
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Repeating line-number can be found by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round{14 ÷ (CH[5:0]-18)}.
1. If CH[5:0] is greater than 32 and less than or equal to 46 (32 < CH[5:0] ≤ 46), all lines are repeated once or
twice. The lines that are repeated twice are chosen by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-32)}.
2. If CH[5:0] is greater than 46 and less than or equal to 60 (46 < CH[5:0] ≤ 60), all lines are repeated two or three
times. The lines that are repeated three times are chosen by the following formula.
[# of the repeating lines = 2 + N × M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-46)}.
3. If CH[5:0] is greater than 60 and less than or equal to 64 (60 < CH[5:0] ≤ 64), all Lines are repeated three or four
times. The lines that are repeated four times are chosen by the following formula.
[# of the repeating lines = 2 + N x M],
where N = 1, 2, 3, ... and M = round {14 ≤ (CH[5:0]-60)}.
CH's reference value is 18, and even if you input 0, it operates in the same way as when CH = 18. The repeating
line-number is limited to 16. If the M value is less than or equal to 1, all lines of the standard font are repeated more
than once.
Table 13. Repeating Line as Controlling by CH bits
Character Height
Repeating Line
CH = 18
-
CH = 19
9
CH = 20, 21
6, 13
CH = 22
5, 11, 17
CH = 23
4, 9, 14, 19
CH = 24
3, 7, 11, 15, 19, 21
CH = 25, 26, 27
3, 7, 11, 13, 15, 19, 22
CH = 28
3, 6, 9, 12, 14, 18, 20, 23, 25
CH = 29
3, 6, 9, 11, 13, 15, 18, 21, 23, 25, 26
CH = 30
3, 6, 8, 10, 12, 14, 16, 18, 20, 22, 25, 27
CH = 31
2, 5, 7, 9, 11, 13, 15, 17, 21, 23, 25, 27, 28
CH = 32, 33, 34, 35
2, 5, 7, 9, 11, 13, 15, 18, 21, 23, 25, 27, 28, 29
CH = 36
-
CH = 37
18
38
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
Table 13. Repeating Line as Controlling by CH bits
Character Height
Repeating Line (Continued)
CH = 38, 39
12, 25
CH = 40
10, 20, 30
CH = 41
8, 16, 24, 32
CH = 42
6, 12, 18, 24, 30, 36
CH = 43, 44, 45
6, 12, 18, 24, 30, 36, 41
CH = 46
4, 8, 12, 17, 21, 25, 29, 33, 37, 41
CH = 47
4, 8, 12, 16, 20, 24, 28, 32, 36, 40, 44
CH = 48
4, 8, 12, 16, 20, 23, 26, 29, 33, 37, 41, 45
CH = 49
4, 8, 12, 16, 19, 22, 25, 28, 31, 35, 39, 43, 47
CH = 50, 51, 52, 53
4, 8, 12, 15, 18, 21, 24, 27, 30, 33, 36, 40, 44, 48
CH = 54
-
CH = 55
27
CH = 56, 57
18, 36
CH = 58
14, 28, 42
CH = 59
12, 23, 34, 45
CH = 60
9, 18, 26, 34, 43, 52
CH = 61, 62, 63
8, 16, 23, 30, 37, 44, 51
39
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
•
Positioning
The frame control register-2's HP Bit [F:8] signifies delay of the horizontal display from the H-Sync reference
edge to the character's 1st pixel location, and is controlled by multiplying HP [F:8]'s range value by 6. Also, VP
bit[7:0] signifies the top margin height from the V-Sync reference edge, and is controlled by multiplying 4 to the
VP [7:0]'s range value. Refer to the Figure shown below.
(HFLB)
VP[7:0]
HP[7:0]
OSD characters
30 columns (= 30 x 12 dots)
15 rows
(=15 x 18 lines)
(VFLB)
Background Screen
Figure 14. Frame Composition with the OSD Characters
40
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
VISUAL EFFECTS
•
Shadowing
The character shadow can only be black. Character shadow is making 1 pixel to the right and below the
character.
Shadowing
Figure 15. Character Shadowing
•
Scrolling
Scrolling is slowly displaying or erasing a character from the top line to the bottom. This effect makes it look as
if 1 character line is scrolling up or down. asharacter line is scrolling up or down.
Figure 16. Scrolling
41
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
PLL CONTROL
•
Introduction
PLL (Phase Lock Loop) is feedback controlled circuit that maintains a constant phase difference between a
reference signal and an oscillator output signal.
Generally, PLL is composed as follow Figure.
Reference Signal
PFD
(Phase Frequency Detector)
LF
(Loop Filter)
VCO (Voltage
Controlled Oscillator)
FD
(Frequency Detector)
Figure 17. Block Diagram of General PLL
- PFD (Phase Frequency Detector)
PFD compares the phase of the VCO output frequency, with the phase of a reference signal frequency output
pulse is generated in proportion to that phase difference.
- LF (Loop Filter)
LF smooths the output pulse of the phase detector and the resulting DC component is the VCO input.
- VCO (Voltage Controlled Oscillator)
VCO is controlled by loop filter output. The output of the VCO is fed back to the phase frequency detector
input for comparison which in turn controls the VCO oscillating frequency to minimize the phase difference.
- FD (Frequency Divider)
FD divides too much different frequency that is oscillated from the VCO to compare it with reference signal
frequency.
42
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
•
KB2514
PLL of the KB2514
PLL is composed of the phase detector, charge pump, VCO, and N-divider as 4 sub-blocks.
Loop
Filter
# Composed of External Components
CP_out
(Pin4)
HFLB (Pin32)
Phase
Detector
VCO_in
(Pin3)
Charge
Pump
VCO_out
VCO
Div_out
N-Divider
CP0
CP1
DOT0
DOT1
HF0 HF1 HF2
Figure 18. Block Diagram of the PLL Built in KB2514
The following is the description of the input/output signals.
- HFLB (Input)
Horizontal flyback signal is refrence signal of the PLL built in KB2514.
The HFLB signal's frequency range is 15 ~ 90kHz, so the PLL block must be a wide range PLL that can cover
HFLB's entire frequency range.
> 4.2V
< 0.4V
fHFLB
~2us
- VCO (Input)
Error signal that passes through an external loop filter is input into VCO.
Operation voltage range is 1-4V. You can raise immunity towards external noise by lowering VCO
sensitivity. You can do this by making it have the maximum operation voltage range possible in the 5V power
voltage.
43
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
- DOT0, 1 (Input)
Mode control signal that controls the number of dots per line in the frame control register. There are 4 modes:
320, 480, 640, and 800 dots/line.
According to your choice of mode, the OSD_PLL block's N-Divider is controlled by one of ÷320, ÷480, ÷640, or
÷800 Divider.
- HF0, 1, 2 (Input)
The horizontal Sync frequency information is received from the micro controller through the frame control
registers-1's bit C-A.
- CP0, 1 (Input)
Charge Pump's output sourcing (or sinking) current control pin.
This control data is received through frame control registers-1's bits E-D.
- VCO_OUT (Output)
VCO output that becomes a system clock. It is the OSD R, G, B output signal's dot frequency, and the standard
signal for OSD's various timings.
Also, it is input into the N-Divider and makes a PLL loop
> 4.2V
< 0.4V
fclk
Rise Time : < 4nS
Fall Time : < 4nS
- CP_OUT (Output)
Charge Pump circuit's output. input into external loop filter. It becomes one of 3 states according to the standard
signal input into the phase detector (HFLB) and the divider output (Div_Out).
- HFLB Div_Out is lead: Current sink
- HFLB Lag: Current source
- HFLB In-Phase: High impedence
44
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
TUNNING FACTORS OF THE KB2514 PLL
•
PLL External Circuit
You may follow the recommendations for PCB art work and input/output signal characteristic improvement in
recommendation.
The external circuit that has the most influence on KB2514 PLL block operation is pin 3 (VCO_IN) and pin 4
(CP_OUT)'s surrounding circuit. Refer to OSD PLL block.
3
4
5
No Connection
(pin open)
C1
C2
R1
R2
1MΩ
Figure 19. PLL External Circuit
Because the PLL circuit is basically a feedback circuit, there are many components that influence the
characteristics. C1, C2, R1, and R2 do not have a localized effect.
As you can see, they are connected to the PLL control bits and influence the characteristics through their
complicated relationships. The main functions of the time canstant and their reference values are as follows.
Table 14. Main Function of Time Constant in PLL External Circuit
Time Canstant
Recommended Value
C1
10uF
R1
5.6KΩ(7.5KΩ)
R2
27KΩ (or 33KΩ)
C2
33pF
Main Function
Influences the damping ratio and controls the PLL
response time
Same as C1
Charge pump current adjustment
Removes ripple caused by R-C circuit
45
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
•
PLL Control Bit
After configuring an external circuit using the recommended values, carry out programming using the
recommended values for frequency range and control bits given in the Table below.
Table 15. Recommend Values of PLL Control Bit
Register Set
PLL Control Bit
Freq. Range
CP1
CP0
FPLL
HF2
HF1
HF0
DOT1
DOT0
Hex
Below 40kHz
0
0
0
0
1
0
1
1
0B
40 - 50kHz
1
0
0
1
0
0
1
1
93
50 - 70kHz
1
1
0
1
0
1
1
1
A7
Above 70kHz
1
1
0
1
1
1
1
1
AF
(Ref: 800 × 600, C1: 10uF, R1: 5.6K, R2: 27K, C2: 33pF)
•
Locking Range
As you can see the figure below, it is 2.35V that measured voltage at pin-3 to optimize OSD quality. The proper
voltage range is 1.5 ~ 3.25V.
Locking Range
4V
3.25V
2.37V
1.625V
1.5V
Ve (min)
0.75V
f0
fC
-2¥ð
fL
Figure 20. Locking Range
46
2¥ð
fmax
Ve (max)
1.625V
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
•
KB2514
HF Bits Selection
HF bits is not selecting from out of 8 (23) steps uniformly, but selecting the step shown in figure below. In
example, at 800 mode, there are 5 steps that the frequency range is controlled by HF bits.
Table 16. HF Bits Selection
DIV
DOT1
DOT0
320
0
0
480
0
1
640
1
0
800
1
1
HF2
HF1
HF0
After fixing time constants of the external circuit and PLL control bits except HF bits, if HF bits are stepped up, the
voltage measured at pin-3 drops. On the contrary, if HF bits are stepped down, the voltage rises.
The voltage measured at pin-3 don't change by changing CP bits.
•
External Register at pin-4
The external register at pin-4 is the factor that changes greatly at PLL tunning. The initial value of this external
register value is decided as follows.
At first, the external register is replaced variable-register (about 50KΩ range).
and then, set the lowest PLL control bits at the lowest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
also, set the highest PLL control bits at the highest frequency allowed by set.
and then, change variable-register to be 2.35V that optimum voltage is locking.
and then, measure register value at this time.
You may decide the average of these two registers' value to initial value.
47
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
The table below shows that other factors change as changing external register's value.
Fixing Factor
Variable Factor
Time constants of the external circuit
and PLL control bits except
Rext
48
Change
Voltage
Current
Lock Range
↑
↑
↓
↓ (shift)
↓
↓
↑
↑ (shift)
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
RECOMMENDATION
5V Power Routing
KB2514's OSD part power is composed of analog VDD and digital VDD. To eliminate clock noise influence in the
digital block, you need to separate the analog VDDA and digital VDD.
(BD102 use: Refer to Application Circuit )
12V Power Routing
Because KB2514 is a wideband AMP of above 150MHz, 12V power significantly affects the video characteristics.
The effects from the inductance and capacitance are different for each board, and , therefore, some tuning is
required to obtain the optimum performance. The output power, VCC2, must be separated from VCC1 and VCC3
using a coil, which is parallel-connected to the damping resistor.The appropriate coil value is between 20uH 200uH. Parallel-connected a variable resistor to the coil and control its resistance to obtain the optimum video
waveform.
(Moreover, BD103 can tune using a coil and variable resistor to obtain the optimum video waveform.
L103, R124, BD103: Refer to application circuit)
VCC1, VCC3 12V Power
Use a 104 capacitor and large capacitor greater than 470uH for the power filter capacitor.
12V Output Stage Power VCC2
Do not use the power filter capacitor.
5V Digital Power VDD
Don't use a coil or magnetic core to the VDD input. Make the power filter capacitor, an electric capacitor of greater
than 50uF, single and connect it to VSS, the digital GND.
Output Stage GND2
Care must be taken during routing because it ,as an AMP output stage GND, is an important factor of video
oscillation. R/G/B clamp cap and R/G/B load resistor must be placed as close as possible to the GND2 pin. GND2
must be arranged so that it has the minimum GND loop, which at one point must be connected to the main GND.
Digital GND VSS
When this is to be connected directly to the GND2, it can cause the OSD clock noise, so the loop connection
should be routed as far away as possible. If the OSD clock noise affects the screen, separate VSS GND from all
GND and connect it to the main board using a bead. Again, the bead connection point should be placed as far
away as possible to the GND2.
Analog Block
The PLL built in to KB2514 is sensitive to noise due to the wide range PLL characteristics. Therefore, you need to
isolate the analog block in the following manner. First make a separate land for the analog block (pin2 - pin6)'s
ground, and connect it to the main ground through a 1MΩ resistor. The analog GND of both sides of a double faced
PCB must be separated from the main ground. (Separate pin 2's 5V analog GND, which is the GND for OSD PLL,
from the main and digital GNDs and connect it to the main GND using about 1MΩ resistor. GND for pins 2 - 6 is the
No. 2 VSSA GND.)
49
KB2514
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
I2C Control Line (SCL, SDA Line)
I2C communication noise (noise generated in the OSD display pattern when data is transmitted in the I2C line) may
be generated because of an I2C control line that passes near the analog block. The I2C control lines near KB2514
must be separated from the analog block as much as possible.
Furthermore, the I2C bus interference can be prevented by inserting a series resistor in the line.
Horizontal Flyback Signal
Display jittering can be generated if the horizontal signal (HFLB) input to KB2514 is not a clean signal.
We recommend a short path and shielded cable for obtaining a clean signal.
Generally, the input horizontal signal (HFLB) is generated by using a high voltage horizontal flyback signal. The
effect from the high voltage flyback signal can be reduced by separating the R115 and R117 GND, which
determines the flyback signal slice level, from the transistor GND, which generates the actual KB2514 input
horizontal signal. Furthermore, the flyback signal sharpness must be maintained by minimizing the values of R115,
R116 and R117 resistors, which set the horizontal signal slice level. values.
(R115, R116, R117: Refer to application circuit )
HFLB Input Signal Generator
You can correct the circuit by reducing the resistors that sets the slice level of the horizontal signal in the HFLBgenerating circuit.
50
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
APPLICATION BOARD CIRCUIT
CN1
CN2
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1N4148
DR01
DG02
1N4148
DG01
6.3V
DB02
1N4148
DB01
103
1N4148
12V
DR02
70V
C123
R123
1N4148
C109
1M
103
1N4148
C124
103
RB01
RG01
RR01
75
12V
RB02
75
C110
75
RG02
75
+
75
L101
100uH
RR02
75
100uF
BD102
5V
R107
1K
C102
CG02
104
CR01
104
R108
5.6K
+
CB02
104
1uF
R109
27K
C112
4.7K
1uF
+
R101
33pF
1
2
3
4
5
6
VFLB
VSSA
VCO_IN
VREF1
VREF
VDDA
470uF
+
BD103
VDD
HFLB
SDA
SCL
VSS
RCT
GCT
BCT
ROUT
RCLP
VCC2
GCLP
104
C128
560
104
560
C160
+
10K
32
31
30
29
28
27
26
25
24
23
22
21
20
19
R119
R116
1N4148
104
C103
R118
330pF
D102
18
150
C152
C151
17
C118
GOUT
1.8nF
G1
R117
GND2
BOUT
BCLP
C126
1nF
CONT_CAP
KB2514
WSP-401M
7
ABL_IN
GND
CLP_IN
VCC3
RIN
VCC1
GIN
SK101
C116
8
9
10
11
12
13
14
GND1
BIN
5V
R103
390
15
16
102
1nF
12_1V
100
C119
C117
C113
10uF
C114
R102
47uF
R115
R124
2K
220
2
12V
L103
27uH
R114
3
Q102
2N3904
470
CB02
CG02
CR02
104
104
104
RG03
RB03
5V
1
RR03
470
470
470
RG15
47
RB15
47
RB04
100
RG04
100
CB08
270pF
RR15
47
RR04
100
CG08
270pF
9
7
GND
VCC
DRIVER IC
RIN
GIN
+
5
4
3
2
1
47uF
70V
CG07
37pF
RB08
56
CB07
37pF
RG14
75
RB14
75
104
LR01
0.15uH
2.2K
LG01
0.15uH
LB01
0.15uH
3
3
3
2
QG02
2N5401C-Y
DB03
2
QR02
2N5401C-Y
DB04
1SS244
DG03
1
1
1
RB13
82K
RG13
82K
RR13
82K
DG05
1N4148
DG04
1SS244
70V
DB05
1N4148
RG08
56
RR14
75
RR12
2.2K
2
CR07
37pF
CR05
104
RG12
2.2K
RR08
56
104
CG05
104
RB12
C108
CR05
104
CB05
BOUT
CG05
104
104
3
3
3
CB05
QB02
2N5401C-Y
QR01
220uF
2N5551C-Y
2
C121
C107
+
QG01
2N5551C-Y
2
104
1
1
1
QB01
2N5551C-Y
2
C106
BIN
4.7K
VBB GOUT
RR20
4.7K
6
8
RR11
100
RG20
4.7K
ROUT
RG11
100
12V
RB11
100
RB20
CR08
270pF
DR03
DR04
1SS244
DR05
1N4148
+
+
CR04
1uF
+
CG04
1uF
1SS244
1SS244
1SS244
CB04
1uF
RR09
RG09
RB09
75K
75K
75K
G2
R104
390
RR10
39
SK102
SKB01
DMS-200D
RG10
39
RB10
39
DMS-200D
SKG01
C120
1nF
DMS-200D
G2
DMS-200D
SKR01
B_OUT
G_OUT
R_OUT
Figure 21. Application Board Circuit
51
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
TYPICAL APPLICATION CIRCUIT
CN1
CN2
1
2
3
4
5
6
1
2
3
4
5
6
7
8
9
10
11
12
13
14
1N4148
DR01
DG02
1N4148
DG01
6.3V
DB02
1N4148
DB01
103
1N4148
12V
DR02
70V
C123
R123
1N4148
C109
1M
103
1N4148
C124
103
RB01
RG01
RR01
75
12V
RB02
75
C110
75
RG02
75
+
75
L101
100uH
RR02
75
100uF
BD102
5V
R107
1K
C102
CR01
104
C112
1uF
1uF
R101
R108
5.6K
+
CG02
104
+
CB02
104
R109
27K
4.7K
33pF
1
2
3
4
5
6
VFLB
VSSA
VCO_IN
VREF1
VREF
VDDA
+
470uF
BD103
VDD
HFLB
SDA
SCL
VSS
RCT
GCT
BCT
ROUT
RCLP
VCC2
GCLP
GOUT
104
C128
560
104
560
C160
+
10K
32
31
30
29
28
27
26
25
24
23
22
21
20
19
R119
R116
1N4148
104
C103
R118
330pF
D102
18
150
C152
C151
17
C118
GND2
1.8nF
G1
R117
BOUT
BCLP
C126
1nF
CONT_CAP
KB2514
WSP-401M
7
ABL_IN
GND
CLP_IN
VCC3
RIN
VCC1
GIN
SK101
C116
8
9
10
11
12
13
14
GND1
BIN
5V
R103
390
15
16
102
1nF
12_1V
100
C119
C117
C113
10uF
C114
R102
47uF
R115
R124
2K
220
2
12V
L103
27uH
R114
3
470
Q102
2N3904
CB02
CG02
CR02
104
104
104
RG03
RB03
RR03
470
470
470
RG15
47
RB15
47
RR15
47
9
GND
DRIVER IC
RIN
+
5
4
3
2
70V
104
RG12
RR12
2.2K
2.2K
2.2K
RR14
75
RG14
75
RB14
75
3
3
3
2
QG02
2N5401C-Y
DB03
2
QR02
2N5401C-Y
DB04
1SS244
DG03
1
1
1
RB13
82K
RG13
82K
RR13
82K
DG05
1N4148
DG04
1SS244
70V
DB05
1N4148
VCC
CR05
104
RB12
2
47uF
104
CG05
104
C108
CR05
104
CB05
1
CG05
104
104
3
3
3
CB05
QB02
2N5401C-Y
QR01
220uF
2N5551C-Y
2
C121
C107
+
QG01
2N5551C-Y
2
GIN
1
1
1
QB01
2N5551C-Y
2
104
7
4.7K
BOUT
4.7K
C106
BIN
4.7K
ROUT
RR20
VBB GOUT
RR11
100
RG20
6
8
RG11
100
12V
RB11
100
RB20
DR03
DR04
1SS244
1SS244
1SS244
1SS244
DR05
1N4148
+
+
CR04
1uF
+
CG04
1uF
CB04
1uF
RR09
RG09
RB09
75K
75K
G2
LR01
0.15uH
LG01
0.15uH
LB01
0.15uH
R104
390
RR10
39
SK102
SKB01
DMS-200D
RG10
39
RB10
39
DMS-200D
SKG01
C120
1nF
DMS-200D
G2
DMS-200D
SKR01
B_OUT
G_OUT
R_OUT
Figure 22. Typical Application Circuit
52
75K
5V
1
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS
KB2514
ROM FONTS
Figure 23. ROM Fonts
53
KB2514
54
Preliminary
VIDEO AMP MERGED OSD PROCESSOR FOR MONITORS