TECHNICAL DATA KK74LV74 Dual D-type flip-flop with set and reset; positive-edge trigger N SUFFIX PLASTIC The KK74LV74 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT74. The KK74LV74 is a dual positive edge triggered, D-type flip-flop with individual data (D) inputs, clock (CP) inputs, set (SD) and (RD) inputs; also complementary Q and Q outputs. The set and reset are asynchronous active LOW inputs and operate independently of the clock input. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time prior to the LOW-toHIGH clock transition, for predictable operation. Schmitt-trigger action in the clock input makes the circuit highly tolerant to slower clock rise and fall times. • Output voltage levels are compatible with input levels of CMOS, NMOS and TTL ICS • Supply voltage range: 1.2 to 3.6 V • Low input current: 1.0 µА; 0.1 µА at Т = 25 °С • High Noise Immunity Characteristic of CMOS Devices 14 1 D SUFFIX SOIC 14 1 ORDERING INFORMATION KK74LV74N KK74LV74D Plastic SOIC TA = -40° to 125° C for all packages PIN ASSIGNMENT LOGIC DIAGRAM RESET 1 1 14 V CC DATA 1 2 13 RESET 2 CLOCK 1 3 12 DATA2 SET 1 4 11 CLOCK 2 Q1 5 10 SET 2 Q1 6 9 Q2 GND 7 8 Q2 FUNCTION TABLE Inputs PIN 20=VCC PIN 10 = GND Outputs Set Reset Clock Data Q Q L H X X H L H L X X L H L L X X H* H* H H H H L H H L L H H H L X No Change H H H X No Change H H X No Change *Both outputs will remain high as long as Set and Reset are low, but the output states are unpredictable if Set and Reset go high simultaneously. H= high level L = low level X = don’t care Z = high impedance 1 KK74LV74 MAXIMUM RATINGS* Symbol VCC Parameter Value Unit DC supply voltage -0.5 to +5.0 V 1 Input diode current ±20 mA 2 Output diode current ±50 mA Output source or sink current ±35 mA ICC VCC current ±70 mA IGND GND current ±70 mA Power dissipation per package: Plastic DIP *4 SO *4 750 500 IIK * IOK * IO * 3 PD Tstg TL mW Storage Temperature -65 to +150 °C 260 °C Lead Temperature, 1.5 mm (Plastic DIP Package), 0.3 mm (SO Package) from Case for 4 Seconds * Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. *1 VI < -0.5 V or VI > VCC + 0.5 V. *2 VO < -0.5 V or VO > VCC + 0.5 V. *3 -0.5 V < VO < VCC + 0.5 V. *4 Derating - Plastic DIP: - 12 mW/°C from 70° to 125°C SO Package: - 8 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol VCC Parameter DC Supply Voltage Min Max Unit 1.2 3.6 V VI DC Input Voltage 0 VCC V VO DC Output Voltage 0 VCC V TA Operating Temperature, All Package Types -40 +125 °C tr, tf Input Rise and Fall Time except for Schmitttrigger inputs (Figure 1) 0 0 0 0 1000 700 500 400 ns VCC =1.2 V VCC =2.0 V VCC =3.0 V VCC =3.6 V This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, VIN and VOUT should be constrained to the range GND≤(VIN or VOUT)≤VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open. 2 KK74LV74 DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C Unit 125°C min max min max min max VIH HIGH level input voltage 1.2 2.0 3.0 3.6 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - 0.9 1.4 2.1 2.5 - V VIL LOW level output voltage 1.2 2.0 3.0 3.6 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 - 0.3 0.6 0.9 1.1 V VOH HIGH level output voltage VI = VIH or VIL IO = -50 µА 1.2 2.0 3.0 3.6 1.1 1.92 2.92 3.52 - 1.0 1.9 2.9 3.5 - 1.0 1.9 2.9 3.5 - V VI = VIH or VIL IO = -6mА 3.0 2.48 - 2.34 - 2.20 - V VI = VIH or VIL IO = 50 µА 1.2 2.0 3.0 3.6 - 0.09 0.09 0.09 0.09 - 0.1 0.1 0.1 0.1 - 0.1 0.1 0.1 0.1 V VI = VIH or VIL IO = 6 mА 3.0 - 0.33 - 0.4 - 0.5 V Input current VI = VCC or 0 V * - ±0.1 - ±1.0 - ±1.0 µА Supply current VI =VCC or 0 V IO = 0 µА * - 4.0 - 40 - 80 µА VOL II ICC LOW level output voltage * VCC = 3.3 ± 0.3 V AC ELECTRICAL CHARACTERISTICS (CL=50 pF, tr=tf=6.0 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C min max min 125°C max min max Unit tPHL, tPLH Propagation delay , Clock to Q or Q VI = 0 V or VCC Figures 1,3 1.2 2.0 * - 140 45 28 - 160 56 35 - 180 67 42 ns tPHL, tPLH Propagation delay , Set to Q or Q VI = 0 V or VCC Figures 2,3 1.2 2.0 * - 150 44 27 - 170 54 34 - 190 65 41 ns tPHL, tPLH Propagation delay , Reset to Q or Q VI = 0 V or VCC Figures 2,3 1.2 2.0 * - 160 47 29 - 180 58 37 - 200 70 44 ns tTHL, tTLH Output Transition Time, Any Output VI = 0 V or VCC Figures 1,3 1.2 2.0 * - 90 20 15 - 110 25 19 - 130 30 23 ns 3.0 - 7.0 - - - - pF - 48 - - - - pF CI CPD Input capacitance Power dissipation VI = 0 V or VCC capacitance (per flip-flop) 3 KK74LV74 TIMING REQUIREMENTS (CL=50 pF, tr=tf=6.0 ns) Symbol Parameter Test VCC conditions V Guaranteed Limit 25°C -40°C to 85°C Unit 125°C min max min max min max tw Pulse Width, Clock, Set or VI = 0 V or VCC Reset Figures 1,2,3 1.2 2.0 * 75 25 16 - 96 32 20 - 114 38 24 - ns tsu Setup Time, Data to Clock VI = 0 V or VCC Figures 1,3 1.2 2.0 * 25 16 10 - 32 20 13 - 40 24 15 - ns trem Removal Time, Set or Reset to Clock VI = 0 V or VCC Figures 2,3 1.2 2.0 * 18 9 6 - 24 12 8 - 30 15 9 - ns th Hold Time, Clock to Data VI = 0 V or VCC Figures 1,3 1.2 2.0 * 3 3 3 - 5 3 3 - 5 3 3 - ns fc Clock Frequency 1.2 2.0 3.0 8 18 30 - 6 15 24 - 4 12 20 - MHz VI = 0 V or VCC Figures 1,3 * VCC = 3.3 ± 0.3 V V M = 0.5 ∗ VCC VOL and VOH are the typical output voltage drop that occur with the output load. Figure 1. Switching Waveforms 4 KK74LV74 V M = 0.5 ∗ VCC Figure 2. Switching Waveforms TEST POINT DEVICE UNDER TEST OUTPUT * CL * Includes all probe and jig capacitance Figure 3. Test Circuit EXPANDED LOGIC DIAGRAM (ONE FLIP-FLOP) 5 KK74LV74 N SUFFIX PLASTIC DIP (MS - 001AA) A Dimension, mm 8 14 B 7 1 Symbol MIN MAX A 18.67 19.69 B 6.1 7.11 5.33 C F L C -T- SEATING PLANE N G M K J H D 0.25 (0.010) M T NOTES: 1. Dimensions “A”, “B” do not include mold flash or protrusions. Maximum mold flash or protrusions 0.25 mm (0.010) per side. D 0.36 0.56 F 1.14 1.78 G 2.54 H 7.62 J 0° 10° K 2.92 3.81 L 7.62 8.26 M 0.2 0.36 N 0.38 D SUFFIX SOIC (MS - 012AB) Dimension, mm A 14 8 H B 1 G P 7 R x 45 C -TK D SEATING PLANE M Symbol MIN MAX A 8.55 8.75 B 3.8 4 C 1.35 1.75 D 0.33 0.51 F 0.4 1.27 G 1.27 H 5.27 J 0° 8° K 0.1 0.25 1. Dimensions A and B do not include mold flash or protrusion. M 0.19 0.25 2. Maximum mold flash or protrusion 0.15 mm (0.006) per side for A; for B ‑ 0.25 mm (0.010) per side. P 5.8 6.2 R 0.25 0.5 J 0.25 (0.010) M T C M NOTES: F 6