SMSC LPC47N217N-ABZJ

LPC47N217N
56-Pin Super I/O with
LPC Interface
PRODUCT FEATURES
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Data Brief
3.3 Volt Operation (5V tolerant)
Programmable Wakeup Event Interface (IO_PME#
Pin)
SMI Support (IO_SMI# Pin)
GPIOs (13)
Two IRQ Input Pins
XNOR Chain
PC2001
ACPI 2.0 Compliant
56-pin QFN Lead-free RoHS Compliant package
Intelligent Auto Power Management
Serial Port
— One Full Function Serial Port
— High Speed 16C550A Compatible UART with
Send/Receive 16-Byte FIFO
— Supports 230k and 460k Baud
— Programmable Baud Rate Generator
— Modem Control Circuitry
— Multiple Base I/O Address options and 15 IRQ Options
SMSC LPC47N217N 56QFN
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Multi-Mode Parallel Port with ChiProtect™
— Standard Mode IBM PC/XT®, PC/AT®, and PS/2™
Compatible Bidirectional Parallel Port
— Enhanced Parallel Port (EPP) Compatible - EPP 1.7
and EPP 1.9 (IEEE 1284 Compliant)
— IEEE 1284 Compliant Enhanced Capabilities Port
(ECP)
— ChiProtect Circuitry for Protection Against Damage Due
to Printer Power-On
— 192 Base I/O Address, 15 IRQ and 3 DMA Options
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LPC Bus Host Interface
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Multiplexed Command, Address and Data Bus
8-Bit I/O Transfers
8-Bit DMA Transfers
16-Bit Address Qualification
Serial IRQ Interface Compatible with Serialized IRQ
Support for PCI Systems
— PCI CLKRUN# Support
— Power Management Event (IO_PME#) Interface Pin
PRODUCT PREVIEW
Revision 0.3 (09-16-09)
56-Pin Super I/O with LPC Interface
ORDER NUMBER(S):
LPC47N217N-ABZJ for 56-pin QFN Lead-free ROHS Compliant package
LPC47N217N-ABZJ-TR for 56-pin QFN Lead-free ROHS Compliant package (tape and reel)
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123
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Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for
construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC
reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications
before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent
rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated
version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors
known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not
designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property
damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of
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TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 0.3 (09-16-09)
2
PRODUCT PREVIEW
SMSC LPC47N217N 56QFN
56-Pin Super I/O with LPC Interface
General Description
The SMSC LPC47N217N is a 3.3V PC 99, PC2001, and ACPI 2.0 compliant Super I/O Controller. The
LPC47N217N implements the LPC interface, a pin reduced ISA interface which provides the same or
better performance as the ISA/X-bus with a substantial savings in pins used. The part also includes
13 GPIO pins.
The LPC47N217N incorporates a 16C550A compatible UART and one Multi-Mode parallel port with
ChiProtect™ circuitry plus EPP and ECP support. The LPC47N217N is easy to use and offers lower
system cost and reduced board area.
The LPC47N217N offers a full 16-bit internally decoded address bus, a Serial IRQ interface with PCI
CLKRUN# support, relocatable configuration ports, and three DMA channel options.
The parallel port is compatible with IBM PC/AT architectures, as well as IEEE 1284 EPP and ECP. The
parallel port ChiProtect™ circuitry prevents damage caused by an attached powered printer when the
LPC47N217N is not powered.
The LPC47N217N features Software Configurable Logic (SCL) for ease of use. SCL allows
programmable system configuration of key functions such as the parallel port and UART.
The LPC47N217N supports the ISA Plug-and-Play Standard register set (Version 1.0a) and provides
the recommended functionality to support Windows operating systems, PC99, and PC2001. The I/O
Address, DMA Channel, and Hardware IRQ of each device in the LPC47N217N may be reprogrammed
through the internal configuration registers. There are multiple I/O address location options, a
Serialized IRQ interface, and three DMA channels.
SMSC LPC47N217N 56QFN
3
PRODUCT PREVIEW
Revision 0.3 (09-16-09)
56-Pin Super I/O with LPC Interface
Block Diagram
PD[0:7],
IO_SMI#*
IO_PME#
MULTI-MODE
PARALLEL
PORT
SMI PME WDT
CONTROL, ADDRESS, DATA
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ#
PCI_RESET#
SERIAL
IRQ
IRQIN1*, IRQIN2*
ACPI
BLOCK
CONFIGURATION
REGISTERS
nSLCTIN, nALF
nINIT, nSTROBE
GP10, GP11,
GP12*, GP13*,
GP14*,
GP23,
GP4[1:7]
GENERAL
PURPOSE
I/O
SER_IRQ
PCI_CLK
BUSY, SLCT,
PE, nERROR, nACK
TXD1, nRTS1, nDTR1
16C550
COMPATIBLE
SERIAL
PORT 1
LPC BUS
INTERFACE
nCTS1, RXD1,
nDSR1, nDCD1, nRI1
LPCPD#
CLKRUN#
CLOCK
GEN
V TR Vcc GND
CLOCKI
* Denotes Multifunction Pins
Figure 1 LPC47N217N Block Diagram
Revision 0.3 (09-16-09)
4
PRODUCT PREVIEW
SMSC LPC47N217N 56QFN
56-Pin Super I/O with LPC Interface
Package Outline
REVISION HISTORY
REVISION
D
D2
D1
A
e
TERMINAL #1
IDENTIFIER AREA
(D/2 X E/2)
B
3
DESCRIPTION
DATE
INITIAL RELEASE
2/07/04
S.K.ILIEV
REMOVE "PRELIMINARY" NOTE
10/7/04
S.K.ILIEV
7/2/05
S.K.ILIEV
L(MAX) FROM 0.55 TO 0.50. ADDED D2/E2 VARIATIONS TABLE
C
RELEASED BY
3
TERMINAL #1
IDENTIFIER AREA
(D1/2 X E1/2)
E1
E
E2
EXPOSED PAD
2
56X L
56X b 2
4X 45°X0.6 MAX (OPTIONAL)
TOP VIEW
BOTTOM VIEW
A2
A
A1
SIDE VIEW
D2 / E2 VARIATIONS
CATALOG PART
NOTES:
1. ALL DIMENSIONS ARE IN MILLIMETER.
2. POSITION TOLERANCE OF EACH TERMINAL AND EXPOSED PAD IS ± 0.05mm AT MAXIMUM MATERIAL
CONDITION. DIMENSIONS "b" APPLIES TO PLATED TERMINALS AND IT IS MEASURED BETWEEN 0.15 AND
0.30 mm FROM THE TERMINAL TIP.
3. DETAILS OF TERMINAL #1 IDENTIFIER ARE OPTIONAL BUT MUST BE LOCATED WITHIN THE AREA INDICATED.
UNLESS OTHERWISE SPECIFIED
DIMENSIONS ARE IN MILLIMETERS
AND TOLERANCES ARE:
DECIMAL
X.X
±0.1
X.XX ±0.05
X.XXX ±0.025
THIRD ANGLE PROJECTION
80 ARKAY DRIVE
HAUPPAUGE, NY 11788
USA
ANGULAR
±1°
TITLE
NAME
DIM AND TOL PER ASME Y14.5M - 1994
MATERIAL
3-D VIEWS
FINISH
-
PRINT WITH "SCALE TO FIT"
DO NOT SCALE DRAWING
DATE
DRAWN
S.K.ILIEV
2/06/04
CHECKED
S.K.ILIEV
STD COMPLIANCE
SCALE
2/07/04
REV
MO-56-QFN-8x8
2/07/04
APPROVED
S.K.ILIEV
PACKAGE OUTLINE
56 TERMINAL QFN, 8x8mm BODY, 0.5mm PITCH
DWG NUMBER
1:1
JEDEC: MO-220
C
SHEET
1 OF 1
Figure 2 LPC47N217N 56-Pin QFN Package, 8x8mm Body, 0.5mm Pitch
SMSC LPC47N217N 56QFN
5
PRODUCT PREVIEW
Revision 0.3 (09-16-09)