LINER LTC1405CGN

Final Electrical Specifications
LTC1405
12-Bit, 5Msps,
Sampling ADC
January 2000
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DESCRIPTIO
FEATURES
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5Msps Sample Rate
Low Power Dissipation: 115mW
Single 5V Supply or ±5V Supplies
Integral Nonlinearity Error <0.35LSB
Differential Nonlinearity <0.25LSB
71.3dB S/(N + D) and 85dB SFDR at Nyquist
100MHz Full-Power Bandwidth Sampling
±2.048V, ±1.024V and ±0.512V Bipolar Input Range
Input PGA
Out-of-Range Indicator
True Differential Inputs with 75dB CMRR
28-Pin Narrow SSOP Package
Pin-Compatible 10Msps Version (LTC1420)
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APPLICATIO S
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Telecommunications
Digital Signal Processing
Multiplexed Data Acquisition Systems
High Speed Data Acquisition
Spectral Analysis
Imaging Systems
The LTC®1405 is a 5Msps, 12-bit sampling A/D converter
that draws only 115mW from either single 5V or dual ±5V
supplies. This easy-to-use device includes a high dynamic
range sample-and-hold, a precision reference and a PGA
input circuit.
The LTC1405 has a flexible input circuit that allows fullscale input ranges of ±2.048V, ±1.024V and ±0.512V. The
input common mode range is rail-to-rail and a common
mode bias voltage is provided for single supply applications. The input PGA has a digitally selectable 1x or 2x
gain.
Maximum DC specs include ±1LSB INL and ±1LSB DNL
over temperature. Outstanding AC performance includes
71.3dB S/(N + D) and 85dB SFDR at the Nyquist input
frequency of 2.5MHz.
The unique differential input sample-and-hold can acquire
single-ended or differential input signals up to its 100MHz
bandwidth. The 75dB common mode rejection allows
users to eliminate ground loops and common mode noise
by measuring signals differentially from the source. A
separate output logic supply allows direct connection to
3V components.
, LTC and LT are registered trademarks of Linear Technology Corporation.
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TYPICAL APPLICATIO
5V
5V
Typical INL Curve
5V
1µF
1µF
1µF
OPTIONAL 3V
LOGIC SUPPLY
1.00
0.75
DVDD
OVDD
0.50
+ AIN
S/H
PIPELINED 12-BIT ADC
OF
–AIN
D11 (MSB)
OUTPUT
BUFFERS
VCM
1µF
MODE SELECT
INL (LSBs)
AVDD
GAIN
0.25
0
–0.25
–0.50
–0.75
DIGITAL CORRECTION
LOGIC
D0 (LSB)
–1.00
SENSE
5MHz CLK
2.5V
REFERENCE
0
1024
2048
CODE
3072
4096
1405 TA02
VREF
1µF
2.048V
1405 TA01
VSS
1µF
AGND
DGND
OGND
0V OR –5V
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However,
no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the
interconnection of its circuits as described herein will not infringe on existing patent rights.
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LTC1405
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
AVDD = DVDD = 0VDD = VDD (Notes 1, 2)
TOP VIEW
Supply Voltage (VDD) ................................................. 6V
Negative Supply Voltage (VSS) ................................ – 6V
Total Supply Voltage (VDD to VSS) ........................... 12V
Analog Input Voltage
(Note 3) ............................. (VSS – 0.3V) to (VDD + 0.3V)
Digital Input Voltage
(Note 4) ............................. (VSS – 0.3V) to (VDD + 0.3V)
Digital Output Voltage ........ (VSS – 0.3V) to (VDD + 0.3V)
Power Dissipation .............................................. 500mW
Operating Temperature Range
LTC1405C ............................................... 0°C to 70°C
LTC1405I ............................................ – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 150°C
Lead Temperature (Soldering, 10 sec).................. 300°C
+AIN
1
28 GAIN
–AIN
2
27 OF
VCM
3
26 CLK
SENSE
4
25 VSS
VREF
5
24 DGND
AGND
6
23 DVDD
AVDD
7
22 OVDD
AGND
8
21 OGND
D11 (MSB)
9
20 D0
D10 10
19 D1
D9 11
18 D2
D8 12
17 D3
D7 13
16 D4
D6 14
15 D5
ORDER PART
NUMBER
LTC1405CGN
LTC1405IGN
GN PACKAGE
28-LEAD PLASTIC SSOP
TJMAX = 110°C, θJA = 110°C/W
Consult factory for Military grade parts.
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CO VERTER CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C.
With Internal 4.096V Reference. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER
CONDITIONS
Resolution (No Missing Codes)
Integral Linearity Error
●
(Note 7)
Differential Linearity Error
Offset Error
MIN
TYP
UNITS
12
Bits
●
±0.35
±1
LSB
●
±0.25
±1
LSB
±5
12
16
LSB
LSB
±10
30
LSB
(Note 8)
●
Full-Scale Error
Full-Scale Tempco
MAX
±15
IOUT(REF) = 0
ppm/°C
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A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIN
Analog Input Range (Note 9)
+AIN – (–AIN)
VREF = 4.096V (SENSE = 0V), GAIN = 5V
VREF = 4.096V (SENSE = 0V), GAIN = 0V
VREF = 2.048V (SENSE = VREF), GAIN = 5V
VREF = 2.048V (SENSE = VREF), GAIN = 0V
External VREF (SENSE = 5V), GAIN = 5V
External VREF (SENSE = 5V), GAIN = 0V
IIN
Analog Input Leakage Current
CIN
Analog Input Capacitance
tACQ
Sample-and-Hold Acquisition Time
2
MIN
●
●
●
●
●
●
TYP
UNITS
V
V
V
V
V
V
±10
●
Between Conversions
During Conversions
MAX
±2.048
±1.024
±1.024
±0.512
±VREF/2
±VREF/4
µA
12
6
pF
pF
50
ns
LTC1405
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A ALOG I PUT The ● denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
SYMBOL
PARAMETER
tAP
Sample-and-Hold Aperture Delay Time
CONDITIONS
tjitter
Sample-and-Hold Aperture Delay Time Jitter
CMRR
Analog Input Common Mode Rejection Ratio
MIN
TYP
MAX
UNITS
– 250
–2.048V < (–AIN = +AIN) < 2.048V
ps
0.6
ps
75
dB
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DY A IC ACCURACY
The ● denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. VDD = 5V, VSS = – 5V, fSAMPLE = 5MHz, VREF = 4.096V. + AIN = – 0.1dBFS single ended input,
– AIN = 0V. (Note 6)
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
69.0
68.7
71.6
71.3
S/(N + D)
Signal-to-Noise Plus Distortion Ratio
1MHz Input Signal
2.5MHz Input Signal
●
●
THD
Total Harmonic Distortion
1MHz Input Signal, First 5 Harmonics
2.5MHz Input Signal, First 5 Harmonics
●
●
– 87
– 83
– 78.5
– 77.0
dB
dB
SFDR
Peak Harmonic or Spurious Noise
1MHz Input Signal
2.5MHz Input Signal
●
●
– 89
– 85
– 79.5
– 78.0
dB
dB
IMD
Intermodulation Distortion
fIN1 = 29.37kHz, fIN2 = 32.446kHz
Full-Power Bandwidth
±2.048V Input Range
±1.024V Input Range, 2x Mode (SENSE = GAIN = 0V)
Input Referred Noise
MAX
UNITS
dB
dB
– 80
dB
100
MHz
0.22
0.33
LSBRMS
LSBRMS
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I TER AL REFERE CE CHARACTERISTICS
TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation. (Note 5)
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
VCM Output Voltage
IOUT = 0
2.475
2.500
2.525
VCM Output Tempco
IOUT = 0
±15
ppm/°C
VCM Line Regulation
4.75V ≤ VDD ≤ 5.25V
– 5.25V ≤ VSS ≤ –4.75V
0.6
0.03
mV/V
mV/V
VCM Output Resistance
0.1mA ≤ IOUT ≤ 0.1mA
VREF Output Voltage
SENSE = GND, IOUT = 0
SENSE = VREF, IOUT = 0
SENSE = VDD
V
8
Ω
4.096
2.048
Drive VREF with
External Reference
V
V
V
±15
VREF Output Tempco
ppm/°C
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DIGITAL I PUTS AND OUTPUTS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
VIH
High Level Input Voltage
VDD = 5.25V, VSS = 0V
VDD = 5.25V, VSS = – 5V
●
●
MIN
VIL
Low Level Input Voltage
VDD = 4.75V, VSS = 0V
VDD = 4.75V, VSS = – 5V
●
●
TYP
MAX
2.4
3.5
UNITS
V
V
0.8
1
V
V
3
LTC1405
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DIGITAL I PUTS AND OUTPUTS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply
operation. (Note 5)
SYMBOL
PARAMETER
CONDITIONS
IIN
Digital Input Current
VIN = 0V to VDD
CIN
Digital Input Capacitance
VOH
High Level Output Voltage
VOL
MIN
●
0VDD = 4.75V, IO = –10µA
0VDD = 4.75V, IO = –200µA
0VDD = 2.7V, IO = –10µA
0VDD = 2.7V, IO = –200µA
Low Level Output Voltage
TYP
0VDD = 4.75V, IO = 160µA
0VDD = 4.75V, IO = 1.6mA
0VDD = 2.7V, IO = 160µA
0VDD = 2.7V, IO = 1.6mA
●
4.0
●
2.3
●
UNITS
±10
µA
1.8
pF
4.74
4.71
2.6
V
V
V
V
0.05
0.10
0.05
0.10
●
MAX
V
V
V
V
0.4
0.4
ISOURCE
Output Source Current
VOUT = 0V
50
mA
ISINK
Output Sink Current
VOUT = VDD
35
mA
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POWER REQUIRE E TS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
MIN
VDD
Positive Supply Voltage
(Note 10)
VSS
Negative Supply Voltage
Dual Supply Mode
Single Supply Mode
TYP
MAX
UNITS
4.75
5.25
V
– 5.25
– 4.75
V
V
0
IDD
Positive Supply Current
●
23
28
mA
ISS
Negative Supply Current
●
0.8
1.2
mA
PD
Power Dissipation
●
115
145
mW
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TI I G CHARACTERISTICS
The ● denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. Specifications are guaranteed for both dual supply and single supply operation.
(Note 5)
SYMBOL
PARAMETER
CONDITIONS
fSAMPLE
Sampling Frequency
●
tCONV
Conversion Time
●
tACQ
Acquisition Time
●
20
50
ns
tH
CLK High Time
(Note 9)
●
20
100
ns
tL
CLK Low Time
(Note 9)
●
20
100
ns
tAD
Aperture Delay of Sample-and-Hold
– 250
ps
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: All voltage values are with respect to ground with GND and OGND
wired together (unless otherwise noted).
Note 3: When these pin voltages are taken below VSS or above VDD, they
will be clamped by internal diodes. This product can handle input currents
greater than 100mA below VSS or above VDD without latchup.
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MIN
TYP
MAX
150
180
0.02
5
UNITS
MHz
ns
Note 4: When these pin voltages are taken below VSS they will be clamped
by internal diodes. This product can handle input currents greater than
100mA below VSS without latchup. GAIN is not clamped to VDD. When CLK
is taken above VDD, it will be clamped by an internal diode. The CLK pin
can handle input currents of greater than 100mA above VDD without
latchup.
Note 5: VDD = 5V, VSS = – 5V or 0V, fSAMPLE = 5MHz, tr = tf = 5ns unless
otherwise specified.
LTC1405
ELECTRICAL CHARACTERISTICS
Note 6: Dynamic specifications are guaranteed for dual supply operation
with a single-ended + AIN input and – AIN grounded. For single supply
dynamic specifications, refer to the Typical Performance Characteristics.
Note 7: Integral nonlinearity is defined as the deviation of a code from a
straight line passing through the actual endpoints of the transfer curve.
The deviation is measured from the center of the quantization band.
Note 8: Bipolar offset is the offset voltage measured from –0.5LSB
when the output code flickers between 0000 0000 0000 and
1111 1111 1111.
Note 9: Guaranteed by design, not subject to test.
Note 10: Recommended operating conditions.
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PI FU CTIO S
+ AIN (Pin 1): Positive Analog Input.
OGND (Pin 21): Output Logic Ground. Tie to GND.
– AIN (Pin 2): Negative Analog Input.
OVDD (Pin 22): Positive Supply for the Output Logic.
Connect to Pin 23 for 5V logic. If not shorted to Pin 23,
bypass to GND with a 1µF ceramic.
VCM (Pin 3): 2.5V Reference Output.Optional input common mode for single supply operation. Bypass to GND
with a 1µF to 10µF ceramic.
SENSE (Pin 4): Reference Programming Pin. Ground
selects VREF = 4.096V. Short to VREF for 2.048V. Connect
SENSE to VDD to drive VREF with an external reference.
VREF (Pin 5): DAC Reference. Bypass to GND with a 1µF to
10µF ceramic.
VDD (Pin 23): Analog 5V Supply. Bypass to GND with a 1µF
ceramic.
GND (Pin 24): Analog Power Ground.
VSS (Pin 25): Negative Supply. Can be – 5V or 0V. If VSS is
not shorted to GND, bypass to GND with a 1µF ceramic.
GND (Pin 6): DAC Reference Ground.
CLK (Pin 26): Conversion Start Signal. This active high
signal starts a conversion on its rising edge.
VDD (Pin 7): Analog 5V Supply. Bypass to GND with a 1µF
to 10µF ceramic.
OF (Pin 27): Overflow Output. This signal is high when the
digital output is 011111111111 or 100000000000.
GND (Pin 8): Analog Power Ground.
GAIN (Pin 28): Gain Select for Input PGA. 5V selects an
input gain of 1, 0V selects a gain of 2.
D11 to D0 (Pins 9 to 20): Data Outputs. The output format
is two’s complement.
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LTC1405
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FU CTIO AL BLOCK DIAGRA
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OPTIONAL 3V
LOGIC SUPPLY
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5V
VDD
(PIN 7)
GAIN
VDD
(PIN 23)
OVDD
+ AIN
S/H
PIPELINED 12-BIT ADC
OF
–AIN
D11 (MSB)
OUTPUT
BUFFERS
VCM
DIGITAL CORRECTION
LOGIC
MODE SELECT
D0 (LSB)
SENSE
CLK
2.5V
REFERENCE
VREF
2.048V
1405 FBD
VSS
GND
(PIN 6)
0V OR –5V
GND
(PIN 8)
GND
(PIN 24)
OGND
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TI I G DIAGRA
N+1
ANALOG
INPUT
N
N+2
tCLOCK
tH
N+3
tL
CLK
tCONV
tACQ
DATA
OUTPUT
N–3
N–2
N–1
N
1405 TD
6
LTC1405
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APPLICATIO S I FOR ATIO
Conversion Details
Analog Input Ranges
The LTC1405 is a high performance 12-bit A/D converter
that operates up to 5Msps. It is a complete solution with
an on-chip sample-and-hold, a 12-bit pipelined CMOS
ADC, a low drift programmable reference and an input
programmable gain amplifier. The digital output is parallel, with a 12-bit two’s complement output and an out-ofrange (overflow) bit.
The LTC1405 has a flexible analog input with a wide
selection of input ranges. The input range is always
differential and is set by the voltages at the VREF and the
GAIN pins (Figure 1). The input range of the A/D core is
fixed at ±VREF/2. The reference voltage, VREF, is either set
by the on-chip voltage reference or directly driven by an
external voltage. The GAIN pin is a digital input that
controls the gain of a preamplifier in the sample-and-hold
circuit. The gain of this PGA can be set to 1x or 2x. Table 1
gives the input range in terms of VREF and GAIN.
The rising edge of the CLK begins a conversion. The
differential analog inputs are simultaneously sampled and
passed on to the pipelined A/D. After two more conversion
starts (plus a 150ns conversion time) the digital outputs
are updated with the conversion result and will be ready for
capture on the third rising clock edge. Thus even though
a new conversion is begun every time CLK goes high, each
result takes three clock cycles to reach the output.
The analog signals that are passed from stage to stage in
the pipelined A/D are stored on capacitors. The signals on
these capacitors will be lost if the delay between conversions is too long. For accurate conversion results, the part
should be clocked faster than 20kHz.
In some pipelined A/D converters if there is no clock
present, dynamic logic on the chip will droop and the
power consumption sharply increases. The LTC1405
doesn’t have this problem. If the part is not clocked for
1ms, an internal timer will refresh the dynamic logic. Thus
the clock can be turned off for long periods of time to save
power.
Power Supplies
The LTC1405 will operate from either a single 5V or dual
±5V supply, making it easy to interface the analog input to
single or dual supply systems. The digital output drivers
have their own power supply pin (OVDD) which can be set
from 3V to 5V, allowing direct connection to either 3V or
5V digital systems. For single supply operation, VSS should
be connected to analog ground. For dual supply operation,
VSS should be connected to – 5V. Both VDD pins should be
connected to a clean 5V analog supply. (Don’t connect VDD
to a noisy system digital supply.)
Table 1
PGA GAIN
INPUT RANGE
(VIN = AIN + – AIN –)
5V (Logic H)
1x
– VREF/2 < VIN < VREF/2
OV (Logic L)
2x
– VREF/4 < VIN < VREF/4
GAIN PIN
GAIN
1x/2x
+
VIN
–
+AIN
–AIN
PGA
S/H
±VREF/2
VREF
ADC
CORE
1405 F01
Figure 1. Analog Input Circuit
Internal Reference
Figure 2 shows a simplified schematic of the LTC1405
reference circuitry. An on-chip temperature compensated
bandgap reference (VCM) is factory trimmed to 2.500V.
The voltage at the VREF pin sets the input span of the ADC
to ±VREF/2. An internal voltage divider converts VCM to
2.048V, which is connected to a reference amplifier. The
reference programming pin, SENSE, controls how the
reference amplifier drives the VREF pin. If SENSE is tied to
ground, the reference amplifier feedback is connected to
the R1/R2 voltage divider, thus making VREF = 4.096V. If
SENSE is tied to VREF, the reference amplifier feedback is
connected to SENSE thus making VREF = 2.048V. If SENSE
is tied to VDD, the reference amplifier is disconnected from
VREF and VREF can be driven by an external voltage. With
two additional resistors, VREF can be set to any voltage
between 2.048V and 4.5V.
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LTC1405
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APPLICATIO S I FOR ATIO
An external reference or a DAC can be used to drive VREF
over a 0V to 5V range (Figures 3a and 3b). The input
impedance of the VREF pin is 2kΩ, so a buffer may be
required for high accuracy. Driving VREF with a DAC is
useful in applications where the peak input signal amplitude may vary. The input span of the ADC can then be
adjusted to match the peak input signal, maximizing the
signal-to-noise ratio.
Both the VCM and VREF pins must be bypassed with
capacitors to ground. For best performance, 1µF or larger
ceramic capacitors are recommended. For the case of
external circuitry driving VREF, a smaller capacitor can be
used at VREF so the input range can be changed quickly. In
this case, a 0.05µF or larger ceramic capacitor is acceptable.
TO
ADC
VREF
1µF
+
R1
10k
–
SENSE
R2
10k
LOGIC
2.5V
REFERENCE
2.048V
VCM
1µF
1405 F02
The VCM pin is a low output impedance 2.5V reference that
can be used by external circuitry. For single 5V supply
applications it is convenient to connect AIN – directly to the
VCM pin.
Figure 2. Reference Circuit
5V
Driving the Analog Inputs
The differential inputs of the LTC1405 are easy to drive.
The inputs may be driven differentially or single-ended
(i. e., the AIN – input is held at a fixed value). The AIN – and
AIN + inputs are simultaneously sampled and any common
mode signal is reduced by the high common mode rejection of the sample-and-hold circuit. Any common mode
input value is acceptable as long as the input pins stay
between VDD and VSS. During conversion the analog
inputs are high impedance. At the end of conversion the
inputs draw a small current spike while charging the
sample-and-hold.
VIN
VOUT
LT1019A-2.5
VREF
1µF
5V
LTC1405
SENSE
VCM
1µF
1405 F03a
Figure 3a. Using the LT1019-2.5 As an
External Reference; Input Range = ±1.25V
For superior dynamic performance in dual supply mode,
the LTC1405 should be operated with the analog inputs
centered at ground, and in single supply mode the inputs
should be centered at 2.5V. If required, the analog inputs
can be driven differentially via a transformer. Refer to
Table 2 for a summary of the analog input and reference
configurations and their relative advantages.
LTC1405
+
2.048V
VREF
5k
–
1µF
SENSE
5k
LTC1450
VCM
1µF
Figure 3b. Driving VREF with a DAC
8
2k
1405 F03b
LTC1405
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APPLICATIO S I FOR ATIO
Table 2. Comparison of Analog Input Configurations
SUPPLIES
COUPLING
VREF
AIN +
GAIN
AIN –
COMMENTS
±5V
DC
4.096V
1x
±2.048
0
5V
DC
4.096V
2x
2.5 ± 1.024
2.5
Best SINAD, THD for Single Supply
5V
DC
2.048V
1x
2.5 ± 1.024
2.5
Worse Noise than Above Case
Best SNR, THD
5V
DC
4.096V
1x
2.5 ± 2.048
2.5
5V
DC
4.096V
1x
0 to 4.096
2.048
Same As Above
±5V
AC
(Transformer)
4.096V
1x
±1.024
±1.024
Very Best SNR, THD
5V
AC
(Transformer)
4.096V
1x
2.5 ± 1.024
2.5 ± 1.024
Best Single Supply Noise, THD Is Not Optimal
Very Best SNR, THD for Single Supply
5V
DC Coupling the Input
In most applications the analog input signal can be directly
coupled to the LTC1405 inputs. If the input signal is
centered around ground, such as when dual supply op
amps are used, simply connect AIN – to ground and connect VSS to – 5V (Figure 4). In a single power supply
system with the input signal centered around 2.5V, connect AIN – to VCM and VSS to ground (Figure 5). If the input
signal is not centered around ground or 2.5V, the voltage
for AIN – must be generated externally by a resistor divider
or a voltage reference (Figure 6).
4.096V
+AIN
VIN
0V
LTC1405
2.048V
5V
–AIN
SENSE
VSS
1405 F06
Figure 6. DC Coupling a 0V to 4.096V Signal
AC Coupling the Input
5V
0V
+AIN
VIN
LTC1405
–AIN
VCM
1µF
VSS
1405 F04
–5V
Figure 4. DC Coupling a Ground
Centered Signal (Dual Supply System)
The analog inputs to the LTC1405 can also be AC coupled
through a capacitor, though in most cases it is simpler to
directly couple the input to the ADC. Figure 7 shows an
example where the input signal is centered around ground
and the ADC operates from a single 5V supply. Note that
the performance would improve if the ADC was operated
from a dual supply and the input was directly coupled (as
in Figure 4). With AC coupling the DC resistance to ground
should be roughly matched for AIN + and AIN – to maintain
offset accuracy.
5V
5V
C
2.5V
+AIN
VIN
0V
+AIN
VIN
LTC1405
LTC1405
–AIN
–AIN
R
VCM
1µF
R
C
VCM
VSS
1405 F05
Figure 5. DC Coupling a Signal Centered
Around 2.5V (Single Supply System)
1µF
VSS
1405 F07
Figure 7. AC Coupling to the LTC1405. Note That the Input Signal
Can Almost Always Be Directly Coupled with Better Performance
9
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Differential Operation
The THD and SFDR performance of the LTC1405 can be
improved by using a center tap RF transformer to drive the
inputs differentially. Though the signal can no longer be
DC coupled, the improvement in dynamic performance
makes this an attractive solution for some applications.
Typical connections for single and dual supply systems
are shown in Figures 8a and 8b. Good choices for transformers are the Mini Circuits T1-1T (1:1 turns ratio) and
T4-6T (1:4 turns ratio). For best results the transformer
should be located close to the LTC1405 on the printed
circuit board.
5V
MINI CIRCUITS
T1-1T
VIN
15Ω
+AIN
1000pF
15Ω
LTC1405
–AIN
VCM
1µF
VSS
1405 F08a
Figure 8a. Single Supply Transformer Coupled Input
5V
MINI CIRCUITS
T1-1T
VIN
15Ω
+AIN
1000pF
15Ω
LTC1405
–AIN
VCM
1µF
VSS
1405 F08b
–5V
Figure 8b. Dual Supply Transformer Coupled Input
Choosing an Input Amplifier
Choosing an input amplifier is easy if a few requirements
are taken into consideration. First, to limit the magnitude
of the voltage spike seen by the amplifier from charging
the sampling capacitor, choose an amplifier that has a low
output impedance (<100Ω) at the closed-loop bandwidth
frequency. For example, if an amplifier is used in a gain of
1 and has a unity-gain bandwidth of 50MHz, then the
output impedance at 50MHz must be less than 100Ω. The
second requirement is that the closed-loop bandwidth
10
must be greater than 50MHz to ensure adequate smallsignal settling for full throughput rate. If slower op amps
are used, more settling time can be provided by increasing
the time between conversions.
The best choice for an op amp to drive the LTC1405 will
depend on the application. Generally applications fall into
two categories: AC applications where dynamic specifications are most critical and time domain applications where
DC accuracy and settling time are most critical.
Input Filtering
The noise and the distortion of the input amplifier and
other circuitry must be considered since they will add to
the LTC1405 noise and distortion. The small-signal bandwidth of the sample-and-hold circuit is 100MHz. Any noise
or distortion products that are present at the analog inputs
will be summed over this entire bandwidth. Noisy input
circuitry should be filtered prior to the analog inputs to
minimize noise. A simple 1-pole RC filter is sufficient for
many applications.
For example, Figure 9 shows a 1000pF capacitor from
+ AIN to – AIN and a 30Ω source resistor to limit the input
bandwidth to 5.3MHz. The 1000pF capacitor also acts as
a charge reservoir for the input sample-and-hold and
isolates the amplifier driving VIN from the ADC’s small
current glitch. In undersampling applications, an input
capacitor this large may prohibitively limit the input bandwidth. If this is the case, use as large an input capacitance
as possible. High quality capacitors and resistors should
be used since these components can add distortion. NPO
and silver mica type dielectric capacitors have excellent
linearity. Carbon surface mount resistors can generate
distortion from self-heating and from damage that may
occur during soldering. Metal film surface mount resistors are much less susceptible to both problems.
30Ω
+AIN
VIN
1000pF
LTC1405
–AIN
1405 F09
Figure 9. RC Input Filter
LTC1405
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Digital Outputs and Overflow Bit (OF)
Figure 10 shows the ideal input/output characteristics for
the LTC1405. The output data is two’s complement binary
for all input ranges and for both single and dual supply
operation. One LSB = VREF/4.096. To create a straight
binary output, invert the MSB (D11). The overflow bit (OF)
indicates when the analog input is outside the input range
of the converter. OF is high when the output code is 1000
0000 0000 or 0111 1111 1111.
noise from affecting performance, the load capacitance on
the digital outputs should be minimized. If large capacitive
loads are required, (>30pF) external buffers or 100Ω
resistors in series with the digital outputs are suggested.
5V
VIN
5V
R1
50k
24k
+AIN
LTC1405
–AIN
100Ω
–5V
1 OVERFLOW
0 BIT
VREF
011…111
1µF
10k
011…110
R2
1k
OUTPUT CODE
011…101
SENSE
VSS
1405 F11
10k
–5V
Figure 11. Offset and Full-Scale Adjust Circuit
100…010
Timing
100…001
100…000
–(FS – 1LSB)
FS – 1LSB
INPUT VOLTAGE (V)
1405 F10
Figure 10. LTC1405 Transfer Characteristics
Full-Scale and Offset Adjustment
In applications where absolute accuracy is important,
offset and full-scale errors can be adjusted to zero. Offset
error should be adjusted before full-scale error. Figure 11
shows a method for error adjustment for a dual supply,
4.096V application. For zero offset error apply – 0.5mV
(i. e., – 0.5LSB) at + AIN and adjust R1 until the output code
flickers between 0000 0000 0000 and 1111 1111 1111.
For full-scale adjustment, apply an input voltage of 2.0465V
(FS – 1.5LSBs) at + AIN and adjust R2 until the output code
flickers between 0111 1111 1110 and 0111 1111 1111.
Digital Output Drivers
The LTC1405 output drivers can interface to logic operating from 3V to 5V by setting OVDD to the logic power
supply. If 5V output is desired, OVDD can be shorted to VDD
and share its decoupling capacitor. Otherwise, OVDD requires its own 1µF decoupling capacitor. To prevent digital
The conversion start is controlled by the rising edge of the
CLK pin. Once a conversion is started it cannot be stopped
or restarted until the conversion cycle is complete. Output
data is updated at the end of conversion, or about 150ns
after a conversion is begun. There is an additional two
cycle pipeline delay, so the data for a given conversion is
output two full clock cycles plus 150ns after the convert
start. Thus output data can be latched on the third CLK
rising edge after the rising edge that samples the input.
Clock Input
The LTC1405 only uses the rising edge of the CLK pin for
internal timing, and CLK doesn’t necessarily need to have
a 50% duty cycle. For optimal AC performance the rise
time of the CLK should be less than 5ns. If the available
clock has a rise time slower than 5ns, it can be locally sped
up with a logic gate. With single supply operation the clock
can be driven with 5V CMOS, 3V CMOS or TTL logic levels.
With dual power supplies the clock should be driven with
5V CMOS levels.
As with all fast ADCs, the noise performance of the
LTC1405 is sensitive to clock jitter when high speed inputs
11
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connected to this ground plane. All bypass capacitors for
the LTC1405 should also be connected to this ground
plane (Figure 12). The digital system ground should be
connected to the analog ground plane at only one point,
near the OGND pin.
are present. The SNR performance of an ADC when the
performance is limited by jitter is given by:
SNR = – 20log (2π fIN tJ)dB
where fIN is the frequency of an input sine wave and tJ is
the root-mean-square jitter due to the clock, the analog
input and the A/D aperture jitter. To minimize clock jitter,
use a clean clock source such as a crystal oscillator, treat
the clock signals as sensitive analog traces and use
dedicated packages with good supply bypassing for any
clock drivers.
The analog ground plane should be as close to the ADC as
possible. Care should be taken to avoid making holes in the
analog ground plane under and around the part. To accomplish this, we recommend placing vias for power and
signal traces outside the area containing the part and the
decoupling capacitors (Figure 13).
Board Layout
Supply Bypassing
To obtain the best performance from the LTC1405, a
printed circuit board with a ground plane is required.
Layout for the printed circuit board should ensure that
digital and analog signal lines are separated as much as
possible. In particular, care should be taken not to run any
digital track alongside an analog signal track.
High quality, low series resistance ceramic 1µF capacitors
should be used at both VDD pins, VCM and VREF. If VSS is
connected to – 5V it should also be bypassed to ground
with 1µF. In single supply operation VSS should be shorted
to the ground plane as close to the part as possible. If OVDD
is not shorted to Pin 23 (VDD) it also requires a 1µF
decoupling capacitor to ground. Surface mount capacitors such as the AVX 0805ZC105KAT provide excellent
bypassing in a small board space. The traces connecting
the pins and the bypass capacitors must be kept short and
should be made as wide as possible.
An analog ground plane separate from the logic system
ground should be placed under and around the ADC.
Pins 6, 8 and 24 (GND), Pin 21 (OGND) and all other
analog grounds should be connected to this ground plane.
In single supply mode, Pin 25 (VSS) should also be
1
DIGITAL
SYSTEM
LTC1405
+AIN
1000pF
ANALOG
INPUT
CIRCUITRY
+
–
2
–AIN
VCM
VREF
GND
VDD
GND
3
5
6
7
8
1µF
1µF
1µF
VDD
GND
OVDD
23
1µF
22
OGND
VSS
24
1µF
25
21
1µF
ANALOG GROUND PLANE
1405 F12
Figure 12. Power Supply Grounding
LTC1405
PLACE NON-GROUND
VIAS AWAY FROM
GROUND PLANE AND
BYPASS CAPACITORS
AVOID BREAKING GROUND PLANE
IN THIS AREA
BYPASS
CAPACITOR
ANALOG
GROUND
PLANE
1405 F13
Figure 13. Cross Section of LTC1405 Printed Circuit Board
12
2
5 4 3 2
J2
(J6)
BNC (SMB)
5 4 3 2
J1
(J5)
BNC (SMB)
1 –AIN
1 +AIN
1
2
2
R16
51Ω
OPT
R15
51Ω
OPT
1
28
JP4
JP5
2
2
2
1
JP6
1
26
25
1 GAIN
1
1µF
2
C5
24
23
22
21
20
1 AGND
1
1µF
2
C4
1
1µF
27
2
C12
19
18
17
16
15
1 VDD
1 VSS
1 OVDD
D1
MBR0520LT1
E7
E6
E5
E4
E3
E2
1 OGND
VCC
VCM
–AIN
+AIN
VSS
CLK
OF
GAIN
1
R19
0Ω
2
R18
1 20Ω 2
C6
470pF
U1, LTC1405
VREF
SENSE
DGND
AGND
AVDD
AGND
DVDD
OVDD
OGND
D10
D9
D2
D11 (MSB)
D8
D3
D0
D7
D4
D1
D6
D5
1
2
3
4
5
6
7
8
9
10
11
12
13
14
JP7
2
2
1µF
2
3
2
C8
2
C9
1
2
R20
0Ω
1
0.1µF
1
0.1µF
GND
1Q2
GND
1D2
1C
1OE
1Q1
1Q3
1D3
1D1
1Q4
1D4
1Q5
1D5
VCC
1Q6
1D6
VCC
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
VCC
2Q5
2Q6
GND
2Q7
2Q8
2OE
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
VCC
2D5
2D6
GND
2D7
2D8
2C
U2, 74ACT16373DL
CLOCK
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Figure 14. LTC1405 Demo Board Schematic
1
JP1
JP2
2
2
1
1µF
1
1µF
JP3
1
C3
1
1
1
2
C2
2
C1
VCC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
2
2
0.1µF
2
0.1µF
2
4
R17
51Ω
1
3 U3
NC7S04M5
5
C7
VCC 0.1µF
1
2
1
C10
1
C11
VCC
2 CLK
2 OF
2 D11
2 D11
2 D10
2 D9
2 D8
2 D7
2 D6
2 D5
2 D4
2 D3
2 D2
2 D1
2 3 4 5
J3
(J7)
BNC (SMB)
R14 1
R13 1
R21 1
R12 1
R11 1
R10 1
R9 1
R8 1
R7 1
R6 1
R5 1
R4 1
R3 1
R2 1
100 X 15 PLCS
R1 1
2 D0
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
J4
1405 F14
HD2X8-079
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
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1 VCC
APPLICATIO S I FOR ATIO
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LTC1405
13
LTC1405
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14
Figure 15. Top Silkscreen Layer for
LTC1405/LTC1420 Demo Board
Figure 16. Top Layer for LTC1405/LTC1420 Demo Board
Figure 17. Ground Plane Layer for
LTC1405/LTC1420 Demo Board
Figure 18. Power Plane Layer for LTC1405/LTC1420 Demo Board
LTC1405
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Figure 19. Bottom Layer for LTC1405/LTC1420 Demo Board
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TYPICAL APPLICATIO
Single Supply, 5Msps, 12-Bit ADC with 3V Logic Outputs
LTC1405
30Ω
ANALOG INPUT
(2.5V ± 1.024V)
1
1000pF
NPO
2
3
1µF
4
5
1µF
6
7
5V
1µF
8
9
10
11
12
13
14
+AIN
GAIN
–AIN
OF
VCM
CLK
SENSE
VSS
VREF
GND
GND
VDD
VDD
OVDD
GND
OGND
D11
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
D5
28
27
26
5MHz CLOCK
25
24
23
5V
1µF
22
21
3V
1µF
20
19
18
17
16
0V TO 3V
12-BIT
PARALLEL DATA
PLUS OVERFLOW
15
1405 TA03
15
LTC1405
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TYPICAL APPLICATIO
Dual Supply, 5Msps, 12-Bit ADC with 71.3dB SINAD
LTC1405
30Ω
ANALOG INPUT
(±2.048V)
1
1000pF, NPO
2
3
1µF
4
5
1µF
6
7
5V
1µF
8
9
10
11
12
13
14
+AIN
GAIN
–AIN
OF
VCM
CLK
SENSE
VSS
VREF
GND
GND
VDD
VDD
OVDD
GND
OGND
D11
D0
D10
D1
D9
D2
D8
D3
D7
D4
D6
D5
28
5V
27
26
5MHz CLOCK
25
–5V
1µF
24
23
22
21
5V
1µF
20
19
18
17
12-BIT
PARALLEL DATA
PLUS OVERFLOW
16
15
1405 TA04
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PACKAGE DESCRIPTIO
Dimensions in inches (millimeters) unless otherwise specified.
GN Package
28-Lead Plastic SSOP (Narrow 0.150)
(LTC DWG # 05-08-1641)
0.386 – 0.393*
(9.804 – 9.982)
0.015 ± 0.004
× 45°
(0.38 ± 0.10)
0.0075 – 0.0098
(0.191 – 0.249)
0.053 – 0.069
(1.351 – 1.748)
0.004 – 0.009
(0.102 – 0.249)
28 27 26 25 24 23 22 21 20 19 18 17 1615
0.033
(0.838)
REF
0° – 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.008 – 0.012
(0.203 – 0.305)
0.0250
(0.635)
BSC
* DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
** DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
0.229 – 0.244
(5.817 – 6.198)
0.150 – 0.157**
(3.810 – 3.988)
1
2 3
4
5 6
7
8
9 10 11 12 13 14
GN28 (SSOP) 1098
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LTC1420
12-Bit, 10Msps, Sampling ADC
Pin Compatible with LTC1405
LTC1412
12-Bit, 3Msps, Sampling ADC with Parallel Output
Best Dynamic Performance, SINAD = 72dB at Nyquist
LTC1415
Single 5V, 12-Bit, 1.25Msps with Parallel Output
55mW Power Dissipation, 72dB SINAD
LT1019
Precision Bandgap Reference
0.05% Max Initial Accuracy, 5ppm/°C Max Drift
16
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
1405i LT/TP 0100 4K • PRINTED IN USA
 LINEAR TECHNOLOGY CORPORATION 2000