LINER LTM4603V-1

LTM4603/LTM4603-1
6A DC/DC µModule
with PLL, Output Tracking
and Margining
DESCRIPTIO
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FEATURES
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Complete Switch Mode Power Supply
Wide Input Voltage Range: 4.5V to 20V
6A DC Typical, 8A Peak Output Current
0.6V to 5V Output Voltage
Output Voltage Tracking and Margining
Remote Sensing for Precision Regulation
(LTM4603 Only)
Typical Operating Frequency: 1MHz
PLL Frequency Synchronization
1.5% Regulation
Current Foldback Protection (Disabled at Start-Up)
Pin Compatible with the LTM4601
Pb-Free (e4) RoHS Compliant Package with Gold
Finish Pads
Ultrafast Transient Response
Current Mode Control
Up to 93% Efficiency at 5VIN, 3.3VOUT
Programmable Soft-Start
Output Overvoltage Protection
Small Footprint, Low Profile (15mm × 15mm ×
2.8mm) Surface Mount LGA Package
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APPLICATIO S
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Telecom and Networking Equipment
Servers
Industrial Equipment
Point of Load Regulation
The low profile (2.8mm) and light weight (1.73g) package
easily mounts on the unused space on the back side of
PC boards for high density point of load regulation. The
µModule can be synchronized with an external clock for
reducing undesirable frequency harmonics and allows
PolyPhase® operation for high load currents.
A high switching frequency and adaptive on-time current
mode architecture deliver a very fast transient response
to line and load changes without sacrificing stability. An
onboard remote sense amplifier can be used to accurately
regulate an output voltage independent of load current.
The onboard remote sense amplifier is not available in the
LTM4603-1. The LTM4603/LTM4603-1 are pin compatible
with the 12A LTM4601/LTM4601-1.
, LT, LTC, LTM and PolyPhase are registered trademarks of Linear Technology
Corporation. µModule is a trademark of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
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The LTM®4603 is a complete 6A step-down switch mode
DC/DC power supply with onboard switching controller,
MOSFETs, inductor and all support components. The
µModuleTM is housed in a small surface mount 15mm ×
15mm × 2.8mm LGA package. Operating over an input
voltage range of 4.5 to 20V, the LTM4603 supports an
output voltage range of 0.6V to 5V as well as output voltage
tracking and margining. The high efficiency design delivers 6A continuous current (8A peak). Only bulk input and
output capacitors are needed to complete the design.
TYPICAL APPLICATIO
Efficiency vs Load Current with 12VIN
1.5V/6A Power Supply with 4.5V to 20V Input
1.00
0.95
CLOCK SYNC
TRACK/SS CONTROL
VIN
4.5V TO 20V
0.90
0.85
VIN
PGOOD
ON/OFF
CIN
392k
RUN
COMP
INTVCC
DRVCC
MPGM
SGND
PLLIN TRACK/SS
VOUT
LTM4603
PGND
VFB
MARG0
MARG1
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
100pF
MARGIN
CONTROL
VOUT
1.5V
6A
COUT
EFFICIENCY (%)
■
0.80
0.75
0.70
0.65
12VIN, 1.2VOUT
12VIN, 1.5VOUT
12VIN, 1.8VOUT
12VIN, 2.5VOUT
12VIN, 3.3VOUT
12VIN, 5VOUT
0.60
0.55
13.3k
0.50
0.45
0.40
fSET
0
5% MARGIN
1
4
3
2
5
OUTPUT CURRENT (A)
6
7
4603 TA01a
4603 TA01b
4603f
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LTM4603/LTM4603-1
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ABSOLUTE
AXI U RATI GS
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PACKAGE/ORDER I FOR ATIO
(Note 1)
INTVCC, DRVCC, VOUT_LCL, VOUT (VOUT ≤ 3.3V
with Remote Sense Amp) ............................ –0.3V to 6V
PLLIN, TRACK/SS, MPGM, MARG0, MARG1,
PGOOD, fSET .............................. –0.3V to INTVCC + 0.3V
RUN ............................................................. –0.3V to 5V
VFB, COMP ................................................ –0.3V to 2.7V
VIN ............................................................. –0.3V to 20V
VOSNS+, VOSNS– .................................. 0V to INTVCC – 1V
Operating Temperature Range (Note 2) ... –40°C to 85°C
Junction Temperature ........................................... 125°C
Storage Temperature Range................... –55°C to 125°C
INTVCC
PLLIN
TRACK/SS
RUN
COMP
MPGM
TOP VIEW
VIN
fSET
MARG0
MARG1
DRVCC
VFB
PGOOD
SGND
VOSNS+/NC2*
DIFFVOUT/NC3*
VOUT_LCL
VOSNS–/NC1*
PGND
VOUT
LGA PACKAGE
118-LEAD (15mm ´ 15mm ´ 2.8mm)
TJMAX = 125°C, θJA = 15°C/W, θJC = 6°C/W,
θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS, WEIGHT = 1.7g
*LTM4603-1 Only
ORDER PART NUMBER
LGA PART MARKING*
LTM4603EV#PBF
LTM4603IV#PBF
LTM4603EV-1#PBF
LTM4603IV-1#PBF
LTM4603V
LTM4603V
LTM4603V-1
LTM4603V-1
Consult LTC Marketing for parts specified with wider operating temperature ranges.
*The temperature grade is identified by a label on the shipping container.
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
VIN(DC)
Input DC Voltage
VOUT(DC)
Output Voltage
CONDITIONS
CIN = 10µF ×2, COUT = 2×, 100µF/X5R/
Ceramic
VIN = 5V, VOUT = 1.5V, IOUT = 0A
VIN = 12V, VOUT = 1.5V, IOUT = 0A
MIN
●
4.5
●
●
1.478
1.478
TYP
MAX
UNITS
20
V
1.5
1.5
1.522
1.522
V
V
4
V
Input Specifications
VIN(UVLO)
Undervoltage Lockout Threshold
IOUT = 0A
3.2
IINRUSH(VIN)
Input Inrush Current at Startup
IOUT = 0A. VOUT = 1.5V
VIN = 5V
VIN = 12V
0.6
0.7
A
A
3.8
25
mA
mA
2.5
43
mA
mA
22
µA
IQ(VIN,NOLOAD)
Input Supply Bias Current
VIN = 12V, VOUT = 1.5V, No Switching
VIN = 12V, VOUT = 1.5V, Switching
Continuous
VIN = 5V, VOUT = 1.5V, No Switching
VIN = 5V, VOUT = 1.5V, Switching
Continuous
Shutdown, RUN = 0, VIN = 12V
4603f
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LTM4603/LTM4603-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
IS(VIN)
Input Supply Current
VIN = 12V, VOUT = 1.5V, IOUT = 6A
VIN = 12V, VOUT = 3.3V, IOUT = 6A
VIN = 5V, VOUT = 1.5V, IOUT = 6A
INTVCC
VIN = 12V, RUN > 2V
No Load
MIN
TYP
MAX
0.85
1.78
2.034
4.7
5
UNITS
A
A
A
5.3
V
6
A
Output Specifications
Output Continuous Current Range
VIN = 12V, VOUT = 1.5V
(See Output Current Derating Curves
for Different VIN, VOUT and TA)
IOUTDC
VOUT(NOM) – VOUT(ΔLINE) Line Regulation Accuracy
0
VOUT = 1.5V, IOUT = 0A, VIN = 4.5V to 20V
●
0.3
%
VOUT = 1.5V, IOUT = 0A to 6A
VIN = 12V, with Remote Sense Amp
VIN = 12V, LTM4603-1
●
●
0.25
0.5
%
%
VOUT(NOM)
VOUT(NOM) – VOUT(ΔLOAD) Load Regulation Accuracy
VOUT(NOM)
VOUT(AC)
Output Ripple Voltage
IOUT = 0A, COUT = 2×, 100µF/X5R/Ceramic
VIN = 12V, VOUT = 1.5V
VIN = 5V, VOUT = 1.5V
10
10
mVP-P
mVP-P
fS
Output Ripple Voltage Frequency
IOUT = 3A, VIN = 12V, VOUT = 1.5V
1000
kHz
ΔVOUT(START)
Turn-On Overshoot,
TRACK/SS = 10nF
COUT = 2×, 100µF/X5R/Ceramic,
VOUT = 1.5V, IOUT = 0A
VIN = 12V
VIN = 5V
20
20
mV
mV
COUT = 2×, 100µF/X5R/Ceramic,
VOUT = 1.5V, IOUT = 1A Resisitive Load
VIN = 12V
VIN = 5V
0.5
0.7
ms
ms
Load: 0% to 50% to 0% of Full Load,
COUT = 2 × 22µF/Ceramic, 470µF, 4V
Sanyo POSCAP
VIN = 12V
VIN = 5V
35
35
mV
mV
Settling Time for Dynamic Load Step Load: 0% to 50% to 10% of Full Load
VIN = 12V
25
µs
8
8
A
A
tSTART
ΔVOUTLS
tSETTLE
IOUTPK
Turn-On Time, TRACK/SS = Open
Peak Deviation for Dynamic Load
Output Current Limit
COUT = 2×, 100µF/X5R/Ceramic
VIN = 12V, VOUT = 1.5V
VIN = 5V, VOUT = 1.5V
Remote Sense Amp (LTM4603 Only, Not Supported in the LTM4603-1) (Note 3)
VOSNS+, VOSNS–
CM Range
Common Mode Input Voltage Range VIN = 12V, RUN > 2V
0
INTVCC – 1
V
DIFFVOUT Range
Output Voltage Range
0
INTVCC
V
VOS
Input Offset Voltage Magnitude
AV
Differential Gain
GBP
Gain Bandwidth Product
3
MHz
SR
Slew Rate
2
V/µs
RIN
Input Resistance
20
kΩ
CMRR
Common Mode Rejection Ratio
100
dB
VIN = 12V, DIFF OUT Load = 100k
1.25
1
VOSNS+ to GND
mV
V/V
4603f
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LTM4603/LTM4603-1
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the –40°C to 85°C
temperature range, otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application (front page) configuration.
SYMBOL
PARAMETER
CONDITIONS
VFB
Error Amplifier Input Voltage
Accuracy
IOUT = 0A, VOUT = 1.5V
MIN
TYP
MAX
UNITS
0.594
0.6
0.606
V
1
1.5
1.9
V
–1
–1.5
–2
µA
Control Stage
●
VRUN
RUN Pin On/Off Threshold
ISS/TRACK
Soft-Start Charging Current
VSS/TRACK = 0V
tON(MIN)
Minimum On Time
(Note 4)
50
100
ns
tOFF(MIN)
Minimum Off Time
(Note 4)
250
400
ns
RPLLIN
PLLIN Input Resistance
IDRVCC
Current into DRVCC Pin
RFBHI
Resistor Between VOUT and VFB
VMPGM
Margin Reference Voltage
1.18
V
VMARG0, VMARG1
MARG0, MARG1 Voltage Thresholds
1.4
V
50
VOUT = 1.5V, IOUT = 1A,
Frequency = 1MHz, DRVCC = 5V
60.098
kΩ
18
25
mA
60.4
60.702
kΩ
PGOOD Output
ΔVFBH
PGOOD Upper Threshold
VFB Rising
7
10
13
%
ΔVFBL
PGOOD Lower Threshold
VFB Falling
–7
–10
–13
%
ΔVFB(HYS)
PGOOD Hysteresis
VFB Returning
1.5
3
%
VPGL
PGOOD Low Voltage
IPGOOD = 5mA
0.15
0.4
V
Note 1: Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliability and lifetime.
Note 2: The LTM4603E/LTM4603-1 are guaranteed to meet performance
specifications from 0°C to 85°C. Specifications over the –40°C to 85°C
operating temperature range are assured by design, characterization and
correlation with statistical process controls. The LTM4603E/LTM4603-1
are guaranteed and tested over the –40°C to 85°C temperature range.
Note 3: Remote sense amplifier recommended for ≤3.3V output.
Note 4: 100% tested at wafer level only.
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LTM4603/LTM4603-1
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TYPICAL PERFOR A CE CHARACTERISTICS (See Figure 18 for all curves)
Efficiency vs Load Current
with 5VIN
1.00
1.00
0.95
0.95
0.95
0.90
0.90
0.85
0.85
0.80
EFFICIENCY (%)
0.85
0.80
0.75
0.70
5VIN, 0.6VOUT
5VIN, 1.2VOUT
5VIN, 1.5VOUT
5VIN, 1.8VOUT
5VIN, 2.5VOUT
5VIN, 3.3VOUT
0.65
0.60
0.55
0.50
0
1
4
3
2
5
OUTPUT CURRENT (A)
0.80
0.75
0.70
0.65
12VIN, 1.2VOUT
12VIN, 1.5VOUT
12VIN, 1.8VOUT
12VIN, 2.5VOUT
12VIN, 3.3VOUT
12VIN, 5VOUT
0.60
0.55
0.50
0.45
6
0.40
7
EFFICIENCY (%)
0.90
EFFICIENCY (%)
Efficiency vs Load Current
with 20VIN
Efficiency vs Load Current
with 12VIN
0
1
4
3
2
5
OUTPUT CURRENT (A)
4603 G01
6
0.75
0.70
0.65
0.60
20VIN, 1.5VOUT
20VIN, 1.8VOUT
20VIN, 2.5VOUT
20VIN, 3.3VOUT
20VIN, 5VOUT
0.55
0.50
0.45
0.40
7
0
4
3
2
5
OUTPUT CURRENT (A)
1.5V Transient Response
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
25µs/DIV
1.5V AT 3A/µs LOAD STEP
COUT: 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
2.5V Transient Response
4603 G05
25µs/DIV
1.8V AT 3A/µs LOAD STEP
COUT: 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
4603 G06
3.3V Transient Response
LOAD STEP
1A/DIV
LOAD STEP
1A/DIV
VOUT
50mV/DIV
VOUT
50mV/DIV
25µs/DIV
2.5V AT 3A/µs LOAD STEP
COUT: 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
7
1.8V Transient Response
LOAD STEP
1A/DIV
4603 G04
6
4603 G03
4603 G02
1.2V Transient Response
25µs/DIV
1.2V AT 3A/µs LOAD STEP
COUT: 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
1
4603 G07
25µs/DIV
3.3V AT 3A/µs LOAD STEP
COUT: 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
4603 G08
4603f
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LTM4603/LTM4603-1
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TYPICAL PERFOR A CE CHARACTERISTICS (See Figure 18 for all curves)
Start-Up, IOUT = 6A
(Resistive Load)
Start-Up, IOUT = 0A
Short-Circuit Protection,
IOUT = 0A
VOUT
0.5V/DIV
VOUT
0.5V/DIV
VOUT
0.5V/DIV
IIN
0.5A/DIV
IIN
0.5A/DIV
1ms/DIV
VIN = 12V
VOUT = 1.5V
COUT = 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
4603 G09
IIN
2A/DIV
1ms/DIV
VIN = 12V
VOUT = 1.5V
COUT = 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
Short-Circuit Protection,
IOUT = 6A
4603 G10
100µs/DIV
VIN = 12V
VOUT = 1.5V
COUT = 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
VIN to VOUT Step-Down Ratio
5.5
3.3V OUTPUT WITH
82.5k FROM VOUT
TO fSET
5.0
4.5
OUTPUT VOLTAGE (V)
VOUT
0.5V/DIV
IIN
2A/DIV
100µs/DIV
VIN = 12V
VOUT = 1.5V
COUT = 1x 22µF, 6.3V CERAMIC
1x 330µF, 4V SANYO POSCAP
SOFT-START = 3.9nF
4603 G11
4603 G12
5V OUTPUT WITH
150k RESISTOR
ADDED FROM fSET
TO GND
4.0
3.5
3.0
2.0
5V OUTPUT WITH
NO RESISTOR ADDED
FROM fSET TO GND
1.5
2.5V OUTPUT
1.0
1.8V OUTPUT
2.5
1.5V OUTPUT
0.5
0
1.2V OUTPUT
0
2
4
6 8 10 12 14 16 18 20
INPUT VOLTAGE (V)
4603 G13
4603f
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LTM4603/LTM4603-1
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PI FU CTIO S
(See Package Description for Pin Assignment)
VIN (Bank 1): Power Input Pins. Apply input voltage between these pins and PGND pins. Recommend placing
input decoupling capacitance directly between VIN pins
and PGND pins.
VOUT (Bank 3): Power Output Pins. Apply output load
between these pins and PGND pins. Recommend placing
output decoupling capacitance directly between these pins
and PGND pins. Review the figure below.
PGND (Bank 2): Power ground pins for both input and
output returns.
VOSNS– (Pin M12): (–) Input to the Remote Sense Amplifier.
This pin connects to the ground remote sense point. The
remote sense amplifier is used for VOUT ≤3.3V.
NC1 (Pin M12): No Connect on the LTM4603-1.
VOSNS+ (Pin J12): (+) Input to the Remote Sense Amplifier.
This pin connects to the output remote sense point. The
remote sense amplifier is used for VOUT ≤3.3V.
NC2 (Pin J12): No Connect on the LTM4603-1.
DIFFVOUT (Pin K12): Output of the Remote Sense Amplifier. This pin connects to the VOUT_LCL pin.
NC3 (Pin K12): No Connect on the LTM4603-1.
DRVCC (Pin E12): This pin normally connects to INTVCC
for powering the internal MOSFET drivers. This pin can
be biased up to 6V from an external supply with about
50mA capability, or an external circuit shown in Figure
16. This improves efficiency at the higher input voltages
by reducing power dissipation in the modules.
INTVCC (Pin A7): This pin is for additional decoupling of
the 5V internal regulator.
PLLIN (Pin A8): External Clock Synchronization Input to
the Phase Detector. This pin is internally terminated to
SGND with a 50k resistor. Apply a clock above 2V and
below INTVCC. See Applications Information.
TRACK/SS (Pin A9): Output Voltage Tracking and SoftStart Pin. When the module is configured as a master
output, then a soft-start capacitor is placed on this pin
to ground to control the master ramp rate. A soft-start
capacitor can be used for soft-start turn on as a stand
alone regulator. Slave operation is performed by putting
a resistor divider from the master output to the ground,
and connecting the center point of the divider to this pin.
See Applications Information.
MPGM (Pin A12): Programmable Margining Input. A resistor from this pin to ground sets a current that is equal
to 1.18V/R. This current multiplied by 10kΩ will equal a
value in millivolts that is a percentage of the 0.6V reference voltage. See Applications Information. To parallel
LTM4603s, each requires an individual MPGM resistor.
Do not tie MPGM pins together.
fSET (Pin B12): Frequency Set Internally to 1MHz. An
external resistor can be placed from this pin to ground
to increase frequency. This pin can be decoupled with a
1000pF capacitor. See Applications Information for frequency adjustment.
VFB (Pin F12): The Negative Input of the Error Amplifier. Internally, this pin is connected to VOUT_LCL with a
60.4k precision resistor. Different output voltages can be
INTVCC
PLLIN
TRACK/SS
RUN
COMP
MPGM
TOP VIEW
A
VIN
B
BANK 1
C
D
E
PGND
F
BANK 2
G
H
J
VOUT K
BANK 3 L
M
fSET
MARG0
MARG1
DRVCC
VFB
PGOOD
SGND
VOSNS+ (NC2, LTM4603-1)
DIFFVOUT (NC3, LTM4603-1)
VOUT_LCL
VOSNS– (NC1, LTM4603-1)
1 2 3 4 5 6 7 8 9 10 11 12
4603f
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LTM4603/LTM4603-1
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PI FU CTIO S
(See Package Description for Pin Assignment)
programmed with an additional resistor between VFB and
SGND pins. See Applications Information.
ranges from 0V to 2.4V with 0.7V corresponding to zero
sense voltage (zero current).
MARG0 (Pin C12): This pin is the LSB logic input for the
margining function. Together with the MARG1 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
PGOOD (Pin G12): Output Voltage Power Good Indicator.
Open-drain logic output that is pulled to ground when the
output voltage is not within ±10% of the regulation point,
after a 25µs power bad mask timer expires.
RUN (Pin A10): Run Control Pin. A voltage above 1.9V
will turn on the module, and when below 1.9V, will turn
off the module. A programmable UVLO function can be
accomplished with a resistor from VIN to this pin that has
a 5.1V zener to ground. Maximum pin voltage is 5V.
MARG1 (Pin D12): This pin is the MSB logic input for the
margining function. Together with the MARG0 pin will
determine if margin high, margin low or no margin state
is applied. The pin has an internal pull-down resistor of
50k. See Applications Information.
VOUT_LCL (Pin L12): VOUT connects directly to this pin
to bypass the remote sense amplifier, or DIFFVOUT connects to this pin when remote sense amplifier is used.
VOUT_LCL can be connected to VOUT on the LTM4603-1.
VOUT is internally connected to VOUT_LCL through 50Ω in
the LTM4603-1.
SGND (Pin H12): Signal Ground. This pin connects to
PGND at output capacitor point.
COMP (Pin A11): Current Control Threshold and Error
Amplifier Compensation Point. The current comparator
threshold increases with this control voltage. The voltage
W
W
SI PLIFIED BLOCK DIAGRA
1M
VOUT_LCL
>2V = ON
<0.9V = OFF
MAX = 5V
VOUT
RUN
PGOOD
5.1V
ZENER
COMP
1.5µF
VIN
4.5V TO 28V
+
CIN
60.4k
INTERNAL
COMP
POWER CONTROL
SGND
Q1
VOUT
2.5V
6A
MARG1
MARG0
22µF
VFB
RFB
40.2k
50k
50k
+
fSET
COUT
Q2
33.2k
PGND
MPGM
10k
INTVCC
TRACK/SS
PLLIN
50k
VOSNS–
10k
10k
VOSNS+
10k
INTVCC
DRVCC
+
–
CSS
4.7µF
DIFFVOUT
4603 F01
Figure 1. Simplified LTM4603/LTM4603-1 Block Diagram
4603f
8
LTM4603/LTM4603-1
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DECOUPLI G REQUIRE E TS
TA = 25°C, VIN = 12V. Use Figure 1 configuration.
SYMBOL
PARAMETER
CONDITIONS
MIN
CIN
External Input Capacitor Requirement
(VIN = 4.5V to 20V, VOUT = 1.5V)
IOUT = 6A
20
COUT
External Output Capacitor Requirement
(VIN = 4.5V to 20V, VOUT = 1.5V)
IOUT = 6A
100
TYP
MAX
UNITS
µF
200
µF
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OPERATIO
Power Module Description
The LTM4603 is a standalone nonisolated switching mode
DC/DC power supply. It can deliver up to 6A of DC output
current with few external input and output capacitors.
This module provides precisely regulated output voltage
programmable via one external resistor from 0.6VDC to
5.0VDC over a 4.5V to 20V wide input voltage. The typical
application schematic is shown in Figure 18.
The LTM4603 has an integrated constant on-time current
mode regulator, ultralow RDS(ON) FETs with fast switching
speed and integrated Schottky diodes. The typical switching
frequency is 1MHz at full load. With current mode control
and internal feedback loop compensation, the LTM4603
module has sufficient stability margins and good transient
performance under a wide range of operating conditions
and with a wide range of output capacitors, even all ceramic
output capacitors.
Current mode control provides cycle-by-cycle fast current
limit. Besides, foldback current limiting is provided in an
overcurrent condition while VFB drops. Internal overvoltage
and undervoltage comparators pull the open-drain PGOOD
output low if the output feedback voltage exits a ±10%
window around the regulation point. Furthermore, in an
overvoltage condition, internal top FET Q1 is turned off
and bottom FET Q2 is turned on and held on until the
overvoltage condition clears.
Pulling the RUN pin below 1V forces the controller into its
shutdown state, turning off both Q1 and Q2. At low load
current, the module works in continuous current mode by
default to achieve minimum output voltage ripple.
When DRVCC pin is connected to INTVCC an integrated
5V linear regulator powers the internal gate drivers. If a
5V external bias supply is applied on the DRVCC pin, then
an efficiency improvement will occur due to the reduced
power loss in the internal linear regulator. This is especially
true at the higher input voltage range.
The LTM4603 has a very accurate differential remote
sense amplifier with very low offset. This provides for
very accurate remote sense voltage measurement. The
MPGM pin, MARG0 pin and MARG1 pin are used to support voltage margining, where the percentage of margin
is programmed by the MPGM pin, and the MARG0 and
MARG1 select margining.
The PLLIN pin provides frequency synchronization of the
device to an external clock. The TRACK/SS pin is used for
power supply tracking and soft-start programming.
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The typical LTM4603 application circuit is shown in
Figure 18. External component selection is primarily
determined by the maximum load current and output
voltage. Refer to Table 2 for specific external capacitor
requirements for a particular application.
where %VOUT is the percentage of VOUT you want to margin,
and VOUT(MARGIN) is the margin quantity in volts:
VIN to VOUT Step-Down Ratios
where RPGM is the resistor value to place on the MPGM
pin to ground.
There are restrictions in the maximum VIN and VOUT step
down ratio that can be achieved for a given input voltage.
These constraints are shown in the Typical Performance
Characteristics curves labeled VIN to VOUT Step-Down
Ratio. Note that additional thermal derating may apply. See
the Thermal Considerations and Output Current Derating
section of this data sheet.
RPGM =
The output margining will be ± margining of the value.
This is controlled by the MARG0 and MARG1 pins. See
the truth table below:
Output Voltage Programming and Margining
The PWM controller has an internal 0.6V reference voltage. As shown in the Block Diagram, a 1M and a 60.4k
0.5% internal feedback resistor connects VOUT and FB pins
together. The VOUT_LCL pin is connected between the 1M
and the 60.4k resistor. The 1M resistor is used to protect
against an output overvoltage condition if the VOUT_LCL
pin is not connected to the output, or if the remote sense
amplifier output is not connected to VOUT_LCL. The output
voltage will default to 0.6V. Adding a resistor RSET from
the FB pin to SGND pin programs the output voltage:
VOUT = 0.6 V
60.4k + RSET
RSET
MARG1
MODE
LOW
LOW
NO MARGIN
LOW
HIGH
MARGIN UP
HIGH
LOW
MARGIN DOWN
HIGH
HIGH
NO MARGIN
Input Capacitors
LTM4603 module should be connected to a low AC impedance DC source. Input capacitors are required to be placed
adjacent to the module. In Figure 18, the 10µF ceramic
input capacitors are selected for their ability to handle
the large RMS current into the converter. An input bulk
capacitor of 100µF is optional. This 100µF capacitor is only
needed if the input source impedance is compromised by
long inductive leads or traces.
D=
RSET
(kΩ)
Open
60.4
40.2
30.1
25.5
19.1
13.3
8.25
VOUT
(V)
0.6
1.2
1.5
1.8
2
2.5
3.3
5
The MPGM pin programs a current that when multiplied
by an internal 10k resistor sets up the 0.6V reference ±
offset for margining. A 1.18V reference divided by the
RPGM resistor on the MPGM pin programs the current.
Calculate VOUT(MARGIN):
%VOUT
• VOUT
100
MARG0
For a buck converter, the switching duty-cycle can be
estimated as:
Table 1. Standard 1% Resistor Values
VOUT(MARGIN) =
VOUT
1.18 V
•
• 10k
0.6 V VOUT(MARGIN)
VOUT
VIN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
IOUT(MAX )
η%
• D • ( 1– D )
In the above equation, η% is the estimated efficiency of
the power module. CIN can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitor. Note the capacitor ripple current ratings are often based on temperature and hours of life. This
makes it advisable to properly derate the input capacitor,
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or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 18, the 10µF ceramic capacitors are together
used as a high frequency input decoupling capacitor. In a
typical 6A output application, two very low ESR, X5R or
X7R, 10µF ceramic capacitors are recommended. These
decoupling capacitors should be placed directly adjacent
to the module input pins in the PCB layout to minimize
the trace inductance and high frequency AC noise. Each
10µF ceramic is typically good for 2A to 3A of RMS ripple
current. Refer to your ceramics capacitor catalog for the
RMS current ratings.
Multiphase operation with multiple LTM4603 devices in
parallel will lower the effective input RMS ripple current due
to the interleaving operation of the regulators. Application
Note 77 provides a detailed explanation. Refer to Figure 2
for the input capacitor ripple current requirement as a function of the number of phases. The figure provides a ratio
of RMS ripple current to DC load current as a function of
duty cycle and the number of paralleled phases. Pick the
corresponding duty cycle and the number of phases to
arrive at the correct ripple current value. For example, the
2-phase parallel LTM4603 design provides 10A at 2.5V
output from a 12V input. The duty cycle is DC = 2.5V/12V
= 0.21. The 2-phase curve has a ratio of ~0.25 for a duty
cycle of 0.21. This 0.25 ratio of RMS ripple current to a
DC load current of 10A equals ~2.5A of input RMS ripple
current for the external input capacitors.
Output Capacitors
The LTM4603 is designed for low output voltage ripple.
The bulk output capacitors defined as COUT are chosen
with low enough effective series resistance (ESR) to meet
the output voltage ripple and transient requirements. COUT
can be a low ESR tantalum capacitor, a low ESR polymer
capacitor or a ceramic capacitor. The typical capacitance is
200µF if all ceramic output capacitors are used. Additional
output filtering may be required by the system designer,
if further reduction of output ripple or dynamic transient
spike is required. Table 2 shows a matrix of different output
voltages and output capacitors to minimize the voltage
droop and overshoot during a 2.5A/µs transient. The table
optimizes total equivalent ESR and total bulk capacitance
to maximize transient performance.
Multiphase operation with multiple LTM4603 devices in
parallel will lower the effective output ripple current due
to the interleaving operation of the regulators. For example, each LTM4603’s inductor current of a 12V to 2.5V
multiphase design can be read from the “Inductor Ripple
versus Duty Cycle” (Figure 3). The large ripple current at
low duty cycle and high output voltage can be reduced
by adding an external resistor from fSET to ground which
increases the frequency. If we choose the duty cycle of
DC = 2.5V/12V = 0.21, the inductor ripple current for 2.5V
output at 21% duty cycle is ~2.5A in Figure 3.
5
0.6
5V OUTPUT
4
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.4
0.3
1.8V OUTPUT
1.5V OUTPUT
3
1.2V OUTPUT
IL (A)
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT
2.5V OUTPUT
0.5
3.3V OUTPUT WITH
82.5k ADDED FROM
VOUT TO fSET
2
0.2
0.1
0
5V OUTPUT WITH
150k ADDED FROM
fSET TO GND
1
0
0.1
0.2
0.3 0.4 0.5 0.6 0.7
DUTY FACTOR (VOUT/VIN)
0.8
0.9
4603 F02
Figure 2. Normalized Input RMS Ripple Current
vs Duty Factor for One to Six Modules (Phases)
0
20
40
60
DUTY CYCLE (VOUT/VIN)
80
4603 F03
Figure 3. Inductor Ripple Current vs Duty Cycle
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1.00
0.95
1-PHASE
2-PHASE
3-PHASE
4-PHASE
6-PHASE
0.90
0.85
RATIO =
PEAK-TO-PEAK OUTPUT RIPPLE CURRENT
DIr
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VO/VIN)
4603 F04
Figure 4. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOT/LI
Figure 4 provides a ratio of peak-to-peak output ripple current to the inductor current as a function of duty cycle and
the number of paralleled phases. Pick the corresponding
duty cycle and the number of phases to arrive at the correct
output ripple current ratio value. If a 2-phase operation is
chosen at a duty cycle of 21%, then 0.6 is the ratio. This
0.6 ratio of output ripple current to inductor ripple of 2.5A
equals 1.5A of effective output ripple current. Refer to Application Note 77 for a detailed explanation of output ripple
current reduction as a function of paralleled phases.
The output voltage ripple has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output voltage ripple can be calulated with
the known effective output ripple current. The equation:
ΔVOUT(P-P) ≈ (ΔIL/(8 • f • m • COUT) + ESR • ΔIL), where f
is frequency and m is the number of parallel phases. This
calclation process can be easily fulfilled using our Excel
tool (refer to??).
Fault Conditions: Current Limit and Overcurrent
Foldback
The LTM4603 has a current mode controller, which inherently limits the cycle-by-cycle inductor current not only in
steady-state operation, but also in transient.
To further limit current in the event of an overload condition, the LTM4603 provides foldback current limiting. If the
output voltage falls by more than 50%, then the maximum
output current is progressively lowered to about one sixth
of its full current limit value.
Soft-Start and Tracking
The TRACK/SS pin provides a means to either soft-start
the regulator or track it to a different power supply. A
capacitor on this pin will program the ramp rate of the
output voltage. A 1.4µA current source will charge up the
external soft-start capacitor to 80% of the 0.6V internal
voltage reference minus any margin delta. This will control
4603f
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the ramp of the internal reference and the output voltage.
The total soft-start time can be calculated as:
(
)
t SOFTSTART = 0.8 V • 0.6 V – VOUT(MARGIN) •
CSS
1.5µA
When the RUN pin falls below 1.5V, then the SS pin is reset
to allow for proper soft-start control when the regulator
is enabled again. Current foldback and force continuous
mode are disabled during the soft-start process. The
soft-start function can also be used to control the output
ramp up time, so that another regulator can be easily
tracked to it.
Output Voltage Tracking
Output voltage tracking can be programmed externally
using the TRACK/SS pin. The output can be tracked up and
down with another regulator. The master regulator’s output
is divided down with an external resistor divider that is the
same as the slave regulator’s feedback divider. Figure 5
shows an example of coincident tracking. Ratiometric
modes of tracking can be achieved by selecting different
resistor values to change the output tracking ratio. The
master output must be greater than the slave output for
the tracking to work. Figure 6 shows the coincident output
tracking characteristics.
MASTER
OUTPUT
TRACK CONTROL
VIN
100k
CIN
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
SGND
PLLIN TRACK/SS
VOUT
LTM4603
PGND
60.4k FROM
VOUT TO VFB
The RUN pin is used to enable the power module. The
pin has an internal 5.1V zener to ground. The pin can be
driven with a logic input not to exceed 5V.
The RUN pin can also be used as an undervoltage lock out
(UVLO) function by connecting a resistor divider from the
input supply to the RUN pin:
VUVLO =
R1+ R2
• 1.5V
R2
Power Good
The PGOOD pin is an open-drain pin that can be used to
monitor valid output voltage regulation. This pin monitors
a ±10% window around the regulation point and tracks
with margining.
COMP Pin
This pin is the external compensation pin. The module
has already been internally compensated for most output
voltages. Table 2 is provided for most application requirements. A spice model will be provided for other control
loop optimization.
PLLIN
The power module has a phase-locked loop comprised of an
internal voltage controlled oscillator and a phase detector.
This allows the internal top MOSFET turn-on to be locked
R1
40.2k
MASTER OUTPUT
SLAVE OUTPUT
VFB
MARG0
MARG1
COUT
SLAVE OUTPUT
OUTPUT
VOLTAGE
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
R2
60.4k
Run Enable
RSET
40.2k
4603 F05
TIME
Figure 5
4603 F06
Figure 6
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to the rising edge of the external clock. The frequency
range is ±30% around the operating frequency of 1MHz.
A pulse detection circuit is used to detect a clock on the
PLLIN pin to turn on the phase lock loop. The pulse width
of the clock has to be at least 400ns and 2V in amplitude.
During the start-up of the regulator, the phase-lock loop
function is disabled.
60.4k
+ RFB
η
VOUT = 0.6 V
RFB
η is the number of paralleled modules.
INTVCC and DRVCC Connection
An internal low dropout regulator produces an internal
5V supply that powers the control circuitry and DRVCC
for driving the internal power MOSFETs. Therefore, if
the system does not have a 5V power rail, the LTM4603
can be directly powered by Vin. The gate driver current
through the LDO is about 20mA. The internal LDO power
dissipation can be calculated as:
PLDO_LOSS = 20mA • (VIN – 5V)
The LTM4603 also provides the external gate driver voltage pin DRVCC. If there is a 5V rail in the system, it is
recommended to connect DRVCC pin to the external 5V
rail. This is especially true for higher input voltages. Do
not apply more than 6V to the DRVCC pin. A 5V output can
be used to power the DRVCC pin with an external circuit
as shown in Figure 16.
Parallel Operation of the Module
The LTM4603 device is an inherently current mode controlled device. Parallel modules will have very good current
3.5
Thermal Considerations and Output Current Derating
The power loss curves in Figures 7 and 8 can be used
in coordination with the load current derating curves in
Figures 9 to 12, and Figures 13 to 14 for calculating an
approximate θJA for the module with various heat sinking
methods. Thermal models are derived from several temperature measurements at the bench and thermal modeling
analysis. Thermal Application Note 103 provides a detailed
explanation of the analysis for the thermal models and the
derating curves. Tables 3 and 4 provide a summary of the
equivalent θJA for the noted conditions. These equivalent
θJA parameters are correlated to the measured values,
and are improved with air flow. The case temperature is
maintained at 100°C or below for the derating curves.
This allows for 4W maximum power dissipation in the
total module with top and bottom heatsinking, and 2W
power dissipation through the top of the module with an
approximate θJC between 6°C/W to 9°C/W. This equates
to a total of 124°C at the junction of the device.
6
3.5
3.0
20V LOSS
POWER LOSS (W)
2.5
MAXIMUM LOAD CURRENT (A)
3.0
20V LOSS
POWER LOSS (W)
sharing. This will balance the thermals on the design. The
voltage feedback equation changes with the variable η as
modules are paralleled:
12V LOSS
2.0
1.5
5V LOSS
1.0
0.5
2.5
2.0
12V LOSS
1.5
1.0
0.5
0
0
1
4
3
5
2
OUTPUT CURRENT (A)
6
7
4603 F07
Figure 7. 1.5V Power Loss
5
4
3
2
5VIN, 1.5VOUT, 0LFM
5VIN, 1.5VOUT, 200LFM
5VIN, 1.5VOUT, 400LFM
1
0
0
0
1
4
3
5
2
OUTPUT CURRENT (A)
6
7
75
80
85
90
AMBIENT TEMPERATURE (°C)
4603 F09
4603 F08
Figure 8. 3.3V Power Loss
95
Figure 9. No Heat Sink
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5
5
5
4
3
2
5VIN, 1.5VOUT, 0LFM
5VIN, 1.5VOUT, 200LFM
5VIN, 1.5VOUT, 400LFM
0
75
80
85
90
AMBIENT TEMPERATURE (°C)
4
3
2
1
0
95
4
3
2
12VIN, 1.5VOUT, 0LFM
12VIN, 1.5VOUT, 200LFM
12VIN, 1.5VOUT, 400LFM
1
0
70
75
80
85
90
AMBIENT TEMPERATURE (°C)
12VIN, 1.5VOUT, 0LFM
12VIN, 1.5VOUT, 200LFM
12VIN, 1.5VOUT, 400LFM
4603 F10
Figure 10. BGA Heat Sink
95
70
75
80
85
90
AMBIENT TEMPERATURE (°C)
4603 F11
95
4603 F12
Figure 12. BGA Heat Sink
Figure 11. No Heat Sink
6
6
5
5
MAXIMUM LOAD CURRENT (A)
1
MAXIMUM LOAD CURRENT (A)
6
MAXIMUM LOAD CURRENT (A)
6
MAXIMUM LOAD CURRENT (A)
MAXIMUM LOAD CURRENT (A)
APPLICATIO S I FOR ATIO
4
3
2
12VIN, 3.3VOUT, 0LFM
12VIN, 3.3VOUT, 200LFM
12VIN, 3.3VOUT, 400LFM
1
0
70
75
80
85
90
AMBIENT TEMPERATURE (°C)
95
4
3
2
12VIN, 3.3VOUT, 0LFM
12VIN, 3.3VOUT, 200LFM
12VIN, 3.3VOUT, 400LFM
1
0
70
75
80
85
90
AMBIENT TEMPERATURE (°C)
4603 F13
Figure 13. No Heat Sink
95
4603 F14
Figure 14. BGA Heat Sink
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LTM4603/LTM4603-1
Table 2. Output Voltage Response Versus Component Matrix (Refer to Figure 18)
TYPICAL MEASURED VALUES
COUT1 VENDORS
TAIYO YUDEN
TAIYO YUDEN
TDK
VOUT
(V)
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
1.8
1.8
2.5
2.5
2.5
2.5
2.5
2.5
2.5
2.5
3.3
3.3
3.3
3.3
3.3
3.3
3.3
3.3
5
5
CIN
(CERAMIC)
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
2 × 10µF 25V
PART NUMBER
JMK316BJ226ML-T501 (22µF, 6.3V)
JMK325BJ476MM-T (47µF, 6.3V)
C3225X5R0J476M (47µF, 6.3V)
CIN
(BULK)
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
150µF 35V
COUT1
(CERAMIC)
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
1 × 22µF 6.3V
1 × 47µF 6.3V
2 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
4 × 47µF 6.3V
COUT2
(BULK)
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 2.5V
220µF 6.3V
NONE
330µF 4V
330µF 4V
220µF 6.3V
NONE
330µF 4V
330µF 4V
220µF 6.3V
NONE
330µF 4V
330µF 4V
220µF 6.3V
NONE
330µF 4V
330µF 4V
220µF 6.3V
NONE
NONE
NONE
COUT2 VENDORS
SANYO POSCAP
SANYO POSCAP
SANYO POSCAP
VIN
(V)
5
5
5
5
12
12
12
12
5
5
5
5
12
12
12
12
5
5
5
5
12
12
12
12
5
5
5
5
12
12
12
12
7
7
7
7
12
12
12
12
15
20
DROOP
(mV)
34
22
20
32
34
22
20
29.5
35
25
24
36
35
25
24
32.6
38
29.5
28
43
38
28
27
36.4
38
37.6
39.5
66
38
34.5
35.8
50
42
47
50
75
42
47
50
69
110
110
PART NUMBER
6TPE220MIL (220µF, 6.3V)
2R5TPE330M9 (330µF, 2.5V)
4TPE330MCL (330µF, 4V)
PEAK TO
PEAK (mV)
68
40
40
60
68
40
39
55
70
48
47.5
68
70
48
45
61.9
76
57.5
55
80
76
55
52
70
78
74
78.1
119
78
66.3
68.8
98
86
89
94
141
86
88
94
131
215
217
RECOVERY
TIME (µs)
30
26
24
18
30
26
24
18
30
30
26
26
30
30
26
26
37
30
26
26
37
30
26
26
40
34
28
12
40
34
28
18
40
32
28
14
40
32
28
22
20
20
LOAD STEP
(A/µs)
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
3
RSET
(kΩ)
60.4
60.4
60.4
60.4
60.4
60.4
60.4
60.4
40.2
40.2
40.2
40.2
40.2
40.2
40.2
40.2
30.1
30.1
30.1
30.1
30.1
30.1
30.1
30.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
19.1
13.3
13.3
13.3
13.3
13.3
13.3
13.3
13.3
8.25
8.25
4603f
16
LTM4603/LTM4603-1
U
U
W
U
APPLICATIO S I FOR ATIO
Table 3. 1.5V Output
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA (°C/W)
Figures 9, 11
5, 12
Figure 7
0
None
15.2
Figures 9, 11
5, 12
Figure 7
200
None
14
Figures 9, 11
5, 12
Figure 7
400
None
12
Figures 10, 12
5, 12, 20
Figure 7
0
BGA Heat Sink
13.9
Figures 10, 12
5, 12, 20
Figure 7
200
BGA Heat Sink
11.3
Figures 10, 12
5, 12, 20
Figure 7
400
BGA Heat Sink
10.25
DERATING CURVE
VIN (V)
POWER LOSS CURVE
AIR FLOW (LFM)
HEAT SINK
θJA (°C/W)
Figure 13
12
Figure 8
0
None
15.2
Figure 13
12
Figure 8
200
None
14.6
Figure 13
12
Figure 8
400
None
13.4
Figure 14
12
Figure 8
0
BGA Heat Sink
13.9
Figure 14
12
Figure 8
200
BGA Heat Sink
11.1
Figure 14
12
Figure 8
400
BGA Heat Sink
10.5
Table 4. 3.3V Output
Heat Sink Manufacturer
Wakefield Engineering
Part No: 20069
Phone: 603-635-2800
4603f
17
LTM4603/LTM4603-1
U
W
U
U
APPLICATIO S I FOR ATIO
Safety Considerations
• Do not put vias directly on pads.
The LTM4603 modules do not provide isolation from VIN to
VOUT. There is no internal fuse. If required, a slow blow fuse
with a rating twice the maximum input current needs to be
provided to protect each unit from catastrophic failure.
• If vias are placed onto the pads, the the vias must be
capped.
Layout Checklist/Example
The high integration of LTM4603 makes the PCB board
layout very simple and easy. However, to optimize its electrical and thermal performance, some layout considerations
are still necessary.
• Use large PCB copper areas for high current path, including VIN, PGND and VOUT. It helps to minimize the
PCB conduction loss and thermal stress.
• Place high frequency ceramic input and output capacitors next to the VIN, PGND and VOUT pins to minimize
high frequency noise.
• Place a dedicated power ground layer underneath the
unit.
• To minimize the via conduction loss and reduce module
thermal stress, use multiple vias for interconnection
between top layer and other power layers.
• Interstitial via placement can also be used if necessary.
• Use a separated SGND ground copper area for components connected to signal pins. Connect the SGND
to PGND underneath the unit.
Figure 15 gives a good example of the recommended
layout.
Frequency Adjustment
The LTM4603 is designed to typically operate at 1MHz
across most input conditions. The fSET pin is typically left
open or decoupled with an optional 1000pF capacitor. The
switching frequency has been optimized for maintaining
constant output ripple noise over most operating ranges.
The 1MHz switching frequency and the 400ns minimum
off time can limit operation at higher duty cycles like 5V to
3.3V, and produce excessive inductor ripple currents for
lower duty cycle applications like 20V to 5V. The 5V and
3.3V drop out curves are modified by adding an external
resistor on the fSET pin to allow for lower input voltage
operation, or higher input voltage operation.
VIN
CIN
CIN
GND
SIGNAL
GND
COUT
COUT
VOUT
4603 F15
Figure 15. Recommended Layout
4603f
18
LTM4603/LTM4603-1
U
W
U
U
APPLICATIO S I FOR ATIO
Example for 5V Output
Example for 3.3V Output
LTM4603 minimum on-time = 100ns;
tON = ((4.8 • 10pf)/IfSET)
LTM4603 minimum on-time = 100ns;
tON = ((3.3 • 10pF)/IfSET)
LTM4603 minimum off-time = 400ns; tOFF = t – tON,
where t = 1/Frequency
LTM4603 minimum off-time = 400ns;
tOFF = t – tON, where t = 1/Frequency
Duty Cycle = tON/t or VOUT/VIN
Duty Cycle (DC) = tON/t or VOUT/VIN
Equations for setting frequency:
Equations for setting frequency:
IfSET = (VIN/(3 • RfSET)), for 20V operation, ISET = 201µA, tON
= ((4.8 • 10pF)/IfSET), tON = 239ns, where the internal RfSET
is 33.2k. Frequency = (VOUT/(VIN • tON)) = (5V/(20 • 239ns))
~ 1MHz. The inductor ripple current begins to get high at the
higher input voltages due to a larger voltage across the inductor. This is noted in the “Typical Inductor Ripple Current
verses Duty Cycle graph” at ~4.5A at 25% duty cycle. The
inductor ripple current can be lowered at the higher input
voltages by adding an external resistor from fSET to ground
to increase the switching frequency. A 3A ripple current is
chosen, and the total peak current is equal to 1/2 of the 3A
ripple current plus the output current. The 5V output current
is limited to 5A, so total peak current is less than 6.5A. This is
below the 7A peak specified value. A 150k resistor is placed
from fSET to ground, and the parallel combination of 150k
and 33.2k equates to 27.2k. The IfSET calculation with 27.2k
and 20V input voltage equals 245µA. This equates to a tON
of 196ns. This will increase the switching frequency from
1MHz to ~1.28MHz for the 20V to 5V conversion. The
minimum on time is above 100ns at 20V input. Since
the switching frequency is approximately constant over
input and output conditions, then the lower input voltage
range is limited to 10V for the 1.28MHz operation due to
the 400ns minimum off time. Equation: tON = (VOUT/VIN)
• (1/Frequency) equates to a 382ns on time, and a 400ns
off time. The “VIN to VOUT Step Ratio Curve” reflects an
operating range of 10V to 20V for 1.28MHz operation with
a 150k resistor to ground, and an 8V to 16V operation for
fSET floating. These modifications are made to provide
wider input voltage ranges for the 5V output designs while
limiting the inductor ripple current, and maintaining the
400ns minimum off time.
IfSET = (VIN/(3 • RfSET)), for 20V operation, IfSET = 201µA,
tON = ((3.3 • 10pf)/IfSET), tON = 164ns, where the internal
RfSET is 33.2k. Frequency = (VOUT/(VIN • tON)) = (3.3V/(20
• 164ns)) ~ 1MHz. The minimum on-time and minimumoff time are within specification at 164ns and 836ns. The
4.5V minimum input for converting 3.3V output will not
meet the minimum off-time specification of 400ns. tON =
733ns, Frequency = 1MHz, tOFF = 267ns.
Solution
Lower the switching frequency at lower input voltages to
allow for higher duty cycles, and meet the 400ns minimum off-time at 4.5V input voltage. The off-time should
be about 500ns with 100ns guard band. The duty cycle
for (3.3V/4.5) = ~73%. Frequency = (1 – DC)/tOFF, or
(1 – 0.73)/500ns = 540kHz. The switching frequency needs
to be lowered to 540kHz at 4.5V input. tON = DC/frequency,
or 1.35µs. The fSET pin voltage compliance is 1/3 of VIN,
and the IfSET current equates to 45µA with the internal
33.2k. The IfSET current needs to be 24µA for 540kHz
operation. A resistor can be placed from VOUT to fSET to
lower the effective IfSET current out of the fSET pin to 24µA.
The fSET pin is 4.5V/3 =1.5V and VOUT = 3.3V, therefore
82.5k will source 21µA into the fSET node and lower the
IfSET current to 24µA. This enables the 540kHz operation
and the 4.5V to 20V input operation for down converting
to 3.3V output. The frequency will scale from 540kHz to
1.2MHz over this input range. This provides for an effective
output current of 5A over the input range.
4603f
19
LTM4603/LTM4603-1
U
U
W
U
APPLICATIO S I FOR ATIO
VOUT
TRACK/SS CONTROL
VIN
10V TO 20V
C2
10µF
25V
R2
100k
R4
100k
VIN
PGOOD
PLLIN TRACK/SS
VOUT
MPGM
RUN
COMP
INTVCC
DRVCC
5% MARGIN
R1
392k
1%
C1
10µF
25V
LTM4603-1
SGND
PGND
REVIEW TEMPERATURE
DERATING CURVE
+
C6 100pF
VFB
MARG0
MARG1
VOUT_LCL
NC3
NC1
NC2
VOUT
5V
C3
5A
100µF
REFER TO
6.3V
SANYO POSCAP TABLE 2
INTVCC
fSET
RfSET
150k
RSET
8.25k
MARGIN CONTROL
IMPROVE
EFFICIENCY
FOR ≥12V INPUT
SOT-323
DUAL
CMSSH-3C3
4603 F16
Figure 16. 5V at 5A Design Without Differential Amplifier
VOUT
VIN
4.5V TO 20V
TRACK/SS CONTROL
R2
100k
R4
100k
PGOOD
C2
10µF
25V
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
PLLIN TRACK/SS
VOUT
LTM4603
R1
392k
C1
10µF
25V
5% MARGIN
SGND
PGND
REVIEW TEMPERATURE
DERATING CURVE
C6 100pF
VFB
MARG0
MARG1
+
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
MARGIN CONTROL
RfSET
82.5k
VOUT
3.3V
5A
C3
100µF
6.3V
SANYO POSCAP
RSET
13.3k
4603 F17
Figure 17. 3.3V at 5A Design
4603f
20
LTM4603/LTM4603-1
U
U
W
U
APPLICATIO S I FOR ATIO
CLOCK SYNC
VOUT
VIN
4.5V TO 20V
R2
100k
C5
0.01µF
R4
100k
PGOOD
CIN
BULK
OPT.
TABLE 2
+
CIN
10µF
25V
×2 CER
PLLIN TRACK/SS
VOUT
VIN
PGOOD
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R1
392k
LTM4603
SGND
PGND
VFB
MARG0
MARG1
REVIEW TEMPERATURE
DERATING CURVE
C3 100pF
COUT1
22µF
6.3V
MARGIN
CONTROL
+
COUT2
470µF
6.3V
VOUT
1.5V
6A
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
RSET
40.2k
REFER TO
TABLE 2
4603 F18
5% MARGIN
Figure 18. Typical 4.5V-20VIN, 1.5V at 6A Design
CLOCK SYNC 0° PHASE
C10
10µF
25V
C1
10µF
25V
R1
100k
R2
100k
R9
19.1k
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
C12
0.1µF
PLLIN TRACK/SS
VOUT
LTM4603
LTC6908-1
1
R11
118k
2
3
V+
OUT1
GND
OUT2
SET
MOD
2.5V
1.2V
4.5V TO 16V
4
R5
392k
5
SGND
PGND
VFB
MARG0
MARG1
R10
60.4k
1.2V AT 6A
C6 100pF
C4
22µF
6.3V
MARGIN
CONTROL
C5
470µF
6.3V
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
+
R7
60.4k
6
2-PHASE
OSCILLATOR
CLOCK SYNC 180° PHASE
+
C11*
100µF
25V
C3
0.01µF
2.5V
4.5V TO 16V
C2
10µF
25V
R3
100k
R4
100k
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
R6
392k
SGND
PLLIN TRACK/SS
VOUT
LTM4603
PGND
VFB
MARG0
MARG1
2.5V AT 6A
C6 100pF
C7
22µF
6.3V
MARGIN
CONTROL
C8
470µF
6.3V
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
fSET
+
R8
19.1k
4603 F19
*C11 OPTIONAL TO REDUCE LC RINGING.
NOT NEEDED FOR LOW INDUCTANCE PLANE CONNECTIONS
Figure 19. 2-Phase, 2.5V and 1.2V at 6A with Tracking
4603f
21
22
+
C11
100µF
35V
OPT
INTERMEDIATE
BUS
3.3V
C2
10µF
25V
×2
VIN
PGOOD
SGND
MPGM
RUN
COMP
INTVCC
DRVCC
VIN
PGOOD
SGND
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R1
392k
R3
100k
8V TO 16V
5% MARGIN
PGOOD
R2
100k
R27
392k
5% MARGIN
C8
10µF
25V
×2
ON/OFF
R7
100k
PGOOD
R6
100k
8V TO 16V
3.3V OR
APPROPRIATE
–48V
INPUT
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
PGND
LTM4603
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
MARGIN
CONTROL
C8 100pF
R19
30.1k
MARGIN
CONTROL
R12
30.1k
R21
60.4k
R8
13.3k
C7
0.15µF
C12 100pF
TRACK 2.5V
CLOCK SYNC 3
PGND
LTM4603
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
TRACK/SS
CONTROL
CLOCK SYNC 1
3.3V
+
REFER TO
TABLE 2
C3
22µF
6.3V
R17
59k
LTC6902
+
C4
470µF
6.3V
C10
470µF
6.3V
V+
SET
DIV
MOD
PH
GND
OUT1 OUT4
OUT2 OUT3
1.8V AT 6A
REFER TO
TABLE 2
C9
22µF
6.3V
3.3V AT 5A
4-PHASE
OSCILLATOR
8V TO 16V
3.3V
PGND
LTM4603
VIN
PGOOD
SGND
PGND
LTM4603
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
fSET
VOUT_LCL
DIFFVOUT
VOSNS+
VOSNS–
VFB
MARG0
MARG1
PLLIN TRACK/SS
VOUT
CLOCK SYNC 4
SGND
MPGM
RUN
COMP
INTVCC
DRVCC
VIN
PGOOD
CLOCK SYNC 2
MPGM
RUN
ON/OFF
COMP
INTVCC
DRVCC
R14
392k
R16
100k
8V TO 16V
5% MARGIN
PGOOD
R15
100k
R9
392k
ON/OFF
5% MARGIN
PGOOD
R11
100k
3.3V 8V TO 16V
R10
100k
C14
10µF
25V
×2
C14
10µF
25V
×2
C26
0.1µF
4-Phase, Four Outputs (3.3V, 2.5V, 1.8V and 1.5V) with Tracking
MARGIN
CONTROL
C24 100pF
R26
40.2k
MARGIN
CONTROL
C18 100pF
R24
19.1k
R13
40.2k
R25
60.4k
R18
19.1k
R23
60.4k
3.3V
3.3V
+
REFER TO
TABLE 2
C16
22µF
6.3V
+
1.5V AT 6A
REFER TO
TABLE 2
C16
22µF
6.3V
2.5V AT 6A
C15
470µF
6.3V
C15
470µF
6.3V
LTM4603/LTM4603-1
TYPICAL APPLICATIO
4603f
U
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
C(0.30)
PAD 1
1.27
BSC
13.97
BSC
0.12 – 0.28
6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
6.9850
1
5.7150
2
4.4450
3.1750
1.9050
0.6350
0.0000
0.6350
1.9050
3.1750
4.4450
3
4
6
7
8
BOTTOM VIEW
5
13.97
BSC
9
10
SUGGESTED SOLDER PAD LAYOUT
TOP VIEW
5.7150
11
12
DETAIL A
6.9850
bbb Z
PADS
SEE NOTES
3
A
eee M X Y
0.27 – 0.37
SUBSTRATE
DETAIL A
0.60 – 0.66
DETAIL B
0.60 – 0.66
B
C
D
E
F
G
H
J
K
L
M
2.45 – 2.55
MOLD
CAP
Z
DETAIL B
2.72 – 2.92
aaa Z
4
PAD 1
CORNER
(Reference LTM DWG # 05-05-1801 Rev Ø)
LGA Package
118-Lead (15mm × 15mm)
X
DETAILS OF PAD #1 IDENTIFIER ARE OPTIONAL,
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
THE PAD #1 IDENTIFIER MAY BE EITHER A MOLD OR
MARKED FEATURE
4
SYMBOL TOLERANCE
0.10
aaa
0.10
bbb
0.03
eee
LGA 118 0306 REV Ø
6. THE TOTAL NUMBER OF PADS: 118
5. PRIMARY DATUM -Z- IS SEATING PLANE
LAND DESIGNATION PER JESD MO-222, SPP-010
3
2. ALL DIMENSIONS ARE IN MILLIMETERS
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
TOP VIEW
15
BSC
15
BSC
Y
aaa Z
LTM4603/LTM4603-1
PACKAGE DESCRIPTIO
4603f
23
U
LTM4603/LTM4603-1
TYPICAL APPLICATION
3.3V at 5A, LTM4603-1 (No Remote Sense Amplifier)
VIN
4.5V TO 20V
TRACK/SS CONTROL
R2
100k
R4
100k
PGOOD
C2
10µF
35V
R1
392k
VIN
PGOOD
MPGM
RUN
COMP
INTVCC
DRVCC
C1
10µF
35V
SGND
5% MARGIN
REVIEW TEMPERATURE
DERATING CURVE
VOUT
3.3V
C6
5A
100pF +
C3
100µF
6.3V
PLLIN TRACK/SS
VOUT
LTM4603-1
PGND
VFB
MARG0
MARG1
VOUT_LCL
NC3
NC2
NC1
RfSET
82.5k
RSET
13.3k
fSET
4603 TA05
MARGIN CONTROL
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
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Monitors Four Supplies; Adjustable Reset Timer
LTC2923
Power Supply Tracking Controller
Tracks Both Up and Down; Power Supply Sequencing
LT3825/LT3837
Synchronous Isolated Flyback Controllers
No Optocoupler Required; 3.3V, 12A Output; Simple Design
LTM4600
10A DC/DC µModule
Basic 10A Power Supply
LTM4601
12A DC/DC µModule
with PLL, Output Tracking and Margining, LTM4603 Pin Compatible
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6A DC/DC µModule
Basic 6A Power Supply
4603f
24 Linear Technology Corporation
LT 0307 • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408) 432-1900 ● FAX: (408) 434-0507
●
www.linear.com
© LINEAR TECHNOLOGY CORPORATION 2007