Ordering number : ENA0991 LV8071LP Bi-CMOS IC Piezoelectric Actuator Driver IC Overview The LV8071LP is a piezoelectric autofocus actuator driver IC for use in cell phone cameras. It internally generates drive waveforms, which reduces DSP load and makes it possible to control piezoelectric actuators by simple control signals. Features The actuator using the piezoelectric device is driven by the external CLK input and simple control signal. • The 39MHz (CLK1 pin input) CLK input is divided into quarters internally to generate the 9.75MHz input. The operation time is generated using this as a base CLK to ensure the output appropriate for piezoelectric drive. The CLK2 input of 9.75MHz is input to be used, as it is, for the base CLK either. • IC start/stop is controlled by the EN input. Initialization is made according to the built-in sequence at startup. • The actuator drive time is determined by inputting the pulse to the DRIVE pin. • To recognize operation/stop of the actuator, the BUSY signal is output while the OUT pin performs any output. Specifications Maximum Ratings at Ta = 25°C, GND = 0V Parameter Symbol Supply voltage VCC max Output current IO max Input signal voltage VIN max Allowable loss Pd Conditions Ratings Unit -0.5 to 6.0 300 -0.5 to VCC+0.5 Mounted on a specified board* 700 V mA V mW Operating temperature range Topr -20 to +85 °C Storage temperature Tstg -55 to +150 °C Note *: Mounted on a specified board: 40.0mm×50.0mm×0.8mm, glass epoxy board Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer' s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer' s products or equipment. D1907 TI IM 20060124-S00004 No.A0991-1/6 LV8071LP Allowable Operating Condtions at GND = 0V Parameter Symbol Conditions Ratings Unit Supply voltage VCC 2.5 to 3.3 V Input signal voltage VIN 0 to VCC V FCLK1 CLK1 pin 39 MHz Input CLK2 frequency FCLK2 CLK2 pin 9.75 MHz DRIVE “H” minimum pulse width DH min 1clk=1/4CLK1=CLK2 96 clk DRIVE “L” minimum pulse width DL min 1clk=1/4CLK1=CLK2 96 clk Maximum operation cycle frequency Ct max 1 cycle = 87clk Input CLK1 frequency 140 cycles × 170 times Electrical Characteristics at Ta = 25°C, VCC = 2.8V, GND=0V, unless otherwise specified. Parameter Symbol Ratings Conditions min typ Unit max 1.0 μA 0.7 mA Current drain at standby 0 ICC0 No CLK input Current drain during operation ICC1 At CLK1=39MHz “H” level input voltage VIH 2.5V ≤ VCC ≤ 5.5V 0.8 × VCC VCC V “L” level input voltage VIL 2.5V ≤ VCC ≤ 5.5V 0 0.1 × VCC V 0.4 Output block upper-side ON resistance RonP 1.0 1.5 Ω Output block lower-side ON resistance RonN 1.0 1.5 Ω Turn-ON time TPLH at no load * 0.2 μs Turn-OFF time TPHL at no load * 0.2 μs Note: The time for 10→90% at rise and 90→10% at fall is specified. Package Dimensions unit : mm (typ) 3318 TOP VIEW SIDE VIEW BOTTOM VIEW (0.125) (0.13) 2.6 16 0.4 2.6 (C0.116) 2 1 0.5 LASER MARKED INDEX (0.55) 0.25 (0.035) 0.8 SIDE VIEW SANYO : VCT16(2.6X2.6) No.A0991-2/6 LV8071LP Pin Assignment M/I EN VCC (NC) Pd max - Ta 0.8 DRIVE TEST1 15 14 13 1 Allowable Power Dissipation, Pd max - W 16 12 OUT1 11 (NC) 2 LV8071LP TEST2 3 10 RFG CLK1 4 9 (NC) 0.7 0.6 0.5 0.4 0.36 0.3 0.2 0.1 0 -20 5 6 7 8 CLK2 BUSY GND OUT2 Mounted on a specified board: 40.0mm×50.0mm×0.8mm, glass epoxy 4-layer substrate (2S2P) 0 20 40 60 Ambient Temperature, Ta- °C 80 100 ILV00256 Top view Block Diagram VCC CLK1 CLK2 EN M/I Quarterdividing circuit OUT1 CLK select GATE A Actuator drive waveform generated OUT2 GATE B RFG busy BUSY DRIVE TEST1 TEST2 GND Resistance to be provided to the RFG pin In LV8071LP, insertion of the resistor between RFG and GND pins enables suppression of the inrush current to the piezoelectric element. Since the resistance value exerts influence on the actuator operation, determine the constant within the 0Ω to 3.3Ω range while checking the operation. No.A0991-3/6 LV8071LP Description of the Operation • CLK1 and CLK2 inputs CLK1 incorporates the quarter-dividing circuit. To input 39MHz directly, input it directly to the CLK1 pin. When the dividing circuit is provided externally, input 9.75MHz to the CLK2 pin. Short-circuit the unused CLK pin to GND. • 1 cycle: One cycle (8.923μs for CLK1=39MHz or CLK2=9.75MHz) of OUT waveform operation is used as one unit of output operation. The drive waveform appropriate to piezoelectric drive as shown below is generated in IC. (1clk=1/4CLK1=1CLK2) 87clk = 1 cycle 23clk 4clk 34clk • EN input: L input causes the IC functions to stop to suppress the current drain in the standby state. H input causes IC to start. After initialization according to the start sequence, the DRIVE pin is ready to accept the input. • Initialization: Internal sequence to move the actuator to the initial position at start of IC. After the operation of 140 cycles × 170 times in the ∞ direction, the standby time of 140 cycles × 4 times is secured. Then, 140 cycles × 2 times of return operation is made in the macro direction. • DRIVE input: Operation time setting pin. The pin performs 140 cycles of operation per pulse at pulse input. To prevent noise-induced error, the input with the pulse H/L width of 96clk (9.85μs when CLK = 39MHz) respectively is not accepted. • M/I input: Actuator operation direction setting pin. Actuator is set in the macro direction at the input H and in the ∞ direction at the input of L. The actuator stops operation if M/I is changed over even when it is operating with the DRIVE pulse. • TEST1/2 Setting pin for IC inspection. Short-circuit this pin with GND during actual use. • BUSY output: The signal output pin, which outputs “H=VCC voltage while the actuator is operating and “L” when the actuator is stopped. No.A0991-4/6 LV8071LP Timing Chart (For CLK1=39MHz) EN Operation stop with EN input at “L” Macro direction logic select ∞ direction logic select M/I Operation for 2 pulses = 280 cycles DRIVE 8.923μs GATE A Operating in the ∞ direction GATE B Operating in the macro direction Operation start at DRIVE input Returns to “H” with “EN=L” even during operation 280 cycles = 5.00ms BUSY BUSY output “H” only during operation Enlarged view of gate signal sequence Operating in the ∞ direction 8.923μs 2.359μs 2.359μs GATE A 410ns GATE B 3.487μs 3.487μs 8.923μs Operating in the macro direction 410ns GATE A 3.487μs 3.487μs GATE B 2.359μs 2.359μs Initialization sequence at startup Start with EN=H. Initialization sequence starts. EN 8.923μs GATE A GATE B Operating in the ∞ direction Standby state Operating in the macro direction 140 cycles × 170 = 212.3ms 140 cycles × 4 = 5.00ms Initialization about 220ms 140 cycles × 2 = 2.50ms BUSY “H” during initialization even in the standby state BUSY output “L” at end of initialization BUSY output “H” during initialization No.A0991-5/6 LV8071LP SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. 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SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above. This catalog provides information as of December, 2007. Specifications and information herein are subject to change without notice. PS No.A0991-6/6