STMICROELECTRONICS M41T256YMT7F

M41T256Y
256Kbit (32K x 8) serial RTC
Not For New Design
Features
■
5V operating voltage
■
Serial interface supports extended I2C bus
addressing (400kHz)
■
Automatic switchover and deselect circuitry
■
Power-fail deselect voltages:
– M41T256Y: VCC = 4.5 V to 5.5V;
VPFD = 4.2V < VPFD < 4.5V
■
Counters for tenths/hundredths of seconds,
seconds, minutes, hours, day, date, month,
and year
■
Programmable software clock calibration
■
32,752 bytes of general purpose RAM
■
Microprocessor power-on reset
■
Holds microprocessor in reset until supply
voltage reaches stable operating level
■
Automatic address-incrementing
■
Tamper indication circuit with time-stamp
■
Sleep mode function
■
Available in ST’s 44-lead SNAPHAT® SOIC mates with ST’s removable/replaceable
SNAPHAT® battery/crystal top (ordered
separately)
■
RoHS compliant
– Lead-free second level interconnect
SNAPHAT (SH)
crystal/battery
44
1
November 2007
SOH44 (MH)
Rev 5
This is information on a product still in production but not recommended for new designs.
1/30
www.st.com
1
Contents
M41T256Y
Contents
1
Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
2
Operating modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1
3
2-wire bus characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.1
Bus not busy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.1.2
Start data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.3
Stop data transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.4
Data valid . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1.5
Acknowledge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2
Read mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.3
Write mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.4
Data retention mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.5
Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Clock operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.1
Reading the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.2
Setting the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3
Stopping and starting the oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4
Power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5
Tamper indication circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6
Tamper event time-stamp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.7
Calibrating the clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.8
Battery low warning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.9
Preferred power-on/battery attach defaults . . . . . . . . . . . . . . . . . . . . . . . 21
4
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5
DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7
Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
2/30
M41T256Y
8
Contents
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3/30
List of tables
M41T256Y
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
4/30
Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
TIMEKEEPER® register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Preferred default values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
DC and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Crystal electrical characteristics (externally supplied) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Power down/up AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SOH44 – 44-lead plastic small outline, SNAPHAT, package mech. data. . . . . . . . . . . . . . 26
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data. . . . . . . . . 27
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
SNAPHAT® battery table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
M41T256Y
List of figures
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
44-pin SOIC (MH - snaphat) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Serial bus data transfer sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Acknowledgement sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Bus timing requirements sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Slave address location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Alternate read mode sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Write mode sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Crystal accuracy across temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Clock calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power down/up mode AC waveforms. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
SOH44 – 44-lead plastic small outline, SNAPHAT, package outline . . . . . . . . . . . . . . . . . 26
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal outline . . . . . . . . . . . . . . . . . 27
5/30
Summary
1
M41T256Y
Summary
The M41T256Y Serial TIMEKEEPER® SRAM is a low power 256Kbit static CMOS SRAM
organized as 32K words by 8 bits. A built-in 32.768kHz oscillator (external crystal controlled)
and 8 bytes of the SRAM (see Table 3 on page 18) are used for the clock/calendar function
and are configured in binary coded decimal (BCD) format.
Addresses and data are transferred serially via a two line, bi-directional I2C interface. The
built-in address register is incremented automatically after each WRITE or READ data byte.
The M41T256Y has a built-in power sense circuit which detects power failures and
automatically switches to the battery supply when a power failure occurs. The energy
needed to sustain the SRAM and clock operations can be supplied by a lithium button-cell
supply when a power failure occurs. Functions available to the user include a non-volatile,
time-of-day clock/calendar, and power-on reset. The eight clock address locations contain
the year, month, date, day, hour, minute, second, and tenths/hundredths of seconds in 24hour BCD format. Corrections for 28, 29 (leap year - valid until year 2100), 30 and 31 day
months are made automatically. The first clock address location (7FF8h) stores the clock
software calibration settings as well as the write clock bit.
The M41T256Y is supplied in a 44-lead SOIC SNAPHAT® package (MH - which integrates
both crystal and battery in a single SNAPHAT top). The 44-pin, 330mil SOIC provides
sockets with gold-plated contacts at both ends for direct connection to a separate
SNAPHAT housing containing the battery and crystal. The unique design allows the
SNAPHAT battery/crystal package to be mounted on top of the SOIC package after the
completion of the surface-mount process.
Insertion of the SNAPHAT housing after reflow prevents potential battery and crystal
damage due to the high temperatures required for device surface-mounting. The SNAPHAT
housing is also keyed to prevent reverse insertion. The 44-pin SOIC and crystal/battery
packages are shipped separately in plastic, anti-static tubes or in Tape & Reel form. For the
44-lead SOIC, the battery/crystal package (e.g., SNAPHAT) part number is “M4TxxBR12SH” (see Table 14 on page 28).
Caution:
6/30
Do not place the SNAPHAT battery/crystal top in conductive foam, as this will drain the
lithium, button-cell battery.
M41T256Y
Summary
Figure 1.
Logic diagram
VCC
SCL
RST
SDA
M41T256Y
FT
TP
VSS
AI04754b
1. For 44-pin SNAPHAT (MT) package only.
Table 1.
Signal names
FT
Frequency test (open drain)
RST
Reset output (open drain)
SCL
Serial clock input
SDA
Serial data input/output
VCC
Supply voltage
VSS
Ground
TP
Tamper input
7/30
Summary
Figure 2.
M41T256Y
44-pin SOIC (MH - snaphat)
44
1
2
43
3
42
4
41
40
5
39
6
7
38
8
37
9
36
35
10
11 M41T256Y 34
12
33
13
32
14
31
15
30
29
16
17
28
27
18
26
19
20
25
21
24
22
23
NC
NC
NF
RST
NF
NF
NF
NF
NF
NF
NF
TP
NC
NF
NF
NF
NF
SDA
VSS
VSS
NC
VSS
VCC
NC
NC
NC
FT
NF
NF
NF
NF
NF
NF
NC
NC
NF
SCL
NC
NF
NF
NF
NF
NF
NC
AI07022
Figure 3.
Block diagram
PULL-UP TO
CHIP VCC
REAL TIME CLOCK
CALENDAR
32,752 BYTES
USER RAM
SDA
I2C
INTERFACE
RTC
& CALIBRATION
SCL
TAMPER BIT
32KHz
OSCILLATOR
Crystal
FT(1)
TP
POWER
VCC
VBAT
VBL= 2.5V
COMPARE
VSO = VBAT
COMPARE
BL
VPFD = 4.38V
COMPARE
POR
RST(1)
AI04759
1. Open drain output
8/30
M41T256Y
2
Operating modes
Operating modes
The M41T256Y clock operates as a slave device on the serial bus. Access is obtained by
implementing a start condition followed by the correct slave address (D0h). The 256K bytes
contained in the device can then be accessed sequentially in the following order:
0-7FEF = General purpose RAM
7FF0-7FF6 = Reserved
7FF7h = Tenths/hundredths register
7FF8h = Control register
7FF9h = Seconds register
7FFAh = Minutes register
7FFBh = Hour register
7FFCh = Tamper/day register
7FFDh = Date register
7FFEh = Month register
7FFFh = Year register
The M41T256Y clock continually monitors VCC for an out-of tolerance condition. Should
VCC fall below VPFD, the device terminates an access in progress and resets the device
address counter. Inputs to the device will not be recognized at this time to prevent
erroneous data from being written to the device from an out-of-tolerance system. When VCC
falls below VSO, the device automatically switches over to the battery and powers down into
an ultra low current mode of operation to conserve battery life. As system power returns and
VCC rises above VSO, the battery is disconnected, and the power supply is switched to
external VCC. Write protection continues until VCC reaches VPFD plus tREC.
For more information on Battery Storage Life refer to Application Note AN1012.
2.1
2-wire bus characteristics
The bus is intended for communication between different ICs. It consists of two lines: a
bidirectional data signal (SDA) and a clock signal (SCL). Both the SDA and SCL lines must
be connected to a positive supply voltage via a pull-up resistor.
The following protocol has been defined:
●
Data transfer may be initiated only when the bus is not busy.
●
During data transfer, the data line must remain stable whenever the clock line is high.
●
Changes in the data line, while the clock line is high, will be interpreted as control
signals.
Accordingly, the following bus conditions have been defined:
2.1.1
Bus not busy
Both data and clock lines remain High.
9/30
Operating modes
2.1.2
M41T256Y
Start data transfer
A change in the state of the data line, from high to low, while the clock is high, defines the
START condition.
2.1.3
Stop data transfer
A change in the state of the data line, from low to high, while the clock is high, defines the
STOP condition.
2.1.4
Data valid
The state of the data line represents valid data when after a start condition, the data line is
stable for the duration of the high period of the clock signal. The data on the line may be
changed during the Low period of the clock signal. There is one clock pulse per bit of data.
Each data transfer is initiated with a start condition and terminated with a stop condition.
The number of data bytes transferred between the start and stop conditions is not limited.
The information is transmitted byte-wide and each receiver acknowledges with a ninth bit.
By definition a device that gives out a message is called “transmitter,” the receiving device
that gets the message is called “receiver.” The device that controls the message is called
“master.” The devices that are controlled by the master are called “slaves.”
2.1.5
Acknowledge
Each byte of eight bits is followed by one acknowledge clock pulse. This acknowledge clock
pulse is a low level put on the bus by the receiver whereas the master generates an extra
acknowledge related clock pulse. A slave receiver which is addressed is obliged to generate
an acknowledge after the reception of each byte that has been clocked out of the slave
transmitter.
The device that acknowledges has to pull down the SDA line during the acknowledge clock
pulse in such a way that the SDA line is a stable Low during the High period of the
acknowledge related clock pulse. Of course, setup and hold times must be taken into
account. A master receiver must signal an end of data to the slave transmitter by not
generating an acknowledge on the last byte that has been clocked out of the slave. In this
case the transmitter must leave the data line High to enable the master to generate the
STOP condition.
10/30
M41T256Y
Figure 4.
Operating modes
Serial bus data transfer sequence
DATA LINE
STABLE
DATA VALID
(SCL) CLOCK
(SDA) DATA
START
CONDITION
CHANGE OF
DATA ALLOWED
STOP
CONDITION
AI04756
Figure 5.
Acknowledgement sequence
CLOCK PULSE FOR
ACKNOWLEDGEMENT
START
SCL FROM
MASTER
DATA OUTPUT
BY TRANSMITTER
1
MSB
2
8
9
LSB
DATA OUTPUT
BY RECEIVER
AI00601
11/30
Operating modes
Figure 6.
M41T256Y
Bus timing requirements sequence
SDA
tBUF
tHD:STA
tHD:STA
tR
tF
SCL
tHIGH
P
S
tLOW
tSU:DAT
tHD:DAT
tSU:STA
SR
tSU:STO
P
AI00589
Table 2.
AC characteristics
Parameter(1)
Symbol
fSCL
SCL clock frequency
tBUF
Time the bus must be free before a new transmission can
start
tF
Min
Max
Unit
0
400
kHz
1.3
SDA and SCL fall time
tHD:DAT
Data hold time
tHD:STA
µs
300
ns
0
µs
START condition hold time
(after this period the first clock pulse is generated)
600
ns
tHIGH
Clock high period
600
ns
tLOW
Clock low period
1.3
µs
tR
tSU:DAT(2)
SDA and SCL rise time
300
ns
Data setup time
100
ns
tSU:STA
START condition setup time
(only relevant for a repeated start condition)
600
ns
tSU:STO
STOP condition setup time
600
ns
1. Valid for ambient operating temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Transmitter must internally provide a hold time to bridge the undefined region (300ns max) of the falling edge of SCL
2.2
Read mode
In this mode the master reads the M41T256Y slave after setting the slave address (see
Figure 7 on page 13). Following the WRITE mode control bit (R/W=0) and the Acknowledge
Bit, the byte addresses A(0) and A(1) are written to the on-chip address pointer (MSB of
address byte A(0) is a “Don’t care”). Next the START condition and slave address are
repeated followed by the READ mode control bit (R/W=1). At this point the master
transmitter becomes the master receiver. The data byte which was addressed will be
transmitted and the master receiver will send an acknowledge bit to the slave transmitter.
The address pointer is only incremented on reception of an acknowledge clock. The
M41T256Y slave transmitter will now place the data byte at address An+1 on the bus, the
12/30
M41T256Y
Operating modes
master receiver reads and acknowledges the new byte and the address pointer is
incremented to An+2.
This cycle of reading consecutive addresses will continue until the master receiver sends a
STOP condition to the slave transmitter (see Figure 8 on page 14).
Note:
Address pointer will wrap around from maximum address to minimum address if
consecutive READ or WRITE cycles are performed.
An alternate READ mode may also be implemented whereby the master reads the
M41T256Y slave without first writing to the (volatile) address pointer. The first address that
is read is the last one stored in the pointer (see Figure 9 on page 14).
Figure 7.
Slave address location
R/W
SLAVE ADDRESS
1
A
LSB
MSB
START
1
0
1
0
0
0
AI00602
Note:
The most significant bit is sent first.
13/30
Operating modes
S
ACK
ACK
DATA n
ACK
BUS ACTIVITY:
BYTE
ADDRESS (1)
R/W
R/W
BYTE
ADDRESS (0)
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Read mode sequence
START
Figure 8.
M41T256Y
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
S
ACK
ACK
DATA n
ACK
BUS ACTIVITY:
BYTE
ADDRESS (1)
R/W
R/W
BYTE
ADDRESS (0)
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Alternate read mode sequence
START
Figure 9.
AI04760
SLAVE
ADDRESS
STOP
SLAVE
ADDRESS
P
NO ACK
DATA n+X
14/30
AI04760
M41T256Y
2.3
Operating modes
Write mode
In this mode the master transmitter transmits to the M41T256Y slave receiver. Bus protocol
is shown in Figure 10 on page 15. Following the START condition and slave address, a logic
'0' (R/W=0) is placed on the bus and indicates to the addressed device that byte addresses
A(0) and A(1) will follow and is to be written to the on-chip address pointer (MSB of address
byte A(0) is a “Don’t care”).
The data byte to be written to the memory is strobed in next and the internal address pointer
is incremented to the next memory location within the RAM on the reception of an
acknowledge bit. The M41T256Y slave receiver will send an acknowledge bit to the master
transmitter after it has received the slave address (see Figure 7 on page 13) and again after
it has received each address byte.
STOP
R/W
SLAVE
ADDRESS
P
ACK
DATA n+X
ACK
DATA n
ACK
BUS ACTIVITY:
2.4
BYTE
ADDRESS (1)
BYTE
ADDRESS (0)
S
ACK
SDA LINE
ACK
BUS ACTIVITY:
MASTER
START
Figure 10. Write mode sequence
AI04761
Data retention mode
With valid VCC applied, the M41T256Y can be accessed as described above with READ or
WRITE cycles. Should the supply voltage decay, the M41T256Y will automatically deselect,
write protecting itself when VCC falls between VPFD (max) and VPFD (min). This is
accomplished by internally inhibiting access to the clock registers. At this time, the reset pin
(RST) is driven active and will remain active until VCC returns to nominal levels. When VCC
falls below the battery back-up switchover voltage (VSO), power input is switched from the
VCC pin to the external battery and the clock registers and SRAM are maintained from the
attached battery supply.
All outputs become high impedance. On power up, when VCC returns to a nominal value,
write protection continues for tREC. The RST signal also remains active during this time (see
Figure 14 on page 25).
For a further more detailed review of lifetime calculations, please see Application Note
AN1012.
15/30
Operating modes
2.5
M41T256Y
Sleep mode
In order to minimize the battery current draw while in storage, the M41T256Y provides the
user with a battery “sleep mode,” which disconnects the RAM memory array from the
external Lithium battery normally used to provide non-volatile operation in the absence of
VCC. This can significantly extend the lifetime of the battery, when non-volatile operation is
not needed.
Note:
The sleep mode will remove power from the RAM array only and not affect the data retention
of the TIMEKEEPER Registers (7FF0h through 7FFFh - this includes the Calibration
Register).
The sleep mode (SLP) Bit located in register 7FF8h (D6), must be set to a '1' by the user
while the device is powered by VCC. This will “arm” the sleep mode latch, but not actually
disconnect the RAM array from power until the next power-down cycle. This protects the
user from immediate data loss in the event he inadvertently sets the SLP Bit. Once VCC falls
below VSO (VBAT), the sleep mode circuit will be engaged and the RAM array will be isolated
from the battery, resulting in both a lower battery current, and a loss of RAM data.
Note:
Upon initial battery attach or initial power application without the battery, the state of the SLP
Bit will be undetermined. Therefore, the SLP Bit should be initialized to '0' by the user.
Additional current reduction can be achieved by setting the STOP (ST) Bit in register 7FF9h
(D7), turning off the clock oscillator. This combination will result in the longest possible
battery life, but also loss of time and data. When the device is again powered-up, the user
should first read the SLP Bit to determine if the device is currently in sleep mode, then reset
the bit to '0' in order to disable the sleep mode (this will NOT be automatically taken care of
during the power-up).
Note:
16/30
See AN1570, “M41T256Y Sleep Mode Function” for more information on sleep mode and
battery lifetimes.
M41T256Y
3
Clock operation
Clock operation
Year, month, and date are contained in the last three registers of the TIMEKEEPER®
register map (see Table 3 on page 18). Bits D0 through D2 of the next register contain the
day (day of week). Finally, there are the registers containing the seconds, minutes, and
hours, respectively. The first clock register is the control register (this is described in the
clock calibration section).
The nine clock registers may be read one byte at a time, or in a sequential block. The control
register (Address location 7FF8h) may be accessed independently. Provision has been
made to assure that a clock update does not occur while any of the nine clock addresses
are being read. If a clock address is being read, an update of the clock registers will be
halted. This will prevent a transition of data during the read.
3.1
Reading the clock
The nine byte clock register (see Table 3 on page 18) is used to both set the clock and to
read the date and time from the clock, in a binary coded decimal format. The system-to-user
transfer of clock data will be halted whenever the address being read is a clock address
(7FF9h to 7FFFh). The update will resume either due to a stop condition or when the pointer
increments to a RAM address.
This prevents reading data in transition. The TIMEKEEPER® cells in the register map are
only data registers and not actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
3.2
Setting the clock
Bit D7 of the control register (7FF8h) is the write clock bit. Setting the write clock bit to a '1'
will allow the user to write the desired day, date, and time data in 24-hour BCD format.
Resetting the write clock bit to a '0' then transfers the values of all time registers (7FF8h7FFFh) to the actual clock counters and resets the internal divider (or clock) chain.
Note:
The tenths/hundredths of seconds register will automatically be reset to zero when the
WRITE clock bit is set.
Other register bits such as FT, TEB, and ST may be written without setting the WC Bit. In
such cases, the clock data will be undisturbed and will retain their previous values.
3.3
Stopping and starting the oscillator
The oscillator may be stopped at any time. If the device is going to spend a significant
amount of time on the shelf, the oscillator can be turned off to minimize current drain on the
battery. The stop bit (ST) is the most significant bit of the seconds register. Setting it to '1'
stops the oscillator. Setting it to '0' restarts the oscillator in approximately one second.
17/30
Clock operation
M41T256Y
Table 3.
TIMEKEEPER® register map
Data
Function/Range
Address
D7
7FFFh
D6
D5
D4
D3
D2
10 years
D0
BCD Format
Year
Year
00-99
Month
Month
01-12
Date: Day of Month
Date
01-31
Tamper/day
0-1/01-07
Hours (24 Hour Format)
Hours
00-23
7FFEh
0
0
7FFDh
0
0
7FFCh
BL
FT
7FFBh
0
0
7FFAh
0
10 minutes
Minutes
Minutes
00-59
7FF9h
ST
10 seconds
Seconds
Seconds
00-59
7FF8h
WC
7FF7h
0
D1
10M
10 date
TEB
TB
10 hours
SLP
0
S
Day of Week
Calibration
0.1 Seconds
Control
0.01 Seconds
Seconds
7FF6h
X
X
X
X
X
X
X
X
Reserved
7FF5h
X
X
X
X
X
X
X
X
Reserved
7FF4h
X
X
X
X
X
X
X
X
Reserved
7FF3h
X
X
X
X
X
X
X
X
Reserved
7FF2h
X
X
X
X
X
X
X
X
Reserved
7FF1h
X
X
X
X
X
X
X
X
Reserved
7FF0h
X
X
X
X
X
X
X
X
Reserved
00-99
Keys:
S = Sign bit
FT = Frequency test bit
ST = Stop bit
WC = Write clock bit
X = '1' or '0'
BL = Battery low flag (read only bit)
TB = Tamper bit (read only bit)
TEB = Tamper enable bit
0 = Must be set to '0'
SLP = Sleep mode bit
Note:
7FF0h through 7FF6h are invalid addresses and when read will return arbitrary data.
3.4
Power-on reset
The M41T256Y continuously monitors VCC. When VCC falls to the power fail detect trip
point, the RST pulls low (open drain) and remains low on power-up for tREC after VCC
passes VPFD (max). The RST pin is an open drain output and an appropriate pull-up resistor
should be chosen to control rise time.
18/30
M41T256Y
3.5
Clock operation
Tamper indication circuit
The M41T256Y provides an independent input pin, the tamper pin (TP) which can be used
to monitor a signal which can result in the setting of the tamper bit (TB) if the tamper enable
bit (TEB) is set to a '1.'
The tamper pin is triggered by being connected to VCC/VBAT through an external switch.
This switch is normally open in the application, allowing the pin to be “floating” (internally
latched to VSS when TEB is set). When this switch is closed (connecting the pin to
VCC/VBAT), the tamper bit will be immediately set. This allows the user to determine if the
device has been physically moved or tampered with. The tamper bit is a “read only” bit and
is reset only by taking the tamper pin to ground and resetting the tamper enable bit to '0.'
This function operates both under normal power, and in battery back-up. If the switch closes
during a power-down condition, the bit will still be set correctly.
Note:
Upon initial battery attach or initial power application without the battery, the state of TEB
(and TB) will be undetermined. Therefore TEB must be initialized to a '0.'
3.6
Tamper event time-stamp
If a tamper occurs, not only will the tamper bit be set, but the event will also automatically be
time-stamped. This is accomplished by freezing the normal update of the clock registers
(7FF7h through 7FFFh) immediately following a tamper event. Thus, when tampering
occurs, the user may first read the time registers to determine exactly when the tamper
event occurred, then re-enable the clock update to the current time (and reset the Tamper
Bit, TB) by resetting the tamper enable bit (TEB).
The time update will then resume, and after either a stop condition or incrementing the
address pointer to a RAM address and back, the clock can be read to determine the current
time.
Note:
The tamper bit (TB) must always be set to '0' in order to read the current time.
3.7
Calibrating the clock
The M41T256Y is driven by a quartz controlled oscillator with a nominal frequency of
32,768Hz. The devices are tested not exceed ±35 ppm (parts per million) oscillator
frequency error at 25oC, which equates to about ±1.53 minutes per month. When the
calibration circuit is properly employed, accuracy improves to better than +1/–2 ppm at
25°C.
The oscillation rate of crystals changes with temperature (see Figure 11 on page 20).
Therefore, the M41T256Y design employs periodic counter correction. The calibration circuit
adds or subtracts counts from the oscillator divider circuit at the divide by 256 stage, as
shown in Figure 12 on page 20. The number of times pulses which are blanked (subtracted,
negative calibration) or split (added, positive calibration) depends upon the value loaded into
the five calibration bits found in the control register. Adding counts speeds the clock up,
subtracting counts slows the clock down.
The calibration bits occupy the five lower order bits (D4-D0) in the control register (7FF8h).
These bits can be set to represent any value between 0 and 31 in binary form. Bit D5 is a
sign bit; '1' indicates positive calibration, '0' indicates negative calibration. Calibration occurs
within a 64 minute cycle. The first 62 minutes in the cycle may, once per minute, have one
19/30
Clock operation
M41T256Y
second either shortened by 128 or lengthened by 256 oscillator cycles. If a binary '1' is
loaded into the register, only the first 2 minutes in the 64 minute cycle will be modified; if a
binary 6 is loaded, the first 12 will be affected, and so on.
Therefore, each calibration step has the effect of adding 512 or subtracting 256 oscillator
cycles for every 125,829,120 actual oscillator cycles, that is +4.068 or –2.034 ppm of
adjustment per calibration step in the calibration register. Assuming that the oscillator is
running at exactly 32,768Hz, each of the 31 increments in the calibration byte would
represent +10.7 or –5.35 seconds per month which corresponds to a total range of +5.5 or –
2.75 minutes per month.
Figure 11. Crystal accuracy across temperature
Frequency (ppm)
20
0
–20
–40
–60
–80
ΔF = K x (T –T )2
O
F
–100
K = –0.036 ppm/°C2 ± 0.006 ppm/°C2
–120
TO = 25°C ± 5°C
–140
–160
–40
–30
–20
–10
0
10
20
30
40
50
60
70
80
Temperature °C
AI00999b
Figure 12. Clock calibration
NORMAL
POSITIVE
CALIBRATION
NEGATIVE
CALIBRATION
AI00594B
Two methods are available for ascertaining how much calibration a given M41T256Y may
require.
20/30
M41T256Y
Clock operation
The first involves setting the clock, letting it run for a month and comparing it to a known
accurate reference and recording deviation over a fixed period of time. Calibration values,
including the number of seconds lost or gained in a given period, can be found in Application
Note AN934: TIMEKEEPER CALIBRATION. This allows the designer to give the end user
the ability to calibrate the clock as the environment requires, even if the final product is
packaged in a non-user serviceable enclosure. The designer could provide a simple utility
that accesses the calibration byte.
The second approach is better suited to a manufacturing environment, and involves the use
of the FT pin. The pin will toggle at 512Hz, when the stop bit (ST) is '0,' and the frequency
test bit (FT) is '1.'
Any deviation from 512Hz indicates the degree and direction of oscillator frequency shift at
the test temperature. For example, a reading of 512.010124Hz would indicate a +20 ppm
oscillator frequency error, requiring a –10 (XX001010) to be loaded into the calibration byte
for correction. Note that setting or changing the calibration byte does not affect the
frequency test output frequency.
The FT pin is an open drain output which requires a pull-up resistor to VCC for proper
operation. A 500 to 10k resistor is recommended in order to control the rise time. The FT bit
is cleared on power-down.
3.8
Battery low warning
The M41T256Y automatically performs battery voltage monitoring upon power-up. The
battery low (BL) bit, bit D7 of day register, will be asserted if the battery voltage is found to
be less than approximately 2.5V. The BL bit will remain asserted until completion of battery
replacement and subsequent battery low monitoring tests, during the next power-up
sequence.
If a battery low is generated during a power-up sequence, this indicates that the battery is
below approximately 2.5 volts and may not be able to maintain data integrity in the SRAM.
Data should be considered suspect and verified as correct. A fresh battery should be
installed. The battery may be replaced while VCC is applied to the device.
The M41T256Y only monitors the battery when a nominal VCC is applied to the device. Thus
applications which require extensive durations in the battery back-up mode should be
powered-up periodically (at least once every few months) in order for this technique to be
beneficial. Additionally, if a battery low is indicated, data integrity should be verified upon
power-up via a checksum or other technique.
3.9
Preferred power-on/battery attach defaults
See Table 4, below.
Table 4.
Preferred default values
Condition
WC
TEB(1)
TB(1)
FT
ST(1)
SLP(1)
Battery attach or initial power-up
0
X
X
0
X
X
Power-cycling (with battery)
0
UC
UC
0
UC
UC
1. X = Undetermined; UC = Unchanged
21/30
Maximum rating
4
M41T256Y
Maximum rating
Stressing the device above the rating listed in the “Absolute Maximum Ratings” table may
cause permanent damage to the device. These are stress ratings only and operation of the
device at these or any other conditions above those indicated in the Operating sections of
this specification is not implied. Exposure to Absolute Maximum Rating conditions for
extended periods may affect device reliability. Refer also to the STMicroelectronics SURE
Program and other relevant quality documents.
Table 5.
Absolute maximum ratings
Symbol
Parameter
Value
Unit
TSTG
Storage temperature (VCC off, oscillator off)
SNAPHAT®
–40 to 85
°C
TSLD(1)
SOIC
–55 to 125
°C
Lead solder temperature for 10 seconds
260
°C
VIO
Input or output voltages
–0.3 to VCC + 0.3
V
VCC
Supply voltage
–0.3 to 7.0
V
IO
Output current
20
mA
PD
Power dissipation
1
W
1. For SO package, standard (SnPb) lead finish: Reflow at peak temperature of 225°C (total thermal budget
not to exceed 180°C for between 90 to 150 seconds).
For SO package, Lead-free (Pb-free) lead finish: Reflow at peak temperature of 260°C (total thermal
budget not to exceed 245°C for greater than 30 seconds).
Caution:
Negative undershoots below –0.3V are not allowed on any pin while in the Battery Back-up
mode.
Caution:
Do NOT wave solder SOIC to avoid damaging SNAPHAT sockets.
22/30
M41T256Y
5
DC and AC parameters
DC and AC parameters
This section summarizes the operating and measurement conditions, as well as the DC and
AC characteristics of the device. The parameters in the following DC and AC Characteristic
tables are derived from tests performed under the Measurement Conditions listed in Table 6:
DC and AC measurement conditions. Designers should check that the operating conditions
in their projects match the measurement conditions when using the quoted parameters.
Table 6.
DC and AC measurement conditions
Parameter
M41T256Y
VCC Supply voltage
4.5 to 5.5V
Ambient operating temperature
–25 to 70°C
Load capacitance (CL)
100pF
Input rise and fall times
≤ 50ns
Input pulse voltages
0.2VCC to 0.8VCC
Input and output timing ref. voltages
0.3VCC to 0.7VCC
Figure 13. AC testing input/output waveforms
0.8VCC
0.2VCC
0.7VCC
0.3VCC
AI02568
Table 7.
Capacitance
Parameter(1) and (2)
Symbol
CIN
CIO(3)
tLP
Min
Max
Unit
7
pF
1000
pF
Input / output capacitance
10
pF
Low-pass filter input time constant (SDA and SCL)
50
ns
Input capacitance
Input capacitance (tamper pin)
1. Effective capacitance measured with power supply at 5V; sampled only, not 100% tested.
2. At 25°C, f = 1MHz.
3. Outputs deselected.
23/30
DC and AC parameters
Table 8.
Sym
IBAT
DC characteristics
Battery current OSC ON
ICC2
Supply current (standby)
Typ
Max
Unit
1.5
1.9
µA
1.0
1.4
µA
f = 400kHz
1.4
3.0
mA
SCL, SDA = VCC – 0.3V
1.0
2.5
mA
0V ≤ VIN ≤ VCC
±1
µA
0V ≤ VOUT ≤ VCC
±1
µA
0.7VCC
VCC + 0.3
V
VBAT – Vdiode
VBAT
V
–0.3
0.3VCC
V
2.5
3.5
V
VCC + 0.3
V
TA = 25°C, VCC = 0V, VBAT = 3.0V
Input leakage current
Output leakage current
VIH
Input high voltage
VIHB
Input high voltage in battery
back-up for tamper pin
VIL
Min
Battery current OSC OFF
Supply current
ILO(2)
Test condition(1)
Parameter
ICC1
ILI
M41T256Y
Input low voltage
VBAT Battery voltage
VOH
VOL
Output high voltage
Output low voltage
IOL = 3.0mA
0.4
V
Output low voltage (open
drain)(3)
IOL = 10mA
0.4
V
4.50
V
VPFD Power fail deselect
4.20
VSO
Battery back-up switchover
RSW
Switch resistance on tamper
pin
VBAT
V
500
W
1. Valid for ambient operating temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. Outputs deselected.
3. For RST and FT pin (open drain).
Table 9.
Crystal electrical characteristics (externally supplied)
Parameter(1)
Symbol
f0
Resonant frequency
RS
Series resistance
CL
Load capacitance
Typ
Min
Max
Unit
32.768
kHz
35
12.5
1. Load capacitors are integrated within the M41T256Y. Circuit board layout considerations for the 32.768kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
24/30
kΩ
pF
M41T256Y
DC and AC parameters
Figure 14. Power down/up mode AC waveforms
VCC
VPFD (max)
VPFD (min)
VSO
tF
tR
tFB
tRB
tDR
INPUTS
RECOGNIZED
tREC
DON'T CARE
RECOGNIZED
RST
HIGH-Z
OUTPUTS
VALID
VALID
(PER CONTROL INPUT)
(PER CONTROL INPUT)
AI04757
Table 10.
Symbol
Power down/up AC characteristics
Parameter(1)
Min
Typ
Max
Unit
tF(2)
tFB(3)
VPFD (max) to VPFD (min) VCC fall time
300
µs
VPFD (min) to VSS VCC fall time
10
µs
tR
VPFD (min) to VPFD (max) VCC rise time
10
µs
tRB
VSS to VPFD (min) VCC rise time
1
µs
tREC
Power up deselect time
tDR
Expected data retention time (OSC on, sleep mode off)
40
7.2(4)
200
ms
years
1. Valid for ambient operating temperature: TA = –25 to 70°C; VCC = 4.5 to 5.5V (except where noted).
2. VPFD (max) to VPFD (min) fall time of less than tF may result in deselection/write protection not occurring until 200µs after
VCC passes VPFD (min).
3. VPFD (min) to VSS fall time of less than tFB may cause corruption of RAM data.
4.
At 25°C and VCC = 0V with the oscillator running and using M4T32-BR12SH SNAPHAT battery top.
25/30
Package mechanical data
6
M41T256Y
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label. ECOPACK is an ST trademark.
ECOPACK specifications are available at: www.st.com.
Figure 15. SOH44 – 44-lead plastic small outline, SNAPHAT, package outline
A2
A
C
B
eB
e
CP
D
N
E
H
A1
α
L
1
SOH-A
Note:
Drawing is not to scale.
Table 11.
SOH44 – 44-lead plastic small outline, SNAPHAT, package mech. data
mm
inches
Symb
Typ
Min
A
Typ
Min
3.05
Max
0.120
A1
0.05
0.36
0.002
0.014
A2
2.34
2.69
0.092
0.106
B
0.36
0.46
0.014
0.018
C
0.15
0.32
0.006
0.012
D
17.71
18.49
0.697
0.728
E
8.23
8.89
0.324
0.350
–
–
–
–
eB
3.20
3.61
0.126
0.142
H
11.51
12.70
0.453
0.500
L
0.41
1.27
0.016
0.050
a
0°
8°
0°
8°
N
44
e
CP
26/30
Max
0.81
0.032
44
0.10
0.004
M41T256Y
Package mechanical data
Figure 16. SH – 4-pin SNAPHAT housing for 120mAh battery & crystal outline
A1
A2
A3
A
eA
B
L
eB
D
E
SHTK-A
Note:
Drawing is not to scale.
Table 12.
SH – 4-pin SNAPHAT housing for 120mAh battery & crystal, mechanical data
mm
inches
Symb
Typ
Min
A
Max
Typ
Min
10.54
Max
0.415
A1
8.00
8.51
0.315
.0335
A2
7.24
8.00
0.285
0.315
B
0.46
0.56
0.018
0.022
D
21.21
21.84
0.835
0.860
E
17.27
18.03
0.680
.0710
eA
15.55
15.95
0.612
0.628
eB
3.20
3.61
0.126
0.142
L
2.03
2.29
0.080
0.090
A3
0.38
0.015
27/30
Part numbering
M41T256Y
7
Part numbering
Table 13.
Ordering information scheme
Example:
M41T
256Y
MT
7
E
Device type
M41T
Supply voltage and write protect voltage
256Y = VCC = 4.5 to 5.5V; VPFD = 4.2 to 4.5V
Package
MH(1) = SOH44
Temperature range
7 = –25 to 70°C
Shipping method
E = Lead-free package (ECOPACK®), tubes
F = Lead-free package (ECOPACK®), tape & reel
1. The SOIC package (SOH44) requires the SNAPHAT® battery package which is ordered separately under the part
number “M4Txx-BR12SH” in plastic tubes (see Table 14).
Caution:
Do not place the SNAPHAT battery package “M4TXX-BR12SH” in conductive foam as it will
drain the lithium button-cell battery.
For other options, or for more information on any aspect of this device, please contact the
ST sales office nearest you.
Table 14.
28/30
SNAPHAT® battery table
Part Number
Description
Package
M4T32-BR12SH
Lithium battery (120mAh) SNAPHAT
SH
M41T256Y
8
Revision history
Revision history
Table 15.
Document revision history
Date
Version
Revision Details
February 2002
1.0
First Issue
26-Apr-02
1.1
Addition of “Tamper Event Time-Stamp” text
31-May-02
1.2
Add Sleep Mode, 44-pin with SNAPHAT package (Figure 2, 5, 19, 20;
Table 1, 5, 14, 15, 12, 13).
03-Jul-02
1.3
Modify Crystal Electrical Characteristics table footnotes (Table 9).
12-Jul-02
1.4
Added programmable Sleep Mode information to document (Figure 3, 4,
5, 6; Table 3, 4)
29-Jul-02
1.5
Add “Hatless” to package description (Figure 1,18) and Table 14, 11)
20-Dec-02
2.0
ICC Characteristics changed (Table 8); Document promoted to
“Datasheet”
04-Jan-03
2.1
Add VOL value (Table 8)
26-Mar-03
2.2
Update test condition (Table 10)
15-Jun-04
3.0
Reformatted; add Lead-free information; update characteristics (Figure
14; Table 5, 14)
16-Apr-2007
4
Reformatted document. Updated packaging references that only 44-lead
SNAPHAT available (cover page, Summary, Figure 1, Table 1, Table 13).
Updated Table 9, 10.
09-Nov-2007
5
Added lead-free second level interconnect information to cover page and
Section 6: Package mechanical data; product status “Not for New
Design”; updated Table 13.
29/30
M41T256Y
Please Read Carefully:
Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the
right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any
time, without notice.
All ST products are sold pursuant to ST’s terms and conditions of sale.
Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no
liability whatsoever relating to the choice, selection or use of the ST products and services described herein.
No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this
document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products
or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such
third party products or services or any intellectual property contained therein.
UNLESS OTHERWISE SET FORTH IN ST’S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED
WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED
WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS
OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT.
UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT
RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING
APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY,
DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE
GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER’S OWN RISK.
Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void
any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any
liability of ST.
ST and the ST logo are trademarks or registered trademarks of ST in various countries.
Information in this document supersedes and replaces all information previously supplied.
The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners.
© 2007 STMicroelectronics - All rights reserved
STMicroelectronics group of companies
Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America
www.st.com
30/30