MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
DESCRIPTION
PIN CONFIGURATION (TOP VIEW)
The M52693SP is a semiconductor integrated circuit developed for
analog signal processing of a picture-in-picture system, consisting
of a sync separator, an ACC, a burst lock clock generator circuit,
an analog switch and a clamp circuit, etc. It is also available on
digital video signal systems other than the above.
PIP CVBS OUT
1
30 SUB CLAMP OUT
GND
2
29 REFERENCE A/D+
MAIN CLAMP CAP.
3
28 SMALL LUMA IN
VIDEO IN 1
4
27 REFERENCE A/D-
VCC2
VCC
5
26 SMALL CHROMA IN
6
25 GND 2
VIDEO IN 2
7
24 BURST GATE IN
APC FILTER
8
23 VCA OUT
VCXO OUT
9
22 FREE RUN CONTROL
FEATURES
Low power dissipation of supply voltage 5.0V and circuit current
32mA (Typ.)
Built-in 4fsc burst lock clock generator circuit required for digital
video signal processing
Small picture chroma level following main picture burst level
Main picture pedestal level matching small picture pedestal level
Built-in reference voltage source for A/D converter
ACC FILTER 10
21 FSC OUT
VCXO IN 11
20 INPUT SW CONTROL 1
VCA CAP. 12
APPLICATION
19 4FSC OUT
MAIN CHROMA IN 13
18 INPUT SW CONTROL 2
MAIN VIDEO OUT 14
17 SUPER SWITH
TV, VCR
SYNC SEP. IN 15
RECOMMENDED OPERATING CONDITION
16 SYNC SEP. OUT
Outline 30P4B
Supply voltage range...................................................... 4.7 to 5.3V
Rated supply voltage.................................................................5.0V
BLOCK DIAGRAM
SUPER
REFERENCE
REFERENCE
4FSC
SUB
A/D+ SMALL A/D- SMALL
BURST
FREE
INPUT OUT
INPUT SWITH SYNC
CLAMP
LUMA
CHROMA
GATE VCA
RUN
FSC
SW
SW
SEP.
OUT
IN
IN
GND 2
IN
OUT CONTROL OUT CONTROL 1
CONTROL 2
OUT
21
23
22
20
30
29
28
27
24
19
18
17
26
25
16
MIX.
CHFOMA
VCA
BGP
GEN.
FREE RUN
CTRL.
bgp
REF.
S2
MAIN
CLAMP
SW
CTRL.
fsc
S3
SW
CTRL.
4fsc
S2
SW
CTRL.
S1
SYNC
SEPARATOR
S3
bgp
1/4
DEV.
bgp
S1
PHASE
COMP.
CLAMP
1
2
PIP
CVBS
OUT
GND
3
4
LEVEL
DET.
VCXO
ACC
CLAMP
5
MAIN VIDEO VCC2
CLAMP
IN 1
CAP.
6
VCC
7
8
9
10
11
VIDEO APC
VCXO ACC
VCXO
IN 2 FILTER OUT FILTER
IN
12
13
14
15
VCA
MAIN
MAIN SYNC
CAP. CHROMA VIDEO SEP.
IN
OUT
IN
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS (Ta=25°C, unless otherwise noted)
Symbol
VCC
Pd
Topr
Tstg
Parameter
Supply voltage
Power dissipation
Operating temperature
Storage temperatare
Ratings
6.0
1265
-20 to +75
-40 to +125
Unit
V
mW
°C
°C
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
ELECTRICAL CHARACTERISTICS TEST METHOD
VR
VR=VRH-VRL
VSOH, VSOL, tH and tPDH
SYNC IN
(PG 1 )
tPDH
tH
SYNC OUT
(Pin 16 )
VSOH
VSOL
GND
Measure tH and t PDH when the input amplitude of pin
is 0.1VP-P.
Make sure that tH and tPDH are within the allowable range. When
the input amplitude of pin 15 is 0.6VP-P, make sure that tH and t PDH
are within the allowable range.
If the voltage which appears at pin 30 when pin 18 is "H" is taken
as Vsub1, and the voltage which appears at pin 30 when pin 18 is
"L" is taken as Vsub2, the clamp offset is given by the following
expression:
DVSRB = (Vsub1 - V27), (Vsub2 - V27)
Vsub and ∆VSRB
Gsub
Measure pin 30 DC output voltage in correspondence to the "H"
and "L" states of pin 18 .
Measure pin
pin 18 .
Sync-in
15
30
gain in correspondence to the "H" and "L" states of
CTsub, Cmain, and CTPIP
Measure crosstalk under the following input conditions:
Prameter
Input signal
Pin connection
Switching condition:Left
Input codition:Right
4
CTsub
CTmain
CTPIP
CTsub 1
Ctsub 2
CTmain 1
CTmain 2
CTPIP 1
CTPIP 2
Sine wave
Amplitude
0.3VP-P
Frequency
3.58MHz
b
a
b
a
b
a
17
0V
0V
0V
0V
7
IN
-IN
-IN
--
a
b
a
b
a
b
-IN
-IN
-IN
0
0
18
5
0
5V
5V
20
0V
0V
0V
5V
0V
0V
0V
0V
5
0
0V
5V
5V
0V
fBWsub
fBWmain
Measure pin 30 frequency characteristics in correspondence to the
"H" and "L" states of pin 18 . Condition: ≤-3dB
Measure pin
Vmain
∆VPIP
Measure pin 14 DC output voltage in correspondence to the "H"
and "L" states of pin 20 .
If the voltage which appears at pin 1 when pin 20 is "H" is taken
as Vpip1, and the voltage which appears at pin 1 when pin 20 is
"L" is taken as Vpip2, ∆VPIP is given by the following expression:
14
frequency characteristics in correspondence to the
"H" and "L" states of pin
20
. Condition: ≤-3dB
Gmain
Measure pin
pin 20 .
14
gain in correspondence to the "H" and "L" states of
∆VPIP = Vpip1 - VPIP , Vpip2 - VPIP
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
GPIPSC
CTPIPS
Pin 12 = 2.185V V1 = Amplitude of pin
GPIPSC = 20 log (V1/V23)
1
V23 = Amplitude of pin
23
GPIP
Measure pin
pin 20 .
1
gain in correspondence to the "H" and "L" states of
fBWPIP
Measure pin 1 frequency characteristics in correspondence to the
"H" and "L" states of pin 20 . Condition: ≤-3dB
Apply 5.0V to pin 20 . Define as VOS1 the amplitude which appears
at pin 1 a when pin 17 is "H", and as VOM1 the amplitude which
appears when pin 17 is "L". Then apply 0V to pin 20 . Define as
VOS2 the amplitude which appears at pin 1 when pin 17 is "H",
and as VOM2 the amplitude which appears at pin 1 when "L".
CTPIPS is given under the above conditions by the equation given
below.
CTPIPS=20log (VOMI/VOSI), 201log (VOM2/VOS2)
VCAtyp, VCAmax, VCAmin, Gmax, Lvca
20 log {(amplitude of pin 23)/SG5}
fBWPIPS
Condition: ≤-3dB
V4fSCH, L; VfSCH, L; 4fsc; fsc
Make sure that the input signal at pin 13 is synchronous with the
output signal at pin 19 .
4fSC
PIN 19
V4fSCL
V4fSCH
GND
fSC
PIN 21
VfSCL
VfSCH
GND
fcp (+)
C-IN
1) Raise the frequency of SG8 input signal so that the signal is
synchronous with pin 19 output signal.
2) Lower the SG8 frequency.
Make sure that the pin 13 input signal is synchronous with the pin
19 output signal when the input amplitude of pin 13 is 0.20VP-P.
Then make sure that the pin 13 input signal is synchronous with the
pin 19 output signal when the input amplitude is 0.01VP-P.
3) Measure the SG8 frequency (f1) when the SG8 input signal is
synchronous with the pin 19 output signal.
4) fcp(+) = f1 - fc (fc = 3.579545MHz)
fcp (-)
1) Lower the frequency of SG8 input signal so that the signal is
synchronous with pin 19 output signal.
2) Raise the SG8 frequency.
3) Measure the SG8 frequency (f2) when the SG8 input signal is
synchronous with the pin 19 output signal.
4) fcp(-) = f2 - fc (fc = 3.579545MHz)
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
INPUT SIGNAL
SG No.
SG1
Input signal
NTSC system composite video signal (1VP-P)
SG2
Sine wave
Frequency: 3.58MHz
Amplitude : 0.1VP-P
− − −
SG2'
Sine wave
Frequency: 3.58MHz
Amplitude : 0.2VP-P
− − −
SG2''
Sine wave
Frequency: 3.58MHz
Amplitude : 0.01VP-P
− − −
SG3
Sine wave
Frequency: 3.58MHz
Amplitude : 0.3VP-P
SG4
C-Sync + sine wave
C-Sync
Frequency: 15.734kHz
Amplitude : 0.285VP-P
Sine wave
Frequency: 1/10MHz
Amplitude : 0.715VP-P
SG5
Sine wave
Frequency: 3.58MHz
Amplitude : 0.2VP-P
Remarks
− − −
− − −
Y signal
Amplitude : 0.715VP-P
SG6
SG7
Sine wave
Frequency: 1/10MHz
Amplitude : 0.2VP-P
− − −
SG8
Sine wave
Frequency: Variable
Amplitude : 0.1VP-P
− − −
PG1
C-Sync
Frequency: 15.734kHz
Amplitude : 0.3VP-P
VOL=2.75V
PG1'
C-Sync
Amplitude : 0.1VP-P
0.6VP-P
VOL
− − −
MITSUBISHI ICs (AV COMMON)
M52693SP
BURST LOCK CLOCK GENERATOR
TEST CIRCUIT
M
1
30
2
29
10µ
75 10µ
a
M
M
SW28
3
28
4
27
0.01µ
b
a
SW4
10µ
10µ
b
M
5
26
b
a
6 75 10µ
a
10µ
6
25
7
24
b
8
23
M
9
22
22
10
21
M
11
20
20
12
19
M
13
18
18
14
17
17
15
16
M
0.01µ
2.2µ
330
0.01µ
BGP in
1.5k
0.47µ
0.01µ
10µ
75
SW7
10µ
M
500
M
SW26
5
10µ
75
51
1M
10µ
SW11
75
1µ
a
1µ
SW13
b
M
Notes:
1. Capacitance values are in FARADS
2. Resistors are in OHMS
3.
: VCC
: GND
TYPICAL CHARACTERISTICS
THERMAL DERATING (MAXIMUM RATING)
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-20 0
20 40 60 80 100 120 140 160
25
75
125
AMBIENT TEMPERATURE Ta (°C)
Units
Resistance : Ω
Capacitance : F