19-5523; Rev 0; 9/10 Dual-Pair LLT with Charge Pump and High-ESD Protection Features The MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for industrial and metering applications. Voltages VCC and VL set the logic levels on either side of the device. Logic-high signals present on the VL side of the device appear as highvoltage logic signals on the VCC side of the device and vice versa. S Ultra-Low Shutdown Supply Current, 0.01µA (typ) S Ultra-Low VL Supply Current, 1µA (max) S Operates Down to 1.6V on VL S Continuous Current Drive Capability > 10mA S Extended ESD Protection on VCC Input and Output Lines ±25kV Human Body Model ±15kV IEC 61000-4-2 Air-Gap Discharge ±12kV IEC 61000-4-2 Contact Discharge The device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logiclevel translator from a high voltage to a low voltage. The device also features a high-efficiency charge pump to boost the battery input, VBAT, to VCC (5V). S 16-Pin QSOP Package S -40NC to +85NC Extended Operating Temperature Range The device features an extreme power-saving mode that reduces supply current to a typical 0.01FA. The device also features thermal short-circuit protection for enhanced protection in applications that route signals externally. Applications Automatic Meter Reader Remote Communications System Industrial Networking In addition, the device features enhanced high electrostatic discharge (ESD) Human Body Model (HBM) protection on OUTAVCC, INBVCC, OUTCVCC, and INDVCC ports up to Q25kV. The MAX14569 is available in a 16-pin QSOP package, and is specified over the -40NC to +85NC extended temperature range. Ordering Information PART MAX14569EEE+T TEMP RANGE PIN-PACKAGE -40NC to +85NC 16 QSOP +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel. Typical Operating Circuit LITHIUM BATTERY 1.8V TO 3.3V 0.1μF 1μF 0.47μF VL µPROCESSOR VBAT CP1 CP2 CHARGE PUMP EN ENAB DATA INAVL DATA OUTBVL VCC OUTAVCC INBVCC 5V 2.2μF METER TRANSMITTER UNIT GND EN ENCD DATA INCVL DATA OUTDVL MAX14569 OUTCVCC INDVCC GND GND METER TRANSMITTER UNIT GND ________________________________________________________________ Maxim Integrated Products 1 For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. MAX14569 General Description MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection ABSOLUTE MAXIMUM RATINGS (All voltages referenced to GND.) VBAT, VL...................................................................-0.3V to +6V VCC (no shutdown condition)...................... (VBAT - 0.3V) to +6V VCC (shutdown condition)........................................-0.3V to +6V CP1........................................................... -0.3V to (VBAT + 0.3V) CP2...........................................................................-0.3V to +6V ENAB, ENCD............................................................-0.3V to +6V INAVL, INCVL...........................................................-0.3V to +6V OUTBVL, OUTDVL....................................... -0.3V to (VL + 0.3V) INBVCC, INDVCC..................................... -0.3V to (VCC + 0.3V) OUTAVCC, OUTCVCC.............................. -0.3V to (VCC + 0.3V) Short-Circuit Current OUTAVCC, OUTCVCC, OUTBVL, OUTDVL to GND.................Continuous Short-Circuit Duration OUTAVCC, OUTCVCC, OUTBVL, OUTDVL to GND.....................................Continuous Continuous Power Dissipation (TA = +70NC) QSOP (derate 9.6mW/NC above +70NC)...................771.5mW Junction-to-Ambient Thermal Resistance (Note 1) BJA. ..........................................................................103.7NC/W Junction-to-Case Thermal Resistance (Note 1) BJC................................................................................37NC/W Operating Temperature Range........................... -40NC to +85NC Storage Temperature Range............................. -65NC to +150NC Junction Temperature......................................................+150NC Lead Temperature (soldering, 10s).................................+300NC Soldering Temperature (reflow).......................................+260NC Note 1: P ackage thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ELECTRICAL CHARACTERISTICS (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS POWER SUPPLIES VBAT Supply Range VL Supply Range VBAT 2.3 5.5 V VL 1.6 5.5 V 1 FA INBVCC = INDVCC = VCC, INAVL = INCVL = VL Supply Current from VL IQVL VBAT Shutdown Supply Current ISHDN-VBAT VINAVL = VINCVL = 0V, VENAB = VENCD = 0V 0.01 0.5 FA ISHDN-VL VENAB = VENCD = 0V 0.01 0.5 FA VBAT Change in Supply Current with ENAB and ENCD at VIL DIVBAT VENAB = VENCD = VIL (Notes 2, 4, 5) 1 FA OUTAVCC Shutdown Mode Leakage Current IOUTAVCC_LEAK VENAB = 0V, VENCD = VIH, VOUTAVCC = 5V 0.01 1 FA OUTCVCC Shutdown Mode Leakage Current IOUTCVCC_LEAK VENAB = VIH, VENCD = 0V, VOUTCVCC = 5V 0.01 1 FA OUTBVL, OUTDVL Shutdown Mode Leakage Current IOUTBVL_LEAK IOUTDVL_LEAK VENAB = VENCD = 0V, VOUTBVL = VOUTDVL = 0V 0.01 1 FA INBVCC Shutdown Mode Leakage Current IINBVCC_LEAK VENAB = 0V, VENCD = VIH, VINBVCC = 5V 0.01 1 FA INDVCC Shutdown Mode Leakage Current IINDVCC_LEAK VENAB = VIH, VENCD = 0V, VINDVCC = 5V 0.01 1 FA VL Shutdown Supply Current 2 Dual-Pair LLT with Charge Pump and High-ESD Protection (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS INAVL, INCVL Leakage Current IINAVL_LEAK IINCVL_LEAK VINAVL = VINCVL = VL 0.01 1 FA ENAB, ENCD Input Leakage Current IENAB_LEAK IENCD_LEAK VENAB = VENCD = 5V 0.01 1 FA OUTAVCC, OUTCVCC Short-Circuit Output Current ISH VOUTAVCC = 0V or VOUTCVCC = 0V, VBAT R 2.7V 100 250 mA LOGIC LEVELS INAVL, INCVL InputVoltage High VIHL INAVL, INCVL InputVoltage Low VILL INBVCC, INDVCC InputVoltage High VIHC INBVCC, INDVCC InputVoltage Low VILC ENAB, ENCD InputVoltage High VIH ENAB, ENCD InputVoltage Low VIL ENAB, ENCD InputVoltage Hysteresis VHYS OUTBVL, OUTDVL Output-Voltage High OUTBVL, OUTDVL Output-Voltage Low OUTAVCC, OUTCVCC Output-Voltage High VOHL VOLL VOHC 0.7 x VL V 0.3 x VL 0.7 x VCC V 0.3 x VCC 1.2 120 VL - 0.1 OUTBVL or OUTDVL source current = 4mA, INBVCC or INDVCC > VIHC VL - 0.4 V V 0.4 OUTBVL or OUTDVL source current = 100FA, INBVCC or INDVCC > VIHC V V mV V OUTBVL or OUTDVL sink current = 100FA, INBVCC or INDVCC < VILC 0.1 OUTBVL or OUTDVL sink current = 4mA, INBVCC or INDVCC < VILC 0.4 V OUTAVCC or OUTCVCC source current = 100FA, INAVL or INCVL > VIHL, 2.7V P VBAT P 4.5V 4.6 OUTAVCC or OUTCVCC source current = 20mA, INAVL or INCVL > VIHL, 2.7V P VBAT P 4.5V 4.3 V 3 MAX14569 ELECTRICAL CHARACTERISTICS (continued) MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection ELECTRICAL CHARACTERISTICS (continued) (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER OUTAVCC, OUTCVCC Output-Voltage Low SYMBOL VOLC CONDITIONS MIN TYP MAX OUTAVCC or OUTCVCC sink current = 100FA, INAVL or INCVL < VILL, 2.7V P VBAT P 4.5V 0.1 OUTAVCC or OUTCVCC sink current = 20mA, INAVL or INCVL < VILL, 2.7V P VBAT P 4.5V 0.4 UNITS V TIMING CHARACTERISTICS (Note 6) OUTAVCC, OUTCVCC Rise Time tRVCC Figure 1 25 ns OUTAVCC, OUTCVCC Fall Time tFVCC Figure 1 25 ns OUTBVL, OUTDVL Rise Time tRVL Figure 2 25 ns OUTBVL, OUTDVL Fall Time tFVL Figure 2 25 ns Propagation Delay (Driving INAVL, INCVL) Low-to-High tPVL-VCC-LH Figure 1 30 ns Propagation Delay (Driving INAVL, INCVL) High-to-Low tPVL-VCC-HL Figure 1 30 ns Propagation Delay (Driving INBVCC, INDVCC) Low-to-High tPVCC-VL-LH Figure 2 30 ns Propagation Delay (Driving INBVCC, INDVCC) High-to-Low tPVCC-VL-HL Figure 2 30 ns Maximum Data Rate 12 Mbps CHARGE PUMP VCC Output Voltage VCC ICC = 10mA, 2.7V P VBAT P 4.5V 4.7 5.0 5.3 ICC = 40mA, 3.0V P VBAT P 4.5V 4.7 5.0 5.3 VCC Output Voltage Ripple ICC = 40mA VCC Line Regulation ICC = 10mA, 2.7V P VBAT P 4.5V VCC Load Regulation Quiescent Current CP_ Leakage Current 4 DVCC IQ ICP_LEAK 0 P ICC P 40mA, VBAT = 3.6V ICC = 0mA, VBAT = 3.6V VBAT = 3.6V, VCC = 0V VENAB = VENCD = 0V 45 -1 mVP-P +1 -1 0.01 V % % 200 FA 0.5 FA Dual-Pair LLT with Charge Pump and High-ESD Protection (VBAT = 2.3V to 5.5V, VL = 1.6V to 5.5V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC.) (Notes 2, 3, 4) PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS CP_ Switching Frequency fCP No capacitor between CP1 and CP2, 2.7V P VBAT P 4.5V 0.5 1 1.5 MHz Efficiency E ICC = 10mA, VBAT = 2.7V, VCC = 5.0V 90 % THERMAL PROTECTION Thermal Shutdown TSHDN +150 NC Thermal Hysteresis THYST +20 NC ESD PROTECTION OUTAVCC, INBVCC, OUTCVCC, INDVCC All Other Pins Human Body Model ±25 IEC 61000-4-2 Air Gap Discharge ±15 IEC 61000-4-2 Contact Discharge ±12 Human Body Model ±2 kV kV Note 2: VL must be less than or equal to VCC during normal operation. However, VL can be greater than VCC during startup and shutdown conditions. Note 3: All units are 100% production tested at TA = +25NC. Limits over the operating temperature range are guaranteed by design and not production tested. Note 4: Connect a 0.47µF capacitor between CP1 and CP2. Note 5: D IVBAT = [IVBAT(VENAB = VENCD = VIL) - IVBAT(VENAB = VENCD= 0V)]. Guaranteed by design and not production tested. Note 6: VCC = 5.0V, VL = 1.6V to VCC, VBAT = 2.7V to 3.6V, VENAB = VENCD > VIH, RS = 50I, RL = 1MI, CL = 15pF, TA = -40NC to +85NC, unless otherwise noted. Typical values are at VBAT = 3.6V, VL = 3.0V, and TA = +25NC. 5 MAX14569 ELECTRICAL CHARACTERISTICS (continued) MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection tRVCC VL tFVCC VBAT 90% 90% INAVL/ INCVL MAX14569 50I INAVL/ INCVL VL VCC 50% OUTAVCC/ OUTCVCC 50% 50% CL RL 50% OUTAVCC/ 10% OUTCVCC 10% tPVL-VCC-LH tPVL-VCC-HL Figure 1. Push-Pull Driving INAVL/INCVL Test Circuit and Timing tRVL VL tFVL VBAT OUTBVL/ OUTDVL MAX14569 50I INBVCC/ INDVCC VCC VL OUTBVL/ OUTDVL 90% 50% 50% CL 90% 50% RL INBVCC/ INDVCC 10% tPVCC-VL-LH Figure 2. Push-Pull Driving INBVCC/INDVCC Test Circuit and Timing 6 50% 10% tPVCC-VL-HL Dual-Pair LLT with Charge Pump and High-ESD Protection 3.0 2.5 2.0 1.5 1.0 0.5 0 3.1 2.3 4.7 3 VBAT = 3.6V 2 VBAT = 2.7V 1 0.20 0.15 0.10 0.05 10 35 60 2.1 1.6 85 2.6 3.1 3.6 CP_ OPERATING FREQUENCY vs. VBAT VCC SHORT-CIRCUIT CURRENT vs. VBAT VL = 1.8V 0.2 0.1 -15 10 35 60 TA = -40°C 950 TA = 25°C 940 ISH (mA) 700 960 TA = 85°C 930 200 100 0 3.2 4.1 5.0 CP_ LOAD REGULATION (VCC vs. ICC) MAX14569 toc07 5.2 4.96 ENAB = ENCD = HIGH 4.9 4.8 4.7 4.94 4.6 4.92 4.90 4.5 3.0 3.3 3.6 VBAT (V) 3.9 4.2 4.5 0 5 10 15 20 ICC (mA) 4.1 5.0 OUTPUT RIPPLE vs. LOAD CURRENT 5.1 VCC (V) 4.98 3.2 2.3 VBAT (V) 5.0 5.00 TA = 85°C 400 300 CP_ LINE REGULATION (VCC vs. VBAT) 5.02 TA = 25°C 500 910 2.3 5.04 TA = -40°C 600 920 VBAT (V) ENAB = ENCD = HIGH ICC = 10mA 800 900 85 OUTAVCC/OUTCVCC SHORT-TO-GROUND 900 970 MAX14569 toc06 MAX14569 toc05 980 TEMPERATURE (°C) 5.10 1000 25 30 35 40 200 MAX14569 toc09 0.3 990 VCC OUTPUT VOLTAGE RIPPLE (mVP-P) VL = 2.7V 1000 CP_ OPERATING FREQUENCY (kHz) VL = 3.3V 2.7 0.25 0 -15 -40 0 VCC (V) VBAT = 4.5V 0.30 VL SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE 0.4 5.06 4 0.35 VL VOLTAGE (V) 0.5 5.08 5 0.40 TEMPERATURE (°C) 0.6 -40 6 VENAB = VENCD = 0V 0.45 VBAT VOLTAGE (V) VENAB = VENCD = 0V 0.7 7 0 5.5 MAX14569 toc04 VL SHUTDOWN SUPPLY CURRENT (nA) 0.8 3.9 8 0.50 VL SHUTDOWN SUPPLY CURRENT (nA) 3.5 VENAB = VENCD = 0V VINAVL = VINCVL = 0V 9 MAX14569 toc08 4.0 10 MAX14569 toc02 VENAB = VENCD = 0V VINAVL = VINCVL = 0V 4.5 VBAT SHUTDOWN SUPPLY CURRENT (nA) MAX14569 toc01 VBAT SHUTDOWN SUPPLY CURRENT (nA) 5.0 VL SHUTDOWN SUPPLY CURRENT vs. VL VOLTAGE VBAT SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE MAX14569 toc03 VBAT SHUTDOWN SUPPLY CURRENT vs. VBAT VOLTAGE ENAB = ENCD = HIGH VBAT = 3.6V 180 160 140 120 100 80 60 40 20 0 0 5 10 15 20 25 30 35 40 ICC (mA) 7 MAX14569 Typical Operating Characteristics (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) Typical Operating Characteristics (continued) (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) OUTBVL/OUTDVL FALL TIME vs. LOAD CAPACITANCE OUTBVL/OUTDVL RISE TIME vs. LOAD CAPACITANCE 7 6 5 4 3 2 9 1 7 6 5 4 3 2 0 0 20 40 60 80 100 0 20 40 60 OUTBVL/OUTDVL PROPAGATION DELAY vs. LOAD CAPACITANCE OUTAVCC/OUTCVCC FALL TIME vs. LOAD CAPACITANCE tPVCC-VL-LH 6 5 4 3 2 MAX14569 toc13 tPVCC-VL-HL 7 100 OUTAVCC/OUTCVCC FALL TIME (ns) 8 MAX14569 toc12 LOAD CAPACITANCE (pF) 9 100 80 LOAD CAPACITANCE (pF) 10 OUTBVL/OUTDVL PROPAGATION DELAY (ns) 8 1 0 90 80 70 60 50 40 30 20 10 1 0 0 20 40 60 80 200 400 600 800 1000 LOAD CAPACITANCE (pF) LOAD CAPACITANCE (pF) OUTAVCC/OUTCVCC RISE TIME vs. LOAD CAPACITANCE OUTAVCC/OUTCVCC PROPAGATION DELAY vs. LOAD CAPACITANCE MAX14569 toc14 100 90 80 70 60 50 40 30 20 10 0 0 0 100 200 400 600 LOAD CAPACITANCE (pF) 800 1000 OUTAVCC/OUTCVCC PROPAGATION DELAY (ns) 0 8 MAX14569 toc11 8 10 100 MAX14569 toc15 OUTBVL/OUTDVL FALL TIME (ns) 9 OUTBVL/OUTDVL RISE TIME (ns) MAX14569 toc10 10 OUTAVCC/OUTCVCC RISE TIME (ns) MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection 90 80 70 60 50 40 tPVL-VCC-LH 30 tPVL-VCC-HL 20 10 0 0 200 400 600 LOAD CAPACITANCE (pF) 800 1000 Dual-Pair LLT with Charge Pump and High-ESD Protection DRIVING INAVL/INCVL DRIVING INAVL/INCVL MAX14569 toc16 MAX14569 toc17 COUTAVCC/COUTCVCC = 15pF COUTAVCC/COUTCVCC = 150pF IN_VL 2V/div IN_VL 2V/div OUT_VCC 2V/div OUT_VCC 2V/div 400ns/div 400ns/div DRIVING INAVL/INCVL DRIVING INBVCC/INDVCC MAX14569 toc18 MAX14569 toc19 COUTAVCC/COUTCVCC = 1000pF IN_VL 2V/div IN_VCC 2V/div OUT_VCC 2V/div OUT_VL 2V/div COUTBVL/COUTDVL = 15pF 400ns/div 400ns/div 9 MAX14569 Typical Operating Characteristics (continued) (VBAT = 3.6V, VL = 3V, CVBAT = 1FF, CVCC = 2.2FF, CVL = 0.1FF, connect 0.47FF capacitor between CP1 and CP2, data rate = 1Mbps, TA = +25NC, unless otherwise noted.) MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection Pin Configuration TOP VIEW VL 1 + 16 CP1 15 VBAT ENAB 2 ENCD 3 MAX14569 14 CP2 13 VCC INAVL 4 OUTBVL 5 12 OUTAVCC INCVL 6 11 INBVCC OUTDVL 7 10 OUTCVCC GND 8 9 INDVCC QSOP Pin Description PIN 10 NAME FUNCTION Logic Supply Voltage, +1.6V to +5.5V. Bypass VL to GND with a 0.1FF capacitor placed as close as possible to the device. 1 VL 2 ENAB Enable Input for A and B Ports. Drive ENAB low for shutdown mode, or drive ENAB high for normal operation. 3 ENCD Enable Input for C and D Ports. Drive ENCD low for shutdown mode, or drive ENCD high for normal operation. 4 INAVL 5 OUTBVL 6 INCVL 7 OUTDVL 8 GND Input A Port. Referenced to VL. Output B Port. Referenced to VL. Input C Port. Referenced to VL. Output D Port. Referenced to VL. Ground 9 INDVCC 10 OUTCVCC Input D Port. Referenced to VCC. 11 INBVCC 12 OUTAVCC 13 VCC Charge-Pump Output. Bypass VCC to GND with a 2.2FF ceramic capacitor placed as close as possible to the VCC pin to have high ESD protection on OUTAVCC, INBVCC, OUTCVCC, and INDVCC pins. 14 CP2 External Charge-Pump Capacitor Connection 15 VBAT Battery Input, +2.3V to +5.5V. Bypass VBAT to GND with a 1FF capacitor placed as close as possible to the device. 16 CP1 External Charge-Pump Capacitor Connection Output C Port. Referenced to VCC. Input B Port. Referenced to VCC. Output A Port. Referenced to VCC. Dual-Pair LLT with Charge Pump and High-ESD Protection The MAX14569 is a dedicated dual-pair unidirectional logic-level translator that is ideal for automatic remotemetering applications. Externally applied voltage VL and regulated output voltage VCC set the logic levels on either side of the device. The device boosts the VBAT supply input voltage to a charge-pump-regulated output, VCC. Logic-high signals present on the VL side of the device appear as a highvoltage logic signals on the VCC side of the device and vice versa. The device has two pairs of logic-level translators in back-to-back configuration: one logic-level translator from a low voltage to a high voltage and the other logiclevel translator from a high voltage to a low voltage. Level Translation For proper operation, ensure that 2.3V P VBAT P 5.5V, 1.6V P VL P 5.5V. The device enters low-power shutdown mode when ENAB = ENCD = GND (see the Functional Table). In shutdown mode, the INAVL, INBVCC, INCVL, INDVCC, OUTAVCC and OUTCVCC are in high-impedance mode and the OUTBVL and OUTDVL are pulled down to GND. The maximum data rate depends heavily on the load capacitance (see the rise/fall times in the Typical Operating Characteristics), output impedance of the driver, and the operating voltage range. Output Load Requirements The device features an extreme power-saving mode that reduces supply current to a typical 0.01FA. The device also features thermal short-circuit protection on the VCC side for enhanced protection in applications that route signals externally. The device is designed to drive a wide variety of load types including a high capacitive load. To protect the VCC outputs (OUTAVCC, OUTCVCC) from a harsh external environment, the VCC outputs are ruggedized with a high ESD-capable output structure. When the high capacitive load is connected to the VCC output side, the current is limited by the charge-pump circuit along with the output driver impedance. The device is also protected by the thermal protection. Functional Diagram Functional Table INPUTS VL VBAT CHARGE PUMP MAX14569 ENAB VL VCC ENCD Low Low Device is in shutdown OUTAVCC, OUTCVCC: high impedance OUTBVL, OUTDVL: pulldown to GND High OUTAVCC: high impedance OUTBVL: pulldown to GND INCVL to OUTCVCC INDVCC to OUTDVL Low INAVL to OUTAVCC INBVCC to OUTBVL OUTCVCC: high impedance OUTDVL: pulldown to GND High INAVL to OUTAVCC INBVCC to OUTBVL INCVL to OUTCVCC INDVCC to OUTDVL VCC INAVL OUTAVCC VL Low VCC OUTBVL INBVCC High ENCD VL VCC OUTCVCC INCVL VL High VCC OUTDVL INDVCC DRIVERS OUTPUT EVENTS ENAB GND 11 MAX14569 Detailed Description MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection Shutdown Mode The device features two enable inputs (ENAB, ENCD) that place the device into a low-power shutdown mode when both are driven low. If either ENAB or ENCD is pulled high, the internal charge pump starts working and generates 5V on VCC. When both ENAB and ENCD are driven low, the MAX14569 enters shutdown mode and draws a minimum current from VL and VBAT. To minimize supply current in shutdown mode, connect INAVL and INCVL to ground. Charge Pump The internal charge pump provides 5V on VCC when VBAT is between 2.7V and 4.5V. When VBAT is between 2.3V and 2.7V, VCC is twice the voltage of VBAT. The output is regulated to 5V as long as the battery voltage supports it. Thermal Protection The device features thermal shutdown function necessary to protect the device. When the junction temperature exceeds +150NC (typ), the charge pump turns off and OUTAVCC, OUTBVL, OUTCVCC, OUTDVL are low. This limits the device temperature from rising further. When the temperature drops 20NC (typ) below +150NC (typ), the device resumes normal operation. Applications Information Layout Recommendations Use standard high-speed layout practices when laying out a board with the device. For example, to minimize line coupling, place all other signal lines not connected to the device at least 1x the substrate height of the PCB away from the input and output lines of the device. Power-Supply Decoupling To reduce ripple and the chance of introducing data errors, bypass VL to ground with a 0.1FF ceramic capacitor, VBAT to ground with a 1FF ceramic capacitor, and VCC to ground with a 2.2FF ceramic capacitor. Place all capacitors as close as possible to the power-supply inputs. ±25kV ESD Protection As with all Maxim devices, ESD protection structures are incorporated on all pins to protect against electrostatic 12 discharges encountered during handling and assembly. The OUTAVCC, INBVCC, OUTCVCC, INDVCC pins have extra protection against static electricity. Maxim’s engineers have developed state-of-the-art structures to protect these pins against ESD of Q25kV without damage. The ESD structures withstand high ESD in all states: normal operation, shutdown, and powered down. After an ESD event, the device keeps working without latchup or damage. ESD protection can be tested in various ways. The OUTAVCC, INBVCC, OUTCVCC, and INDVCC pins are characterized for protection to the following limits: U Q25kV using the Human Body Model U Q15kV using the Air-Gap Discharge Method specified in IEC 61000-4-2 U Q12kV using the Contact Discharge Method specified in IEC 61000-4-2 ESD Test Conditions ESD performance depends on a variety of conditions. Contact Maxim for a reliability report that documents test setup, test methodology, and test results. Human Body Model Figure 3 shows the Human Body Model, and Figure 4 shows the current waveform it generates when discharged into a low-impedance state. This model consists of a 100pF capacitor charged to the ESD voltage of interest, which is then discharged into the test device through a 1.5kI resistor. IEC 61000-4-2 The IEC 61000-4-2 standard covers ESD testing and performance of finished equipment. It does not specifically refer to integrated circuits. The major difference between tests done using the Human Body Model and IEC 61000-4-2 is higher peak current in IEC 61000-4-2, because series resistance is lower in the IEC 61000-4-2 model. Hence, the ESD withstand voltage measured to IEC 61000-4-2 is generally lower than that measured using the Human Body Model. Figure 5 shows the IEC 61000-4-2 model, and Figure 6 shows the current waveform for the Q8kV, IEC 61000-4-2, level 4, ESD Contact Discharge Method. Dual-Pair LLT with Charge Pump and High-ESD Protection CHARGE-CURRENT LIMIT RESISTOR HIGHVOLTAGE DC SOURCE Cs 100pF RD 330Ω RC 50MΩ to 100MΩ RD 1500Ω DISCHARGE RESISTANCE DISCHARGE RESISTANCE CHARGE CURRENT LIMIT RESISTOR DEVICE UNDER TEST STORAGE CAPACITOR Figure 3. Human Body ESD Test Model HIGHVOLTAGE DC SOURCE MAX14569 RC 1MΩ Cs 150pF STORAGE CAPACITOR DEVICE UNDER TEST Figure 5. IEC 61000-4-2 ESD Test Model I 100% 90% IP 100% 90% I PEAK Ir PEAK-TO-PEAK RINGING (NOT DRAWN TO SCALE) AMPERES 36.8% 10% 0 0 tRL TIME tDL CURRENT WAVEFORM 10% t r = 0.7ns to 1ns t 30ns 60ns Figure 4. Human Body Current Waveform Figure 6. IEC 61000-4-2 ESD Generator Current Waveform Chip Information PROCESS: BiCMOS Package Information For the latest package outline information and land patterns, go to www.maxim-ic.com/packages. Note that a “+”, “#”, or “-“ in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains to the package regardless of RoHS status. PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO. 16 QSOP E16+4 21-0055 90-0167 13 MAX14569 Dual-Pair LLT with Charge Pump and High-ESD Protection Revision History REVISION NUMBER REVISION DATE 0 9/10 DESCRIPTION Initial release PAGES CHANGED — Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 14 © 2010 Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 Maxim Integrated Products Maxim is a registered trademark of Maxim Integrated Products, Inc.