KIT ATION EVALU LE B A IL A AV 19-0848; Rev 0; 10/07 Complete Single-Conversion Television Tuner The MAX3540 complete single-conversion television tuner is designed for use in analog/digital terrestrial applications and digital set-top boxes. This television tuner draws only 760mW of power from a +3.3V supply voltage. The MAX3540 is designed to convert NTSC or ATSC signals in the 54MHz to 860MHz band to a 44MHz intermediate frequency (IF). The MAX3540 includes a variable-gain low-noise amplifier (LNA), multiband tracking filters, a harmonic-rejection mixer, a low-noise IF amplifier, an IF power detector, and a variable-gain IF amplifier. The MAX3540 also includes fully monolithic VCOs and tank circuits as well as a complete frequency synthesizer. This highly integrated design allows for low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. Features ♦ Low Power Consumption: 760mW (typ) from a +3.3V Supply Voltage ♦ Integrated Tracking Filters ♦ ATSC A/74 Compliant ♦ 40dB Adjacent Channel Protection Ratio (ACPR) ♦ 4.4dB (typ) Low Noise Figure ♦ Small, 7mm x 7mm, fcLGA Leadless Package ♦ 256-QAM-Compatible Phase-Noise Performance ♦ IF Overload Detector Controls RF Variable-Gain Amplifier ♦ 2-Wire I2C-Compatible Serial Control Interface The MAX3540 is specified for operation in the 0°C to +85°C temperature range and is available in a leadless 48-pin flip-chip (fcLGA) package. Ordering Information TEMP RANGE PART Applications Televisions MAX3540ULM#G42 Analog/Digital Terrestrial Receivers *EP = Exposed paddle. PINPACKAGE PKG CODE 0°C to +85°C 48 fcLGA-EP* L4877A-E Digital Set-Top Boxes Cable Modems Pin Configuration ADDR2 ADDR1 XTALP XTALN VCC CP MUX VCC VTUNE GND_TUNE LDO VCC VOIP Gateways 48 47 46 45 44 43 42 41 40 39 38 37 + SCL 1 SDA 2 VCC 3 UHF_IN 4 ÷R SERIAL INTERFACE PD CP ÷N VCO DIVIDER 36 IFOUT1- 35 IFOUT1+ 34 IFOVLD 33 VCC VHF_IN 5 32 VCC RFGND2 6 31 GND LEXT 7 30 IFIN+ 29 IFIN- RFGND3 8 RFAGC 9 VREF + - 28 VCC 27 GND GND 11 26 IFAGC GND 12 25 IFOUT2+ MAX3540 VCC 10 13 14 15 16 17 18 19 20 21 22 23 24 GND GND GND GND GND GND GND GND GND GND VCC IFOUT2- EP ________________________________________________________________ Maxim Integrated Products For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com. 1 MAX3540 General Description MAX3540 Complete Single-Conversion Television Tuner ABSOLUTE MAXIMUM RATINGS VCC to GND ..............................................................-0.3V, +3.6V RFIN, IFIN_, IFOUT1_, IFOUT2_, IFAGC, RFAGC, VTUNE, LDO, MUX, CP, XTAL to GND ..-0.3V to (VCC + 0.3V) SDA, SCL, ADDR2, ADDR1 to GND......................-0.3V to +3.6V IFOUT__ Short-Circuit Duration .....................................Indefinite RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70°C) 48-Pin fcLGA (derate 25mW/°C above +70°C) ...............1.4W Operating Temperature Range...............................0°C to +85°C Junction Temperature ......................................................+150°C Storage Temperature Range .............................-65°C to +165°C Lead Temperature (soldering, 10s) .................................+240°C Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. CAUTION! ESD SENSITIVE DEVICE DC ELECTRICAL CHARACTERISTICS (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS +3.5 V SUPPLY VOLTAGE AND CURRENT Supply Voltage Supply Current +3.1 Receive mode 240 Shutdown mode 275 5 RF and IF AGC Input Bias Current At +0.5V and +3V -50 RF and IF AGC Control Voltage (Note 1) Minimum attenuation +3 +50 Maximum attenuation +0.5 0.3 x VCC Digital Input Logic-Level Low 0.7 x VCC Digital Input Logic-Level High mA μA V V V SERIAL INTERFACE 0.3 x VCC Input Logic-Level Low 0.7 x VCC Input Logic-Level High SDA, SCL Input Current Output Logic-Level Low Output Logic-Level High 2 V 0.05 x VCC Input Hysteresis V -10 3mA sink current VCC 0.5 _______________________________________________________________________________________ V +10 μA 0.4 V V Complete Single-Conversion Television Tuner (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75Ω system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS RF INPUT TO IFOUT1_ OUTPUT Operating Frequency Range (See Table 7) VHF_IN, LPF enabled, INPT = 00 54 100 VHF_IN, LPF disabled, INPT = 01 100 300 UHF_IN, INPT = 10 300 Analog channel PIX carrier Output Frequency Voltage Gain Source impedance = 75Ω, load impedance = 200Ω Operating Frequency Range Gain specification met across these frequency bands 860 45.75 Digital channel center frequency Maximum gain, VRFAGC = 3V, 54MHz to 860MHz Maximum gain, VRFAGC = 3V, broadcast channels Minimum gain, VRFAGC = 0.5V MHz 44 34 28.0 34 45.5 dB -11 VHF_IN 54 300 UHF_IN 300 860 MHz Input Return Loss Worst case, selected channel Noise Figure Input IP2 (In-Band and Out-of-Band Tones) Input IP3 (In-Band and Out-of-Band Tones) Maximum gain, VRFVGC = 3V 8 dB Maximum gain, VRFVGC = 3V (Note 1) 4.4 dB Maximum gain, VRFVGC = 3V 15 At 12.5dB of gain 29 At 12.5dB of gain dBm -13 5 Maximum gain, VRFVGC = 3V dBm 11 -24.5 Input P1dB At 12.5dB of gain, CW tone at fC - 36MHz, tested at Ch 69 in UHF band -3 Beats Within Output 0dBmV PIX carrier level (Note 1) -60 VHF_IN from 150MHz to 960MHz -60 VHF_IN from 960MHz to 1400MHz -40 UHF_IN from 600MHz to 1400MHz -40 Beats, Converted to Output MHz dBm dBc dBc Gain Flatness 54MHz to 60MHz Isolation 5MHz to 50MHz, RF input to IF output, relative to desired channel 60 dBc Port-to-Port Isolation Isolation between RF input ports at 215MHz 30 dB Image Rejection Measured at 91.5MHz above desired channel’s center frequency Spurious Leakage at RF Input Phase Noise (Single-Sideband) Output Return Loss 1.5 54MHz to 860MHz Broadcast channels, TA = +25°C 70 dBc 66 5MHz to 65MHz -40 65MHz to 878MHz -40 10kHz offset -85 100kHz offset, 1.5kHz loop bandwidth -105 1MHz offset, 1.5kHz loop bandwidth -125 Balanced 50Ω load dBP-P 9 dBmV dBc/Hz dB _______________________________________________________________________________________ 3 MAX3540 AC ELECTRICAL CHARACTERISTICS MAX3540 Complete Single-Conversion Television Tuner AC ELECTRICAL CHARACTERISTICS (continued) (MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75Ω system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25°C, unless otherwise noted.) PARAMETER CONDITIONS MIN TYP MAX UNITS IF VARIABLE-GAIN AMPLIFIER Input Impedance Balanced Output Impedance Balanced (Note 1) Passband Voltage Gain Source load = 300Ω, output load = 300Ω Ω 2000 300 Maximum gain setting, VIFAGC = 3V 54 56 Ω 65 dB Minimum gain setting, VIFAGC = 0.5V 21 Passband Gain Flatness 40MHz to 48MHz (Note 1) 1.2 dB Output Voltage VIFAGC = 3V (Note 1) 2 VP-P AGC Gain Slope VIFAGC = 3V to 0.5V (Note 1) 30 dB/V Equivalent Input Voltage Noise Density At 44MHz, maximum gain, VIFAGC = 3V (Note 1) 7.3 nV/√Hz Noise Figure Change vs. Attenuation IM3 < 0.35 VOUT = 1.5VP-P, 40dB < gain < 60dB (Note 1) dB/dB -54 dBc IF OVERLOAD DETECTOR (see the IF Overload Detector section) Output Overload Attack Point Attack-Point Accuracy Detector Output Voltage Range Negative polarity, overload reduces VDET (open collector, 0.3mA sink) 0.7 VP-P ±1 dB 0.5 Detector Gain 3.0 V 70 V/V 4 MHz FREQUENCY SYNTHESIZER REFERENCE OSCILLATOR Frequency DIVIDERS RF N-Divider Ratio 256 32,767 RF R-Divider Ratio 8 127 31.50 250.00 LO PHASE DETECTOR AND CHARGE PUMP Comparison Frequency CP = 00 Charge-Pump Current kHz 0.5 CP = 01 1 CP = 10 1.5 CP = 11 mA 2 Charge-Pump Three-State Current Charge-Pump Current Matching ±5 nA 5 % LOCAL OSCILLATOR (OSCILLATOR WITH NARROW BAND LOOP) VCO Tuning Range Tank frequency VCO Tuning Gain Tank oscillator gain 2160 4400 MHz 500 MHz/V 400 kHz 2-WIRE SERIAL INTERFACE Clock Frequency Note 1: Guaranteed by design and characterization. 4 _______________________________________________________________________________________ Complete Single-Conversion Television Tuner PIN NAME 1 SCL 2-Wire Serial-Clock Interface. Requires a pullup resistor to VCC. FUNCTION 2 SDA 2-Wire Serial-Data Interface. Requires a pullup resistor to VCC. 3, 10, 23, 28, 32, 33, 37, 41, 44 VCC Power-Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor. 4 UHF_IN UHF RF Input. Matched to 75Ω over the operating band. Requires a DC-blocking capacitor. 5 VHF_IN VHF RF Input. Matched to 75Ω over the operating band. Requires a DC-blocking capacitor. 6 RFGND2 7 LEXT 8 RFGND3 RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. 9 RFAGC RF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). 11–22, 27, 31 GND 24 IFOUT2- Inverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. 25 IFOUT2+ Noninverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. 26 IFAGC RF Ground. Bypass to the PCB’s ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC. Ground. Connect to the PCB’s ground plane. IF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). 29 IFIN- Inverting IF-VGA Input. Connect to the output of an IF-SAW filter. 30 IFIN+ Noninverting IF-VGA Input. Connect to the output of an IF-SAW filter. 34 IFOVLD 35 IFOUT1+ Noninverting IF-LNA Output. Requires a DC-blocking capacitor. 36 IFOUT1- Inverting IF-LNA Output. Requires a DC-blocking capacitor. 38 LDO 39 GND_TUNE 40 VTUNE 42 MUX 43 CP 45 XTALN 46 XTALP Crystal Input. Requires a DC-blocking capacitor. 47 ADDR1 2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the I2C-compatible serial interface. 48 ADDR2 2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the I2C-compatible serial interface. EP EP IF Power Detector Open-Collector Output. Requires a 10kΩ pullup resistor to VCC. VCO LDO Bypass. Bypass to ground with a 0.47μF capacitor. VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GND must be connected to this pin (see the Typical Application Circuit). VCO Tuning Input. Connect to the PLL loop filter output. Test Output. Leave this pin unconnected during normal operation. Charge-Pump Output. Connect to the PLL loop filter input. Crystal Oscillator Feedback. See the Typical Application Circuit. Exposed Paddle. Solder evenly to the PCB ground plane for proper operation. _______________________________________________________________________________________ 5 MAX3540 Pin Description MAX3540 Complete Single-Conversion Television Tuner Detailed Description filter control registers. These 11 programmable registers are also readable. The read-only registers include a status register and a ROM table data register. Recommended default bit settings are provided for user convenience only and are not guaranteed. The user must write all registers after power-up and no earlier than 100μs after power-up. Register Descriptions The MAX3540 includes 11 programmable registers and two read-only registers. The 11 programmable registers include two N-divider registers, an R-divider register, a VCO register, an RSSI/charge-pump/filter-select register, a control register, a shutdown register, and tracking- Table 1. Register Configuration MSB LSB REGISTER READ/ REGISTER NAME WRITE ADDRESS N-DIV High Both DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 0x00 0 N14 N13 N12 N11 N10 N9 N8 N-DIV Low Both 0x01 N7 N6 N5 N4 N3 N2 N1 N0 R-DIV Both 0x02 0 R6 R5 R4 R3 R2 R1 R0 VCO Both 0x03 VCO4 VCO3 VCO2 VCO1 VCO0 LD IFOVLD, Charge Pump, and Filter Select Both 0x04 0 IFOVLD2 IFOVLD1 IFOVLD0 CP1 CP0 0 0 0 0 SHDN_RF Control Both 0x05 Shutdown Both 0x06 Tracking Filter Series Cap Both 0x07 TFS7 TFS6 TFS5 TFS4 Tracking Filter Parallel Cap Both 0x08 FLD 0 TFP5 Tracking Filter ROM Address Both 0x09 0 0 Reserved Both 0x0A X ROM Table Data Readback Read 0x0B Status Read 0x0C VDIV1 VDIV0 TF1 TF0 SHDN_IFAGC INPT1 INPT0 SH DN _MIX1 SH DN _MIX0 SH DN _I F SH DN _P D SH DN _S YN 0 0 0 TFS3 TFS2 TFS1 TFS0 TFP4 TFP3 TFP2 TFP1 TFP0 0 0 TFA3 TFA2 TFA1 TFA0 X X X X X X X TFR7 TFR6 TFR5 TFR4 TFR3 TFR2 TFR1 TFR0 POR LD2 LD1 LD0 X X X X Table 2. N-DIV High Register (Address: 0000b) 6 BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT RESERVED 7 0 N[14:8] 6–0 001 0010 FUNCTION Must be set to 0. Sets the most significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767. _______________________________________________________________________________________ Complete Single-Conversion Television Tuner MAX3540 Table 3. N-DIV Low Register (Address: 0001b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT N[7:0] 7–0 0101 0000 FUNCTION Sets the least significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767. Table 4. R-DIV Register (Address: 0010b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT RESERVED 7 0 R[6:0] 6–0 100 0000 FUNCTION Must be set to 0. Sets the PLL reference divider (R). Default reference divider value is R = 64. R can range from 16 to 127. Table 5. VCO Register (Address: 0011b) BIT NAME VCO[4:3] BIT LOCATION (0 = LSB) 7, 6 RECOMMENDED DEFAULT FUNCTION 01 VCO select. Selects one of three possible VCOs. 00 = VCOs shut down 01 = selects VCO1 10 = selects VCO2 11 = selects VCO3 VCO sub-band select. Selects one of eight possible VCO sub-bands. 000 = selects SB0 001 = selects SB1 010 = selects SB2 011 = selects SB3 100 = selects SB4 101 = selects SB5 110 = selects SB6 111 = selects SB7 VCO[2:0] 5, 4, 3 101 LD 2 1 Lock-detect enable. 0 = disabled 1 = enabled 01 VCO divider ratio select. 00 = sets VCO divider to 4 01 = sets VCO divider to 8 10 = sets VCO divider to 16 11 = sets VCO divider to 32 VDIV[1:0] 1, 0 _______________________________________________________________________________________ 7 MAX3540 Complete Single-Conversion Television Tuner Table 6. RSSI, Charge Pump, and Filter Select Register (Address: 0100b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION RESERVED 7 0 IFOVLD[2:0] 6, 5, 4 000 Write content of ROM register OD[2:0] to this location. 00 Selects the typical charge-pump current. 00 = 0.5mA 01 = 1mA 10 = 1.5mA 11 = 2mA 00 Selects the tracking filter band of operation. 00 = VHF low 01 = VHF high 10 = UHF 11 = factory use only CP[1:0] TF[1:0] 3, 2 1, 0 Must be set to 0. Table 7. Control Register (Address: 0101b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT RESERVED 7–4 0000 SHDN_RF 3 0 RF shutdown. 0 = RF circuitry enabled 1 = RF circuitry disabled SHDN_IFV GA 2 1 IF VGA shutdown. 0 = IF VGA enabled 1 = IF VGA disabled 00 Selects the RF input. 00 = selects VHF_IN with LPF 01 = selects VHF_IN, no LPF 10 = selects UHF_IN 11 = factory use only INPT[1:0] 8 1, 0 FUNCTION Must be set to 0000. _______________________________________________________________________________________ Complete Single-Conversion Television Tuner MAX3540 Table 8. Shutdown Register (Address: 0110b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION SHDN_MIX 7, 6 0 Mixer shutdown. 00 = mixer enabled 01, 10 = factory use only 11 = mixer disabled SHDN_IF 5 0 IF shutdown. 0 = IF section enabled 1 = IF section disabled SHDN_PD 4 0 IF OVLD shutdown. 0 = power detector enabled 1 = power detector disabled SHDN_SYN 3 0 Frequency synthesizer shutdown. 0 = synthesizer enabled 1 = synthesizer disabled RESERVED 2, 1, 0 000 Must be set to 000. Table 9. Tracking-Filter Series Cap Register (Address: 0111b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT TFS[7:0] 7–0 00000000* FUNCTION Programs series capacitor values in the tracking filter. Table 10. Tracking-Filter Parallel Cap Register (Address: 1000b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FLD 7 0 Filter load bit. A 0 to 1 transition of this bit forces the loading of the ROM table data readback register. Must be set to 0. Reserved 6 0 TFP[5:0] 5–0 000000* FUNCTION Programs parallel capacitor values in the tracking filter. Table 11. Tracking-Filter ROM Address Register (Address: 1001b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT Reserved 7–4 0000 Must be set to 0000. TFA[3:0] 3–0 0000* Address bits of the ROM register to be read. FUNCTION *See the RF Tracking Filter section. Table 12. Reserved Register (Address: 1010b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT Reserved 7–0 N/A FUNCTION Reserved. Do not program these bits during normal operation. _______________________________________________________________________________________ 9 MAX3540 Complete Single-Conversion Television Tuner Table 13. ROM Table Data Readback Register (Address: 1011b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT TFR[7:0] 7–0 00000000* FUNCTION Tracking-filter data bits read from the device’s ROM table. *See the RF Tracking Filter section. Table 14. Status Register (Address: 1100b) BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT POR 7 0 FUNCTION Power-on reset. 0 = status register has been read 1 = power reset since last status register read LD[2:0] 6, 5, 4 000 VCO tuning voltage indicators. 000 = PLL not in lock, tune to the next lowest sub-band 001–110 = PLL in lock 111 = PLL not in lock, tune to the next higher sub-band Reserved 3–0 0000 Reserved. 2-Wire Serial Interface The MAX3540 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX3540 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX3540 behaves as a slave device that transfers and receives data to and from the master. Pull SDA and SCL high with external pullup resistors (1kΩ or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX3540 (8 data bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy. START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3540 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device 10 Table 15. MAX3540 Address Configurations ADDR2 ADDR1 WRITE ADDRESS READ ADDRESS 0 0 0xC0 0xC1 0 1 0xC2 0xC3 1 0 0xC4 0xC5 1 1 0xC6 0xC7 must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time. Slave Address The MAX3540 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is determined by the state of the ADDR2 and ADDR1 pins and is equal to 11000[ADDR2][ADDR1]. The 8th bit (R/W) following the 7-bit address determines whether a read or write operation will occur. Table 15 shows the possible address configurations. ______________________________________________________________________________________ Complete Single-Conversion Television Tuner Figure 2 illustrates an example in which registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively. Read Cycle A read cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3540 issues an ACK if the slave address byte is successfully received. The master then sends the 8-bit address of the first register that it wishes to read. The MAX3540 then issues another ACK. Next, the master must issue a START condition followed by the 7 slave address bits and a read bit (R/W = 1). The MAX3540 issues an ACK if it successfully recognizes its address and begins sending data from the specified register address starting with the most significant bit (MSB). Data is clocked out of the MAX3540 on the rising edge of SCL. On the 9th rising edge of SCL, the master can issue an ACK and continue reading successive registers or it can issue a NACK followed by a STOP condition to terminate transmission. The read cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which registers 0 and 1 are read back. Write Cycle When addressed with a write command, the MAX3540 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit (R/W = 0). The MAX3540 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to. If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX3540 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX3540 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition. SLAVE ADDRESS S 1 1 0 0 0 ADDR2 ADDR1 R/W 1 2 3 4 5 6 7 8 ACK P SDA SCL 9 NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS. Figure 1. MAX3540 Slave Address Byte START WRITE DEVICE ADDRESS R/W ACK WRITE REGISTER ADDRESS ACK WRITE DATA TO REGISTER 0x00 ACK WRITE DATA TO REGISTER 0x01 ACK WRITE DATA TO REGISTER 0x02 ACK 11000[ADDR2][ADDR1] 0 — 0x00 — 0x0E — 0xD8 — 0xE1 — R/W ACK READ DATA REG 0 ACK READ DATA REG 1 NACK D7–D0 — D7–D0 — STOP Figure 2. Example: Write registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively. START WRITE DEVICE ADDRESS R/W ACK WRITE 1st REGISTER ADDRESS ACK 110000[ADDR2][ADDR1] 0 — 0x00 — START WRITE DEVICE ADDRESS 110000[ADDR2][ADDR1] 1 — STOP Figure 3. Example: Read data from registers 0 through 1. ______________________________________________________________________________________ 11 MAX3540 The MAX3540 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period. It is ready to accept or send data depending on the R/W bit (Figure 1). MAX3540 Complete Single-Conversion Television Tuner Applications Information RF Inputs The MAX3540 features separate UHF and VHF inputs that are matched to 75Ω. Both inputs require a DC-blocking capacitor. The input registers select the active inputs. In addition, the input registers enable or disable the lowpass filter, which can be used when the VHF input is selected. For 54MHz to 100MHz, select the VHF_IN with the LPF filter enabled (INPT = 00). For 100MHz to 300MHz, select VHF_IN with LPF disabled (INPT = 01). For 300MHz to 860MHz, select UHF_IN (INPT = 10). RF Gain Control The gain of the RF low-noise amplifier can be adjusted over a typical 45dB range by the RFAGC pin. The RFAGC input accepts a DC voltage from 0.5V to 3V, with 3V providing maximum gain. This pin can be controlled with the IF power-detector output to form a closed RF gain-control loop. See the Closed-Loop RF Gain Control section for more information. RF Tracking Filter The MAX3540 includes a programmable tracking filter for each band of operation to optimize rejection of out-ofband interference while minimizing insertion loss for the desired received signal. VHF low, VHF high, or UHF tracking filter is selected by the TF register. The center fre- quency of each tracking filter is selected by a switchedcapacitor array, which is programmed by the TFS[7:0] bits in the Tracking-Filter Series Cap register and the TFP[5:0] bits in the Tracking-Filter Parallel Cap register. To accommodate part-to-part variations each part is factory-calibrated by Maxim. During calibration the y-intercept and slope for the series and parallel tracking capacitor arrays is calculated and written into an internal ROM table. The user must read the ROM table upon power-up and store the data in local memory (8 bytes total) to calculate the optimal TFS[7:0] and TFP[5:0] settings for each channel. Table 16 shows the address and bits for each ROM table entry. See the Interpolating Tracking Filter Coefficients section for more information on how to calculate the required values. Reading the ROM Table Each ROM table entry must be read using a two-step process. First, the address of the ROM bits to be read must be programmed into the TFA[3:0] bits in the Tracking Filter ROM Address register (Table 11). Once the address has been programmed, the data stored in that address is transferred to the TFR[7:0] bits in the ROM Table Data Readback register (Table 13). The ROM data at the specified address can then be read from the TFR[7:0] bits and stored in the microprocessor’s local memory. Table 16. ROM Table MSB DESCRIPTION LSB ADDRESS DATA BYTE D7 D6 D5 D4 D3 D2 D1 D0 IFOVLD 0x0 OD2 OD1 OD0 X X X X X VHF Low Series/ Parallel Y-Intercept 0x1 LS0[5] LS0[4] LS0[3] LS0[2] LS0[1] LS0[0] LS1[3] LS1[2] VHF High Series/ Parallel Y-Intercept 0x2 LS1[1] LS1[0] LP0[5] LP0[4] LP0[3] LP0[2] LP0[1] LP0[0] UHF Series/ Parallel Y-Intercept 0x3 LP1[3] LP1[2] LP1[1] LP1[0] HS0[3] HS0[2] HS0[1] HS0[0] VHF Low Series Slope 0x4 HS1[3] HS1[2] HS1[1] HS1[0] HP0[3] HP0[2] HP0[1] HP0[0] VHF High Parallel Slope 0x5 HP1[3] HP1[2] HP1[1] HP1[0] US0[7] US0[6] US0[5] US0[4] VHF Low Parallel Slope 0x6 US0[3] US0[2] US0[1] US0[0] US1[5] US1[4] US1[3] US1[2] VHF High Parallel Slope 0x7 US1[1] US1[0] UP0[7] UP0[6] UP0[5] UP0[4] UP0[3] UP0[2] UHF Parallel Slope 0x8 UP0[1] UP0[0] UP1[5] UP1[4] UP1[3] UP1[2] UP1[1] UP1[0] 12 ______________________________________________________________________________________ Complete Single-Conversion Television Tuner ⎡ ⎤ LS0 LS1 TFS = 10 ⎢(2.4 + × 0.6) + (−8.5 + × 2) × f RF × 10 -3 ⎥⎦ 16 64 ⎣ ⎡ LP0 LP1 -3 ⎤ ⎢ [(1.6 + 64 × 0.4) + (−6 + 16 × 2 ) × f RF × 10 ] ⎥ TFP = INT ⎢10 ⎥ ⎥⎦ ⎣⎢ The nominal full-scale current sunk by the IFOVLD pin is 300μA. The IFOVLD pin requires a 10kΩ pullup resistor to VCC. The IF overload detector is calibrated at the factory to attack at 0.6VP-P at IFOUT1. Upon power-up, the baseband processor must read OD[2:0] from the ROM table and store it in the IFVOLD register. Closed-Loop RF Gain Control Closed-loop RF gain control can be implemented by connecting the IFOVLD output to the RFAGC input. Using a 10kΩ pullup resistor on the IFOVLD pin, as shown in the Typical Application Circuit, results in a nominal 0.5V to 3V control voltage range. VCO and VCO Divider Selection VHF High filter: ⎡ HS0 HS1 -3 ⎤ ⎢ [(2.8 + 16 × 0.8) + (−4.2 + 16 × 0.8 ) × f RF × 10 ] ⎥ TFS = INT ⎢10 ⎥ − 20 ⎥⎦ ⎢⎣ ⎡ HP0 HP1 -3 ⎤ ⎢ [(1.6 + 16 × 0.8) + (−1.5 + 16 × 0.6 ) × f RF × 10 ] ⎥ TFP = INT ⎢10 ⎥ − 10 ⎥⎦ ⎣⎢ UHF filter: ⎡ US0 US1 -3 ⎤ ⎢ [(3 + 256 ) + (−2.6 + 64 × 0.8 ) × f RF × 10 ] ⎥ TFS = INT ⎢10 ⎥ − 20 ⎥⎦ ⎢⎣ ⎡ UP0 UP1 -3 ⎤ ⎢ [(1.6 + 256 × 0.8) + (−1.4 + 64 × 0.8 ) × f RF × 10 ] ⎥ TFP = INT ⎢10 ⎥ − 10 ⎥⎦ ⎣⎢ Where: fRF = operating frequency in MHz TFS = decimal value of the optimal TFS[7:0] setting (Table 9) for the given operating frequency TFP = decimal value of the optimal TFP[5:0] setting (Table 10) for the given operating frequency LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0, US1, UP0, and UP1 = the decimal values of the ROM table coefficients (Table 16). IF Overload Detector The MAX3541 includes a broadband IF overload detector, which provides an indication of the total power present at the RF input. The overload-detector output voltage is compared to a reference voltage and the difference is amplified. This error signal drives an opencollector transistor whose collector is connected to the IFOVLD pin, causing the IFOVLD pin to sink current. The MAX3540 frequency synthesizer includes three VCOs and eight VCO sub-bands to guarantee a 2160MHz to 4400MHz VCO frequency range. The frequency synthesizer also features an additional VCO frequency divider, which must be programmed to either 4, 8, 16, or 32 through the VDIV[1:0] bits in the VCO register based on the channel being received. Table 5 describes how the VDIV[1:0] bits should be programmed for each band of operation. To ensure PLL, lock the proper VCO and VCO sub-band for the channel being received, which must be chosen by iteratively selecting a VCO and VCO sub-band then reading the LD[2:0] bits to determine if the PLL is locked. Any reading from 001 to 110 indicates the PLL is locked. If LD[2:0] reads 000, the PLL is unlocked and the selected VCO is at the bottom of its tuning range; a lower VCO subband must be selected. If LD[2:0] reads 111, the PLL is unlocked and the selected VCO is at the top of its tuning range; a higher VCO sub-band must be selected. The VCO and VCO sub-band settings should be progressively increased or decreased until the LD[2:0] reading falls in the 001 to 110 range. Due to overlap between VCO sub-band frequencies, it is possible that multiple VCO settings can be used to tune to the same channel frequency. System performance at a given channel should be similar between the various possible VCO settings, so it is sufficient to select the first VCO and VCO sub-band that provides lock. Layout Considerations The MAX3540 EV kit can serve as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. The exposed paddle must be soldered evenly to the board’s ground plane for proper operation. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling. ______________________________________________________________________________________ 13 MAX3540 Interpolating Tracking Filter Coefficients The TFS[7:0] and TFP[5:0] bits must be reprogrammed for each channel frequency to optimize performance. The optimal settings for each channel can be calculated from the ROM table data using the equations below. VHF LO filter: To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central VCC node. The VCC traces branch out from this node, with each trace going to separate VCC pins of the MAX3540. Each V CC pin must have a bypass capacitor with a low impedance to ground at the frequency of interest. Do not share ground vias among multiple connections to the PCB ground plane. Typical Application Circuit 270Ω 4700pF 470pF 1.3kΩ * 0.033μF * VCC VCC * 22pF 1000pF 1000pF 1000pF 100pF 47μF 2.7Ω RFGND3 RFAGC IFOVLD VCC 0.1μF VCC GND 1000pF GND LDO GND_TUNE VTUNE VCC MUX CP VCC XTALN XTALP VCC VCC 37 36 ÷R 3 PD CP ÷N SERIAL INTERFACE 4 35 34 VCO DIVIDER 33 32 5 6 VREF 31 30 7 29 + - 8 28 9 MAX3540 10 27 EP 11 26 12 25 13 14 15 16 17 18 19 20 21 22 23 IF-SAW FILTER IFOUT10.1μF IFOUT1+ 10kΩ IFOVLD VCC IFOVLD VCC VCC VCC GND 1000pF IFIN- 2.2pF VCC VCC 1000pF GND IFAGC IFOUT2+ 2.7kΩ VIFAGC 0.1μF 24 IFOUT+ IFOUTANTI-ALIASING FILTER VCC 1000pF *CONNECT TO COMMON GROUND POINT AT PIN 39. 14 1000pF IFIN+ IFOUT2- LEXT 1000pF 1000pF RFGND2 38 1 2 680nH 1000pF VCC 470nF 39 GND VCC 40 GND 1000pF 41 GND VHF_IN 42 GND UHF_IN 43 GND VCC 1000pF 44 GND 100Ω 45 GND SDA SDATA 46 GND SCL SCLK 47 GND VCC 48 2.7kΩ ADDR1 ADDR2 ADDRESS2 2.7kΩ 1000pF * ADDRESS1 VCC SAW DRIVER AMPLIFIER VCC 100pF GND MAX3540 Complete Single-Conversion Television Tuner ______________________________________________________________________________________ Complete Single-Conversion Television Tuner 48L LGA.EPS ______________________________________________________________________________________ 15 MAX3540 Package Information (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) MAX3540 Complete Single-Conversion Television Tuner Package Information (continued) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.) Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time. 16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 © 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.