MAXIM MAX9172ETA

19-2578; Rev 2; 6/07
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Features
The MAX9171/MAX9172 single/dual low-voltage differential
signaling (LVDS) receivers are designed for high-speed
applications requiring minimum power consumption,
space, and noise. Both devices support switching rates
exceeding 500Mbps while operating from a single 3.3V
supply.
♦ Input Accepts LVDS and LVPECL
The MAX9171 is a single LVDS receiver and the
MAX9172 is a dual LVDS receiver. Both devices conform to the ANSI TIA/EIA-644 LVDS standard and convert LVDS to LVTTL/LVCMOS-compatible outputs. A
fail-safe feature sets the outputs high when the inputs
are undriven and open, terminated, or shorted. The
MAX9171/MAX9172 are available in 8-pin SO packages
and space-saving thin DFN and SOT23 packages.
♦ Flow-Through Pinout Simplifies PCB Layout
For lower skew devices, refer to the MAX9111/ MAX9113
data sheet.
♦ -40°C to +85°C Operating Temperature Range
♦ In-Path Fail-Safe Circuit
♦ Space-Saving 8-Pin TDFN and SOT23 Packages
♦ Fail-Safe Circuitry Sets Output High for Open,
Undriven Shorted, or Undriven Terminated Output
♦ Guaranteed 500Mbps Data Rate
♦ Second Source to DS90LV018A and DS90LV028A
(SO Packages Only)
♦ Conforms to ANSI TIA/EIA-644 Standard
♦ 3.3V Supply Voltage
♦ Low-Power Dissipation
Applications
Ordering Information
Multipoint Backplane Interconnect
PART
Laser Printers
PIN-PACKAGE
TOP
MARK
PKG
CODE
AALX
K8-1
Digital Copiers
MAX9171EKA-T
8 SOT23-8
Cellular Phone Base Stations
MAX9171ESA
8 SO
—
S8-2
LCD Displays
MAX9171ETA*
8 Thin DFN-EP**
—
T833-2
AALY
K8-1
Network Switches/Routers
Clock Distribution
MAX9172EKA-T
8 SOT23-8
MAX9172ESA
8 SO
—
S8-2
MAX9172ETA*
8 Thin DFN-EP**
—
T833-2
Note: All devices are specified over the -40°C to +85°C operating
temperature range.
*Future product—contact factory for availability.
**EP = Exposed pad.
T = Tape-and-reel.
Pin Configurations
MAX9171
MAX9171
MAX9172
MAX9172
IN- 1
8 VCC
VCC
1
8 IN-
IN1- 1
8 VCC
VCC 1
8 IN1-
IN+ 2
7 OUT
GND
2
7 IN+
IN1+ 2
7 OUT1
GND 2
7 IN1+
N.C. 3
6 N.C.
OUT
3
6 N.C.
IN2+ 3
6 OUT2
OUT1 3
6 IN2+
N.C. 4
5 GND
N.C.
4
5 N.C.
IN2- 4
5 GND
OUT2 4
5 IN2-
SO/TDFN*
SOT23
SO/TDFN*
SOT23
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
MAX9171/MAX9172
General Description
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
ABSOLUTE MAXIMUM RATINGS
Operating Temperature Range ..........................-40°C to +85°C
Junction Temperature .....................................................+150°C
Storage Temperature Range ............................-65°C to +150°C
ESD Protection
Human Body Model (IN_+, IN_-) ...................................±13kV
Lead Temperature (soldering, 10s) ................................+300°C
VCC to GND ...........................................................-0.3V to +4.0V
IN_+, IN_- to GND .................................................-0.3V to +4.0V
OUT_ to GND ............................................-0.3V to (VCC + 0.3V)
Continuous Power Dissipation (TA = +70°C)
8-Pin SOT23 (derate 8.9mW/°C above +70°C) ...........714mW
8-Pin SO (derate 5.9mW/°C above +70°C) .................471mW
8-Pin TDFN (derate 24.4mW/°C above +70°C) ........1951mW
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC = 3.0V to 3.6V, differential input voltage |VID| = 0.1V to 1.2V, receiver input voltage = 0 to VCC, common-mode voltage VCM =
|VID/2| to (VCC - |VID/2|), TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, |VID| = 0.2V, VCM = 1.2V,
TA = +25°C.) (Notes 1, 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
-40
0
UNITS
LVDS INPUTS (IN_+, IN_-)
Differential Input High Threshold
VTH
Figure 1
Differential Input Low Threshold
VTL
Figure 1
-100
-40
Input Current (Noninverting Input)
IIN+
Figure 1
+0.5
-2.1
-5.0
µA
VIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0
or open (Figure 1)
-0.5
0
+0.5
µA
Figure 1
-0.5
+4.4
+10.0
µA
VIN+ = 0 to 3.6V, VIN- = 0 to 3.6V, VCC = 0
or open (Figure 1)
-0.5
0
+0.5
µA
Open, undriven short, or
IOH = -4.0mA undriven parallel termination
2.7
3.2
2.7
3.2
Power-Off Input Current
(Noninverting Input)
Input Current (Inverting Input)
Power-Off Input Current
(Inverting Input)
IIN+OFF
IINIIN-OFF
mV
mV
LVCMOS/LVTTL OUTPUTS (OUT_)
Output High Voltage
VOH
VID = 0V
Output Low Voltage
VOL
IOL = 4.0mA, VID = -100mV
Output Short-Circuit Current
IOS
VOUT_ = 0 (Note 3)
ICC
Inputs open
V
0.1
0.4
V
-77
-120
mA
MAX9171
3.6
6
MAX9172
7.0
9
-45
POWER SUPPLY
Supply Current
2
_______________________________________________________________________________________
mA
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
(VCC = 3.0V to 3.6V, CL = 15pF, |VID| = 0.2V, VCM = 1.2V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC =
3.3V, TA = +25°C.) (Notes 4, 5, 6)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Propagation Delay
High to Low
tPHLD
Figures 2, 3
1.0
1.65
2.5
ns
Differential Propagation Delay
Low to High
tPLHD
Figures 2, 3
1.0
1.62
2.5
ns
Differential Pulse Skew
|tPHLD - tPLHD|
tSKD1
Figures 2, 3 (Note 7)
30
400
ps
Differential Channel-to-Channel
Skew (MAX9172)
tSKD2
Figures 2, 3 (Note 8)
40
500
ps
tSKD3
Figures 2, 3 (Note 9)
1
tSKD4
Figures 2, 3 (Note 10)
1.5
Differential Part-to-Part Skew
ns
Rise Time
tTLH
Figures 2, 3
0.55
0.8
ns
Fall Time
tTHL
Figures 2, 3
0.51
0.8
ns
fMAX
All channels switching, VOL(MAX) = 0.4V,
VOH(MIN) = 2.7V, 40% < duty cycle < 60%
Maximum Operating Frequency
250
300
MHz
Note 1: Current into a pin is defined as positive. Current out of a pin is defined as negative. All voltages are referenced to GND
except VTH, VTL, and VID.
Note 2: All devices are 100% production tested at TA = +25°C and are guaranteed by design for TA = -40°C to +85°C, as specified.
Note 3: Short only one output at a time. Do not exceed the absolute maximum junction temperature specification.
Note 4: AC parameters are guaranteed by design and not production tested.
Note 5: CL includes scope probe and test jig capacitance.
Note 6: Pulse generator output conditions: tR = tF < 1ns (0% to 100%), frequency = 250MHz, 50% duty cycle, VOH = 1.3V, VOL = 1.1V.
Note 7: tSKD1 is the magnitude of the difference of differential propagation delays in a channel. tSKD1 = |tPHLD - tPLHD|.
Note 8: tSKD2 is the magnitude of the difference of the tPLHD or tPHLD of one channel and the tPLHD or tPHLD of the other channel on
the same part.
Note 9: tSKD3 is the magnitude of the difference of any differential propagation delays between parts at the same VCC and within
5°C of each other.
Note 10: tSKD4 is the magnitude of the difference of any differential propagation delays between parts operating over the rated
supply and temperature ranges.
_______________________________________________________________________________________
3
MAX9171/MAX9172
SWITCHING CHARACTERISTICS
Typical Operating Characteristics
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, fIN = 200MHz, CL = 15pF, TA = +25°C, unless otherwise specified.)
OUTPUT LOW VOLTAGE
vs. SUPPLY VOLTAGE
3.4
3.3
3.2
3.1
IOL = +4mA
-65
OUTPUT SHORT-CIRCUIT CURRENT (mA)
95
90
85
3.0
2.9
80
3.0
3.1
3.2
3.3
3.4
3.5
3.6
-70
-75
-80
-85
3.1
3.0
3.2
3.3
3.4
3.5
3.6
3.1
3.0
3.2
3.3
3.4
3.5
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
DIFFERENTIAL THRESHOLD VOLTAGE
vs. SUPPLY VOLTAGE
MAX9172 SUPPLY CURRENT
vs. FREQUENCY
MAX9172 SUPPLY CURRENT
vs. TEMPERATURE
HIGH-LOW
-45
30
20
BOTH CHANNELS
SWITCHING
10
LOW-HIGH
-55
3.1
3.2
3.3
3.4
3.5
3.6
6
1
0.1
SUPPLY VOLTAGE (V)
10
100
1000
-40
-15
FREQUENCY (MHz)
35
DIFFERENTIAL PROPAGATION DELAY
vs. TEMPERATURE
2.0
tPHLD
tPLHD
1.5
2.0
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9171 toc07
2.5
10
TEMPERATURE (°C)
DIFFERENTIAL PROPAGATION DELAY
vs. SUPPLY VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
7
ONE CHANNEL
SWITCHING
0
3.0
1.9
1.8
tPHLD
1.7
tPLHD
1.6
1.5
1.0
3.0
3.1
3.2
3.3
3.4
SUPPLY VOLTAGE (V)
3.5
3.6
8
MAX9171 toc08
-50
f = 1MHz
BOTH CHANNELS SWITCHING
SUPPLY CURRENT (mA)
SUPPLY CURRENT (mA)
-40
9
MAX9171 toc05
40
MAX9171 toc04
-35
4
VID = +200mV, OUTPUT
SHORTED TO GROUND
MAX9171 toc06
OUTPUT HIGH VOLTAGE (V)
3.5
100
MAX9171 toc02
IOH = -4mA
OUTPUT LOW VOLTAGE (mV)
MAX9171 toc01
3.6
OUTPUT SHORT-CIRCUIT CURRENT
vs. SUPPLY VOLTAGE
MAX9171 toc03
OUTPUT HIGH VOLTAGE
vs. SUPPLY VOLTAGE
DIFFERENTIAL THRESHOLD VOLTAGE (mV)
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
3.6
-40
-15
10
35
60
TEMPERATURE (°C)
_______________________________________________________________________________________
85
60
85
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
DIFFERENTIAL PULSE SKEW
vs. TEMPERATURE
90
60
30
120
80
40
3.0
0
3.0
3.1
3.2
3.3
3.4
3.5
3.6
MAX9171 toc11
160
0
fIN = 20MHz
2.5
2.0
tPHLD
tPLHD
1.5
1.0
-15
-40
10
35
60
85
600
100
1100
1600
2100
2600
TEMPERATURE (°C)
DIFFERENTIAL INPUT VOLTAGE (mV)
DIFFERENTIAL PROPAGATION DELAY
vs. COMMON-MODE VOLTAGE
TRANSITION TIME vs. TEMPERATURE
DIFFERENTIAL PROPAGATION DELAY
vs. LOAD
1.9
tPHLD
tPLHD
1.6
600
tTLH
500
tTHL
400
1.3
1.0
2.4
DIFFERENTIAL PROPAGATION DELAY (ns)
TRANSITION TIME (ps)
2.2
MAX9171 toc13
700
MAX9171 toc12
fIN = 20MHz
1.1
1.6
2.1
2.6
3.1
-40
-15
COMMON-MODE VOLTAGE (V)
10
35
tPHLD
2.0
tPLHD
1.8
1.6
20
30
1300
tTLH
900
tTHL
500
100
300
MAX9171 toc16
1700
50
DIFFERENTIAL PULSE SKEW
vs. INPUT TRANSITION TIME
MAX9171 toc15
2100
40
LOAD (pF)
TEMPERATURE (°C)
TRANSITION TIME vs. LOAD
TRANSITION TIME (ps)
2.2
10
85
60
DIFFERENTIAL PULSE SKEW (ps)
0.6
fIN = 20MHz
1.4
300
0.1
MAX9171 toc14
SUPPLY VOLTAGE (V)
2.5
DIFFERENTIAL PROPAGATION DELAY (ns)
MAX9171 toc10
200
DIFFERENTIAL PULSE SKEW (ps)
MAX9171 toc09
DIFFERENTIAL PULSE SKEW (ps)
120
DIFFERENTIAL PROPAGATION DELAY
vs. DIFFERENTIAL INPUT VOLTAGE
DIFFERENTIAL PROPAGATION DELAY (ns)
DIFFERENTIAL PULSE SKEW
vs. SUPPLY VOLTAGE
250
200
150
100
50
0
10
20
30
LOAD (pF)
40
50
1.0
1.5
2.0
2.5
3.0
INPUT TRANSITION TIME (ns)
_______________________________________________________________________________________
5
MAX9171/MAX9172
Typical Operating Characteristics (continued)
(VCC = 3.3V, VCM = 1.2V, |VID| = 0.2V, fIN = 200MHz, CL = 15pF, TA = +25°C, unless otherwise specified.)
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
MAX9171/MAX9172
MAX9171 Pin Description
PIN
NAME
FUNCTION
SOT23
SO/TDFN
1
8
VCC
Positive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.
2
5
GND
Ground
3
7
OUT
Receiver Output
4, 5, 6
3, 4, 6
N.C.
No Connection. Not internally connected.
7
2
IN+
Noninverting Differential Receiver Input
8
1
IN-
Inverting Differential Receiver Input
—
(TDFN only)
EP
Exposed Paddle. Solder to PCB ground.
MAX9172 Pin Description
PIN
NAME
FUNCTION
VCC
Positive Power-Supply Input. Bypass with a 0.1µF and a 0.001µF capacitor to GND with the
smallest capacitor closest to the pin.
5
GND
Ground
7
OUT1
Receiver Output 1
4
6
OUT2
Receiver Output 2
5
4
IN2-
Inverting Differential Receiver Input 2
6
3
IN2+
Noninverting Differential Receiver Input 2
7
2
IN1+
Noninverting Differential Receiver Input 1
8
1
IN1-
Inverting Differential Receiver Input 1
—
(TDFN only)
EP
SOT23
SO/TDFN
1
8
2
3
Exposed Paddle. Solder to PCB ground.
Detailed Description
LVDS Inputs
The MAX9171/MAX9172 feature LVDS inputs for interfacing high-speed digital circuitry. The LVDS interface
standard is a signaling method intended for point-topoint communication over controlled-impedance
media, as defined by the ANSI TIA/EIA-644 standards.
The technology uses low-voltage signals to achieve fast
transition times and minimize power dissipation and
noise immunity. The MAX9171/MAX9172 convert LVDS
Table 1. Input-Output Function Table
INPUTS
OUTPUT
(IN_+) - (IN_-)
OUT_
≥ 0mV
High
≤ -100mV
Low
Open
High
Undriven short
High
Undriven parallel termination
High
6
signals to LVCMOS/LVTTL signals at rates in excess of
500Mbps. These devices are capable of detecting differential signals as low as 100mV and as high as 1.2V
within a 0 to VCC input voltage range. Table 1 is the
input-output function table.
Fail-Safe
The MAX9171/MAX9172 fail-safe drives the receiver
output high when the differential input is:
• Open
• Undriven and shorted
• Undriven and terminated
Without fail-safe, differential noise at the input may
switch the receiver and appear as data to the receiving
system. An open input occurs when a cable and termination are disconnected. An undriven, terminated input
occurs when a cable is disconnected with the termination still connected across the receiver inputs or when
the driver of a receiver is in high impedance. An undriven, shorted input can occur due to a shorted cable.
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
2.5µA
IN_+
OUT_
40mV
IN_-
5µA
Figure 1. Input with In-Path Fail-Safe Network Equivalent Circuit
IN_+
PULSE
GENERATOR
OUT_
IN_15pF
50Ω
50Ω
Figure 2. Propagation Delay and Transition Test Time Circuit
The MAX9171/MAX9172 have in-path fail-safe that is
compatible with in-path fail-safe receivers, such as the
DS90LV018A and DS90LV028A. Refer to the MAX9111/
MAX9113 data sheet for pin-compatible receivers with
parallel fail-safe and lower jitter. Refer to the MAX9130
data sheet for a single LVDS receiver with parallel failsafe in an SC70 package.
The MAX9171/MAX9172 with in-path fail-safe are
designed with a +40mV input offset voltage, a 2.5µA
current source between V CC and the noninverting
input, and a 5µA current sink between the inverting
input and ground (Figure 1). If the differential input is
open, the 2.5µA current source pulls the input to VCC 0.7V and the 5µA source sink pulls the inverting input to
ground, which drives the receiver output high. If the differential input is shorted or terminated with a typical
value termination resistor, the +40mV offset drives the
receiver output high. If the input is terminated and floating, the receiver output is driven high by the +40mV offset, and the 2:1 current sink to current source ratio
(5µA:2.5µA) pulls the inputs to ground. This can be an
advantage when switching between drivers on a multipoint bus because the change in common-mode voltage from ground to the typical driver offset voltage of
1.2V is not as much as the change from VCC to 1.2V
(parallel fail-safe pulls the bus to VCC). Figure 2 shows
the propagation delay and transition test time circuit
and Figure 3 shows the propagation delay and transition test time waveforms.
1.3V
IN_1.2V (0V DIFFERENTIAL)
VID = 0.2V
1.1V
IN_+
tPLHD
tPHLD
VOH
80%
1.5V
80%
1.5V
20%
20%
VOL
OUT_
tTLH
tTHL
Figure 3. Propagation Delay and Transition Time Waveforms
_______________________________________________________________________________________
7
MAX9171/MAX9172
In-Path vs. Parallel Fail-Safe
VCC
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
ESD Protection
Termination
ESD protection structures are incorporated on all pins
to protect against electrostatic discharges encountered
during handling and assembly. The receiver inputs of
the MAX9171/MAX9172 have extra protection against
static electricity. These pins are protected to ±13kV
without damage. The structures withstand ESD during
normal operation and when powered down.
The receiver inputs of these devices are characterized
for protection to the limit of ±13kV using the Human
Body Model.
The MAX9171/MAX9172 require an external termination
resistor. The termination resistor should match the differential impedance of the transmission line. Termination
resistance values may range between 90Ω to 132Ω,
depending on the characteristic impedance of the
transmission medium.
When using the MAX9171/MAX9172, minimize the distance between the input termination resistors and the
MAX9171/MAX9172 receiver inputs. Use a single 1%
surface-mount resistor.
Human Body Model
Board Layout
Figure 4a shows the Human Body Model, and Figure
4b shows the current waveform it generates when discharged into a low-impedance load. This model consists of a 100pF capacitor charged to the ESD test
voltage, which is then discharged into the test device
through a 1.5kΩ resistor.
For LVDS applications, a four-layer PCB that provides
separate power, ground, LVDS signals, and output signals is recommended. Separate the input LVDS signals
from the output signals to prevent crosstalk. Solder the
exposed pad on the TDFN package to a pad connected
to the PCB ground plane by a matrix of vias. Connecting
the exposed pad is not a substitute for connecting the
ground pin. Always connect pin 5 on the TDFN package to ground.
Applications Information
Supply Bypassing
Bypass VCC with high-frequency surface-mount ceramic 0.1µF and 0.001µF capacitors in parallel, as close to
the device as possible, with the 0.001µF capacitor closest to the device. For additional supply bypassing,
place a 10µF tantalum or ceramic capacitor at the point
where power enters the circuit board.
RC 1MΩ
RD 1500Ω
DISCHARGE
RESISTANCE
CHARGE-CURRENT
LIMIT RESISTOR
HIGHVOLTAGE
DC
SOURCE
Cs
100pF
DEVICE
UNDER
TEST
STORAGE
CAPACITOR
Differential Traces
Input trace characteristics affect the performance of the
MAX9171/MAX9172. Use controlled-impedance PCB
traces to match the cable characteristic impedance.
Eliminate reflections and ensure that noise couples as
common mode by running the differential traces close
together. Reduce skew by matching the electrical
length of traces.
Each channel’s differential signals should be routed
close to each other to cancel their external magnetic
field. Maintain a constant distance between the differential traces to avoid discontinuities in differential
impedance. Avoid 90° turns and minimize the number
of vias to further prevent impedance discontinuities.
Cables and Connectors
Transmission media typically have a controlled differential impedance of about 100Ω. Use cables and connectors that have matched differential impedance to
minimize impedance discontinuities. Balanced cables
tend to pick up noise as common mode, which is
rejected by the LVDS receiver.
8
Figure 4a. Human Body ESD Test Modules
IP 100%
90%
Ir
PEAK-TO-PEAK RINGING
(NOT DRAWN TO SCALE)
AMPERES
36.8%
10%
0
0
tRL
TIME
tDL
CURRENT WAVEFORM
Figure 4b. Human Body Current Waveform
Chip Information
TRANSISTOR COUNT: 624
PROCESS: CMOS
_______________________________________________________________________________________
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
SOT23, 8L .EPS
_______________________________________________________________________________________
9
MAX9171/MAX9172
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
DIM
A
A1
B
C
e
E
H
L
N
E
H
INCHES
MILLIMETERS
MAX
MIN
0.069
0.053
0.010
0.004
0.014
0.019
0.007
0.010
0.050 BSC
0.150
0.157
0.228
0.244
0.016
0.050
MAX
MIN
1.35
1.75
0.10
0.25
0.35
0.49
0.19
0.25
1.27 BSC
3.80
4.00
5.80
6.20
0.40
SOICN .EPS
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
1.27
VARIATIONS:
1
INCHES
TOP VIEW
DIM
D
D
D
MIN
0.189
0.337
0.386
MAX
0.197
0.344
0.394
MILLIMETERS
MIN
4.80
8.55
9.80
MAX
5.00
8.75
10.00
N MS012
8
AA
14
AB
16
AC
D
A
B
e
C
0 -8
A1
L
FRONT VIEW
SIDE VIEW
PROPRIETARY INFORMATION
TITLE:
PACKAGE OUTLINE, .150" SOIC
APPROVAL
DOCUMENT CONTROL NO.
21-0041
10
______________________________________________________________________________________
REV.
B
1
1
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
6, 8, &10L, DFN THIN.EPS
______________________________________________________________________________________
11
MAX9171/MAX9172
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
MAX9171/MAX9172
Single/Dual LVDS Line Receivers with
“In-Path” Fail-Safe
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information,
go to www.maxim-ic.com/packages.)
COMMON DIMENSIONS
PACKAGE VARIATIONS
SYMBOL
MIN.
MAX.
PKG. CODE
N
D2
E2
e
JEDEC SPEC
b
[(N/2)-1] x e
A
0.70
0.80
T633-2
6
1.50–0.10
2.30–0.10
0.95 BSC
MO229 / WEEA
0.40–0.05
1.90 REF
D
2.90
3.10
T833-2
8
1.50–0.10
2.30–0.10
0.65 BSC
MO229 / WEEC
0.30–0.05
1.95 REF
E
2.90
3.10
T833-3
8
1.50–0.10
2.30–0.10
0.65 BSC
MO229 / WEEC
0.30–0.05
1.95 REF
A1
0.00
0.05
T1033-1
10
1.50–0.10
2.30–0.10
0.50 BSC
MO229 / WEED-3
0.25–0.05
2.00 REF
L
0.20
0.40
T1033-2
10
1.50–0.10
2.30–0.10
0.50 BSC
MO229 / WEED-3
0.25–0.05
2.00 REF
k
0.25 MIN.
T1433-1
14
1.70–0.10
2.30–0.10
0.40 BSC
----
0.20–0.05
2.40 REF
A2
0.20 REF.
T1433-2
14
1.70–0.10
2.30–0.10
0.40 BSC
----
0.20–0.05
2.40 REF
Revision History
Pages changed at Rev 2: 1, 2, 3, 6, 8, 10, 11, 12
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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
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