FUJITSU MB91F467R

FUJITSU SEMICONDUCTOR
DATA SHEET
DS07-16603-1E
32-bit Microcontroller
CMOS
FR60 MB91460R Series
MB91F467R
■ DESCRIPTION
MB91460R series is a line of the general-purpose 32-bit RISC microcontrollers designed for embedded control
applications such as consumer devices and vehicle system, which require high-speed real-time processing.
MB91460R series uses the FR60 CPU compatible with the FR family* CPUs.
MB91460R series contains the LIN-UART and CAN controller.
* : FR, the abbreviation of FUJITSU RISC controller, is a line of products of FUJITSU Limited.
■ FEATURES
• FR60 CPU
• 32-bit RISC, load/store architecture, five-stage pipeline
• Maximum operating frequency : 80 MHz (oscillation frequency 20 MHz, oscillation frequency 4 multiplier (PLL
clock multiplication method))
• 16-bit fixed-length instructions (basic instructions)
• Instruction execution speed : 1 instruction per cycle
• Instructions including memory-to-memory transfer, bit manipulation instructions, and barrel shift instructions:
Instructions suitable for embedded applications
• Function entry/exit instructions and register data multi load store instructions: Instructions supporting C
language
• Register interlock function : Facilitating assembly-language coding
• Built-in multiplier with instruction-level support
Signed 32-bit multiplication : 5 cycles
Signed 16-bit multiplication : 3 cycles
• Interrupt (PC/PS saving) : 6 cycles (16 priority levels)
(Continued)
Be sure to refer to the “Check Sheet” for the latest cautions on development.
“Check Sheet” is seen at the following support page
URL : http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
“Check Sheet” lists the minimal requirement items to be checked to prevent problems beforehand in system
development.
Copyright©2007 FUJITSU LIMITED All rights reserved
MB91460R Series
• Harvard architecture enabling simultaneous execution of both program access and data access
• Instructions compatible with the FR family
• Internal peripheral resources
• Flash memory capacity : 1088 bytes
• Internal RAM capacity : 0 Wait access 16 Kbytes + 1 Wait access 32 Kbytes + 16 Kbytes
(Instruction/data common RAM)
• General-purpose port : Maximum 138 ports
• DMAC (DMA Controller)
Maximum of 5 channels for simultaneous operation is possible. (1 channel for external-to-external)
3 transfer sources (external pin/internal peripheral/software)
Activation source can be selected using software.
Addressing mode with 32-bit full address indication (increment/decrement/fixed)
Transfer mode (demand transfer/burst transfer/step transfer/block transfer)
Fly-by transfer support (between external I/O and memory)
Transfer data size selection 8/16/32-bit
Multi-byte transfer enabled (by software)
DMAC descriptor in I/O areas (200H to 240H, 1000H to 1024H)
• A/D converter (sequential comparison)
10-bit resolution: 16 channels
Conversion time: 3 µs (peripheral macro operation clock at 16.67 MHz)
• External interrupt input: 16 channels
Pins shared with RX pins of CAN0 and CAN1
• Bit search module (for REALOS)
Function of searching for the first “0” data/ “1” data/change bit position in 1 word from the MSB (upper bit)
• LIN-USART (full duplex double buffer): 7 channels
Clock synchronous/asynchronous selectable
Sync-break detection
Internal dedicated baud rate generator
• I2C* bus interface (400 kbps supported): 3 channels
Master/slave sending and receiving
Arbitration function, clock synchronization function
• CAN controller (C-CAN) : 2 channels
Maximum transfer speed : 1 Mbps
32 sent/received message buffers
• 16-bit PPG timer : 8 channels
• 16-bit reload timer : 5 channels
• 16-bit free-run timer : 4 channels (1 channel each for ICU and OCU)
• Input capture : 4 channels (work with free-run timer)
• Output compare : 4 channels (work with free-run timer)
• Watchdog timer
Watchdog reset output pin available
• Real-time clock
• Low-power consumption mode: Sleep/stop/shutdown mode function
• Clock modulator
• Sub clock calibration
• Main oscillation stabilization wait timer
• Sub oscillation stabilization wait timer
(Continued)
2
MB91460R Series
(Continued)
• Package : LQFP-176 (FPT-176P-M07)
• CMOS 0.18 µm technology
• 3 V/5 V power supplies [Internal logic is kept at 1.8 V by step-down circuit, some I/Os have the withstand voltage
of 5.0 V]
• Operating temperature range : between − 40°C and + 85°C
* : Purchase of Fujitsu I2C components conveys a license under the Philips I2C Patent Rights to use, these
components in an I2C system provided that the system conforms to the I2C Standard Specification as defined
by Philips.
3
MB91460R Series
■ PIN ASSIGNMENT
176 VCO5
175 P17_3/PPG3
174 P17_2/PPG2
173 P17_1/PPG1
172 P17_0/PPG0
171 P14_3/ICU3/TIN3/TRG3
170 P14_2/ICU2/TIN2/TRG2
169 P14_1/ICU1/TIN1/TRG1
168 P14_0/ICU0/TIN0/TRG0
167 P22_3
166 P22_2/INT13
165 P22_0/INT12
164 P23_6/INT11
163 P23_4/INT10
162 VCC5
161 VSS
160 P15_3/OCU3/TOT3
159 P15_2/OCU2/TOT2
158 P15_1/OCU1/TOT1
157 P15_0/OCU0/TOT0
156 P18_2/SCK6
155 P18_1/SOT6
154 P18_0/SIN6
153 P19_6/SCK5
152 P19_5/SOT5
151 P19_4/SIN5
150 P19_2/SCK4
149 P19_1/SOT4
148 P19_0/SIN4
147 VCC5
146 VSS
145 P20_6/SCK3/FRCK3
144 P20_5/SOT3
143 P20_4/SIN3
142 P20_2/SCK2/FRCK2
141 P20_1/SOT2
140 P20_0/SIN2
139 P21_6/SCK1/FRCK1
138 P21_5/SOT1
137 P21_4/SIN1
136 P21_2/SCK0/FRCK0
135 P21_1/SOT0
134 P21_0/SIN0
133 VCC5
(TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
(1)
(2)
(3)
LQFP-176
132 VSS
131 INIT
130 MD0
129 MD1
128 MD2
127 MD3
126 P23_3/TX1
125 P23_2/RX1/INT9
124 P23_1/TX0
123 P23_0/RX0/INT8
122 P24_7/INT7
121 P24_6/INT6
120 P24_1/INT1
119 P24_0/INT0
118 P22_5/SCL0
117 P22_4/SDA0/INT14
116 AVRH
115 AVCC3
114 AVSS/AVRL
113 P28_7/AN15
112 P28_6/AN14
111 P28_5/AN13
110 P28_4/AN12
109 P28_3/AN11
108 P28_2/AN10
107 P28_1/AN9
106 P28_0/AN8
105 P29_7/AN7
104 P29_6/AN6
103 P29_5/AN5
102 P29_4/AN4
101 P29_3/AN3
100 P29_2/AN2
99 P29_1/AN1
98 P29_0/AN0
97 WDRESET
96 P17_7/PPG7
95 P17_6/PPG6
94 P17_5/PPG5
93 P17_4/PPG4
92 P16_7/ATG
91 P05_7/A23
90 P05_6/A22
89 VCC3
VSS
P01_0/D16
P01_1/D17
P01_2/D18
P01_3/D19
P01_4/D20
P01_5/D21
P01_6/D22
P01_7/D23
P00_0/D24
P00_1/D25
P00_2/D26
VCC3
VSS
P00_3/D27
P00_4/D28
P00_5/D29
P00_6/D30
P00_7/D31
P07_0/A00
P07_1/A01
P07_2/A02
P07_3/A03
P07_4/A04
P07_5/A05
P07_6/A06
P07_7/A07
P06_0/A08
VCC3
VSS
P06_1/A09
P06_2/A10
P06_3/A11
P06_4/A12
P06_5/A13
P06_6/A14
P06_7/A15
P05_0/A16
P05_1/A17
P05_2/A18
P05_3/A19
P05_4/A20
P05_5/A21
VSS
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSS
P24_2/INT2
P24_3/INT3
P22_6/SDA1/INT15
P22_7/SCL1
P24_4/SDA2/INT4
P24_5/SCL2/INT5
P13_0/DREQ0
P13_1/DACK0
P13_2/DEOP0
VCC3
VCC3
VSS
C_1
P09_4/CS4
P09_3/CS3
P09_2/CS2
P09_1/CS1
P09_0/CS0
P11_0/IORD
P11_1/IOWR
P08_7/RDY
P08_6/BRQ
P08_5/BGRNT
P08_4/RD
P08_1/WR1
P08_0/WR0
NMI
P10_6/MCLKE
P10_5/MCLKI
P10_4/MCLKO
P10_3/WE
P10_2/BAA
P10_1/AS
P10_0/SYSCLK
VCC3
C_2
VSS
X0
X1
VSS
X0A
X1A
VCC3
(FPT-176P-M07)
Note : (1) to (3) are 3.3 V/5 V pin supported pin, and can set 3.3 V and 5 V to the voltage in each block. I2C pin in
(1) can be inputted at 5 V power supply. However, 3.3 V of the input threshold value is used as the standard
value regardless of the power supply voltage.
If 5 V is set in (1) or (2), also set 5 V to (3).
4
MB91460R Series
■ PIN DESCRIPTION
Pin no.
2
3
Pin name
P24_2
INT2
P24_3
INT3
P22_6
4
SDA1
INT15
P22_7
5
SCL1
P24_4
6
SDA2
INT4
P24_5
7
SCL2
INT5
8
9
10
15
16
17
18
19
20
P13_0
DREQ0
P13_1
DACK0
P13_2
DEOP0
P09_4
CS4
P09_3
CS3
P09_2
CS2
P09_1
CS1
P09_0
CS0
P11_0
IORD
I/O
I/O
circuit
type*
I/O
D
I/O
D
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
I/O
Open
Drain
C
I/O
Open
Drain
C
I/O
Open
Drain
Description
I2C bus DATA input/output pin
External interrupt input pin
General-purpose input/output port
I2C bus Clock input/output pin
General-purpose input/output port
C
I2C bus DATA input/output pin
External interrupt input pin
General-purpose input/output port
I/O
Open
Drain
C
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
I2C bus Clock input/output pin
External interrupt input pin
General-purpose input/output port
DMA external transfer request input pin
General-purpose input/output port
DMA external transfer acknowledgement output pin
General-purpose input/output port
DMA external transfer EOP (End of Process) output pin
General-purpose input/output port
Chip select 4 output pin
General-purpose input/output port
Chip select 3 output pin
General-purpose input/output port
Chip select 2 output pin
General-purpose input/output port
Chip select 1 output pin
General-purpose input/output port
Chip select 0 output pin
General-purpose input/output port
Read strobe output pin at DMA flyby transfer
(Continued)
5
MB91460R Series
Pin no.
21
22
23
24
25
Pin name
P11_1
IOWR
P08_7
RDY
P08_6
BRQ
P08_5
BGRNT
P08_4
RD
I/O
I/O
circuit
type*
I/O
H
I/O
H
I/O
H
I/O
H
I/O
H
P08_1
26
27
WR1
P08_0
29
30
31
32
NMI
P10_6
MCLKE
P10_5
MCLKI
P10_4
MCLKO
P10_3
WE
I/O
H
I/O
H
34
35
6
BAA
P10_1
AS
P10_0
SYSCLK
Write strobe output pin at DMA flyby transfer
General-purpose input/output port
External ready input pin
General-purpose input/output port
External bus release request input pin
General-purpose input/output port
External bus release reception output pin
General-purpose input/output port
External read strobe output pin
External write strobe output pin (DQMU signal when using
SDRAM)
General-purpose input/output port (DQML signal when using
SDRAM)
External write strobe output pin
I
H
I/O
H
I/O
H
I/O
H
I/O
H
P10_2
33
General-purpose input/output port
General-purpose input/output port
WR0
28
Description
NMI (Non Maskable Interrupt) input pin
General-purpose input/output port
Clock enable output signal pin for SDRAM
General-purpose input/output port
Clock input pin for SDRAM
General-purpose input/output port
Clock output pin for SDRAM
General-purpose input/output port
External write enable signal pin
General-purpose input/output port
I/O
H
I/O
H
I/O
H
Address advance output pin for burst mode FLASH
memory
General-purpose input/output port
Address strobe output pin
General-purpose input/output port
System clock output pin
39
X0
⎯
G
Clock (oscillation) input pin
40
X1
⎯
G
Clock (oscillation) output pin
42
X0A
⎯
G
Sub lock (oscillation) input pin
43
X1A
⎯
G
Sub lock (oscillation) output pin
MB91460R Series
(Continued)
I/O
I/O
circuit
type*
I/O
H
I/O
H
I/O
H
P06_0 to P06_7
72
76 to 81
A08 to A15
I/O
H
82 to 87 P05_0 to P05_7
90, 91
A16 to A23
I/O
H
I/O
H
I/O
H
O
I
I/O
F
I/O
F
Pin no.
46 to 53
Pin name
P01_0 to P01_7
D16 to D23
54 to 56 P00_0 to P00_7
59 to 63
D24 to D31
64 to 71
92
93 to 96
97
98 to 105
106 to
113
P07_0 to P07_7
A00 to A07
P16_7
ATG
P17_4 to P17_7
PPG4 to PPG7
WDRESET
P29_0 to P29_7
AN0 to AN7
P28_0 to P28_7
AN8 to AN15
P22_4
117
SDA0
INT14
P22_5
118
SCL0
INT0, INT1
C
INT6
I/O
Open
Drain
C
INT7
General-purpose input/output ports
External data buses (D24 to D31)
General-purpose input/output ports
External address buses (A00 to A07)
General-purpose input/output ports
External address buses (A08 to A15)
General-purpose input/output ports
External address buses (A16 to A23)
General-purpose input/output ports
A/D converter external trigger input
General-purpose input/output ports
PPG timer output pin
Watchdog reset output pin
General-purpose input/output ports
Analog input pins for A/D converter
General-purpose input/output ports
Analog input pins for A/D converter
I2C bus DATA input/output pin
General-purpose input/output port
I2C bus clock input/output pin
General-purpose input/output ports
I/O
D
I/O
D
External interrupt input pins
Can be used as a source for recovering from
shutdown
General-purpose input/output port
P24_7
122
External data buses (D16 to D23)
External interrupt input pin
P24_6
121
General-purpose input/output ports
General-purpose input/output port
I/O
Open
Drain
P24_0, P24_1
119, 120
Description
External interrupt input pin
Can be used as a source for recovering from shutdown
General-purpose input/output port
I/O
D
External interrupt input pin
Can be used as a source for recovering from shutdown
(Continued)
7
MB91460R Series
Pin no.
Pin name
I/O
I/O
circuit
type*
P23_0
123
RX0
General-purpose input/output port
I/O
D
P23_1
TX0
I/O
D
P23_2
125
RX1
P23_3
TX1
I/O
D
I/O
D
MD3
I
A
128
MD2
I
J
129
MD1
I
J
130
MD0
I
J
131
INIT
I
B
I/O
D
I/O
D
135
P21_0
SIN0
P21_1
SOT0
P21_2
136
SCK0
138
P21_4
SIN1
P21_5
SOT1
I/O
D
SCK1
I/O
D
I/O
D
141
P20_0
SIN2
P20_1
SOT2
TX output pin of CAN0
Mode setting pins
External reset input pin
General-purpose input/output port
Data input pin of UART0
General-purpose input/output port
Data output pin of UART0
Clock input/output pin of UART0
General-purpose input/output port
Data input pin of UART1
General-purpose input/output port
Data output pin of UART1
General-purpose input/output port
I/O
D
FRCK1
140
General-purpose input/output port
External clock input pin of free-run timer0
P21_6
139
RX input/output pin of CAN1
General-purpose input/output port
FRCK0
137
TX output pin of CAN0
External interrupt input pin
Can be used as a source for recovering from shutdown
127
134
General-purpose input/output port
General-purpose input/output port
INT9
126
RX input/output pin of CAN0
External interrupt input pin
Can be used as a source for recovering from shutdown
INT8
124
Description
Clock input/output pin of UART1
External clock input pin of free-run timer 1
I/O
D
I/O
D
General-purpose input/output port
Data input pin of UART2
General-purpose input/output port
Data output pin of UART2
(Continued)
8
MB91460R Series
Pin no.
Pin name
I/O
I/O
circuit
type*
P20_2
142
SCK2
General-purpose input/output port
I/O
D
FRCK2
143
144
P20_4
SIN3
P20_5
SOT3
SCK3
I/O
D
I/O
D
149
150
151
152
153
154
155
156
P19_0
SIN4
P19_1
SOT4
P19_2
SCK4
P19_4
SIN5
P19_5
SOT5
P19_6
SCK5
P18_0
SIN6
P18_1
SOT6
P18_2
SCK6
I/O
D
OCU0 to OCU3
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
I/O
D
164
P23_4
INT10
P23_6
INT11
General-purpose input/output port
Data output pin of UART3
Clock input pin of UART3
General-purpose input/output port
Data input pin of UART4
General-purpose input/output port
Data output pin of UART4
General-purpose input/output port
Clock input/output pin of UART4
General-purpose input/output port
Data input pin of UART5
General-purpose input/output port
Data output pin of UART5
General-purpose input/output port
Clock input/output pin of UART5
General-purpose input/output port
Data input pin of UART6
General-purpose input/output port
Data output pin of UART6
General-purpose input/output port
Clock input/output pin of UART6
General-purpose input/output ports
I/O
D
TOT0 to TOT3
163
Data input pin of UART3
External clock input pin of free-run timer 3
P15_0 to P15_3
157 to
160
General-purpose input/output port
General-purpose input/output port
FRCK3
148
Clock input/output pin of UART2
External clock input pin of free-run timer 2
P20_6
145
Description
Output compare output pins
Reload timer output pins
I/O
D
I/O
D
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
(Continued)
9
MB91460R Series
(Continued)
Pin no.
165
166
167
Pin name
P22_0
INT12
P22_2
INT13
P22_3
I/O
I/O
circuit
type*
I/O
D
I/O
D
I/O
D
P14_0 to P14_3
168 to
171
ICU0 to ICU3
TIN0 to TIN3
P17_0 to P17_3
PPG0 to PPG3
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
External interrupt input pin
General-purpose input/output port
General-purpose input/output ports
I/O
D
TRG0 to TRG3
172 to
175
Description
Input capture input pins
External trigger input pins of reload timer
External trigger input pins of PPG
I/O
D
General-purpose input/output ports
PPG timer output pins
* : For I/O circuit type, refer to “■ I/O CIRCUIT TYPE”.
10
MB91460R Series
[Power supply/GND pins]
Pin number
Pin name
I/O
Function
1, 13, 38, 41, 45, 58,
74, 88, 132, 146, 161
VSS
(VSS)
11, 12, 36, 44, 57,
73, 89
VCC3
(VCC3)
3.3 V power supply pins
(VCC5)
5 V power supply pins. These pins are I/O power supplies
corresponding to 117 to 145 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5 V when
supplying 5V. Be sure to supply 5 V if more than one 5V
operating pin is specified, or 5V is supplied at pin 162 or pin
176.
(VCC5)
5 V power supply pin. This pin is an I/O power supply
corresponding to 148 to 160 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5V when
supplying 5 V. Be sure to supply 5 V if more than one 5 V
operating pin is specified.
133, 147
162
VCC5
VCC5
GND pins
176
VCC5
(VCC5)
5 V power supply pin. This pin is an I/O power supply
corresponding to 2 to 7 pins. The corresponding I/O pin
operates at 3.3 V when supplying 3.3 V, and at 5 V when
supplying 5 V. Be sure to supply 5 V if more than one 5 V
operating pin is specified.
114
AVSS/
AVRL
(AVSS)
Analog GND pin for A/D converter
115
AVCC3
(AVCC3)
3.3 V power supply pin for A/D converter
116
AVRH
(AVRH)
Reference power supply pin for A/D converter
14
C_1
⎯
Capacitor connection pin for internal regulator
Connect to a capacitance of 4.7 µF.
37
C_2
⎯
Capacitor connection pin for internal regulator
Connect to a capacitance of 4.7 µF.
11
MB91460R Series
■ I/O CIRCUIT TYPE
Type
Circuit type
Remarks
5 V CMOS hysteresis input
With 50 kΩ pull-down
5 V level
Input
A
N-ch
Pull-down
5 V CMOS hysteresis input
With 50 kΩ pull-up
Pull-up
P-ch
B
Input
5 V level
Output driving N-ch
N-ch
I/O pin for I2C
Withstand voltage of 5 V
(with standby control)
C
Input
Standby control
Pull-up control
P-ch
5 V level
P-ch
Output driving P-ch
N-ch
Output driving N-ch
5 V CMOS output
5 V CMOS input
5 V CMOS hysteresis level input
With pull-up/pull-down control
(with standby control)
D
N-ch
Pull-down control
Input
Standby control
Input
Standby control
(Continued)
12
MB91460R Series
Type
Circuit type
3.3 V level
P-ch
Output driving P-ch
N-ch
Output driving N-ch
F
Remarks
3.3 V CMOS output
3.3 V CMOS input
3.3 V CMOS hysteresis level input
Analog input
(with standby control)
Input
Standby control
Input
Standby control
Analog input
3.3 V oscillation cell
3.3 V level
Input
G
Standby control
Pull-up control
P-ch
3.3 V level
P-ch
Output driving P-ch
N-ch
Output driving N-ch
3.3 V CMOS output
3.3 V CMOS input
3.3 V CMOS hysteresis level input
With pull-up/pull-down control
(with standby control)
H
N-ch
Pull-down control
Input
Standby control
Input
Standby control
(Continued)
13
MB91460R Series
(Continued)
Type
Circuit type
Remarks
3.3 V CMOS output
3.3 V level
P-ch
Output driving P-ch
N-ch
Output driving N-ch
I
5 V CMOS hysteresis input
5 V level
J
14
Input
MB91460R Series
■ HANDLING DEVICES
• Preventing Latch-up
Latch-up may occur in a CMOS IC if a voltage higher than VCC or less than VSS is applied to an input or output
pin or if a voltage exceeding the rating is applied between VCC5 pin (VCC3 pin) and VSS pin. If latch-up occurs,
the power supply current increases rapidly, sometimes resulting in thermal breakdown of the device. Therefore,
when using a CMOS IC, do not exceed the maximum rating.
• Handling of unused input pins
If unused input pins are left open, abnormal operation may result. Any unused input pins should be connected
to pull-up or pull-down resistor.
• Power supply pins
In MB91460R series, devices including multiple VCC5 pin (VCC3 pin) and VSS pin are designed as follows;
pins necessary to be at the same potential are interconnected internally to prevent malfunctions such as latchup. All of the power supply pin and GND pin must be externally connected to the power supply and ground
respectively in order to reduce unnecessary radiation, to prevent strobe signal malfunctions due to the ground
level rising and to follow the total output current ratings. Furthermore, the VCC5 pin (VCC3 pin) pins and VSS
pin of the MB91460R series must be connected to the current supply source via a low impedance.
It is also recommended to connect a ceramic capacitor of approximately 0.1 µF as a bypass capacitor between
VCC5 pin (VCC3 pin) and VSS pin near this device.
This series has a built-in step-down regulator. Connect a bypass capacitor of 4.7 µF to C_1 and C_2 pins for
the regulator.
• Crystal oscillator circuit
Noise in proximity to the X0 and X1 (X0A, X1A) pins can cause abnormal operation in this device. Printed circuit
boards should be designed so that the X0 (X0A) and X1 (X1A) pins, and crystal oscillator, as well as bypass
capacitors connected to ground, are placed as close together as possible.
The use of printed circuit board architecture in which the X0 and X1 (X0A, X1A) pins are surrounded by ground
contributes to stable operation and is strongly recommended.
Please ask the crystal maker to evaluate the oscillational characteristics of the crystal and this device.
• Notes on using external clock
In principle, when using external clock, supply a clock to the X0 pin and X1 pin simultaneously. Also, an opposite
phase clock to the X0 pin must be supplied to the X1 pin. However, in this case the stop mode (oscillation stop
mode) must not be used (This is because the X1 pin stops at ”H” output in STOP mode).
X0
X1
(Note) Stop mode (oscillation stop mode) cannot be used.
Example of using external clock (normal)
15
MB91460R Series
• Mode pins (MD0 to MD3)
When using mode pins, connect them directly to VCC5 pin (VCC3 pin) or VSS pin. To prevent the device from
entering test mode accidentally due to noise, minimize the lengths of the patterns between each mode pin and
VCC5 pin (VCC3 pin) or VSS pin on the printed circuit board as possible and connect them with low impedance.
• Power-on sequences for 3.3 V and 5 V
• Immediately after power-on, keep “L” level input to the INIT pin for the oscillation stabilization wait time (8 ms)
to ensure the oscillation stabilization wait time for the oscillator circuit.
• There is no power-on sequences.
• When executing a reset cancellation (changing INIT pin from “L” level to “H” level), be sure to execute it while
3 V and 5 V power supplies are stable.
• Caution on operations during PLL clock mode
On this microcontroller, if in case the crystal oscillator breaks off or an external reference clock input stops while
the PLL clock mode is selected, a self-oscillator circuit contained in the PLL may continue its operation at its
self-running frequency. However, Fujitsu will not guarantee results of operations if such failure occurs.
• External bus setting
This model guarantees the maximum frequency of 40 MHz for the external bus clock SYSCLK.
Setting the base clock frequency to 80 MHz without changing the initial value of DIVR1 (external bus base clock
division setting register) sets the external bus frequency also to 80 MHz. Before changing the base clock
frequency, set SYSCLK not exceeding 40 MHz.
• Pull-up control
Connecting a pull-up resistor to the pin serving as an external bus pin cannot guarantee the AC standard.
• Notes on PS register
Since some instructions process the PS register in advance, the exceptional operations may cause a break in
the interrupt process routine or an update of display contents of the flag in the PS register when the debugger
is being used. In either case, as the device is designed to carry out reprocessing correctly upon returning from
such an EIT event, it performs operations before and after the EIT as specified.
1) The following operations may be performed when the instruction immediately followed by a DIV0U/DIV0S
instruction accepts a user interrupt/NMI, executes a step, or breaks in response to a data event or emulator
menu.
-D0 and D1 flags are updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the DIV0U/DIV0S instruction is executed and the D0 and D1 flags are updated
to the same values as those in 1).
2) The following operations are performed when each instruction of OR CCR, ST ILM, MOV Ri and PS is
executed to enable interrupts while a user interrupt/NMI source has been occurring.
-The PS register is updated in advance.
-An EIT process routine (user interrupt/NMI or emulator) is executed.
-Upon returning from the EIT, the above instructions are executed and the PS register is updated to the same
value as that in 1).
16
MB91460R Series
■ NOTES ON DEBUGGER
• Step execution of RETI instruction
In the environment where interrupts occur frequently when stepping, only the corresponding interrupt process
routines are repeated. As the result of that, the main routine and low-interrupt-level programs are not executed
(For example, if an interrupt to the time base timer is enabled, a break always occurs at the beginning of the
time base routine when stepping RETI) .
Disable the corresponding interrupts when the debug on the corresponding interrupt process routines becomes
unnecessary.
• Break function
If the target address of a hardware break (including an event break) is set to the address currently contained in
the system stack pointer or in the area containing the stack pointer, the user program causes a break after
execution of one instruction even though there is no actual data access instruction in the user program.
To prevent this, do not set (word) access to the area containing the address of the system stack pointer as the
target of a hardware break (including an event break).
• Operand break
If a stack pointer exists in the area which is set as the DSU operand break, malfunctions may occur. Do not set
the access to the areas containing the address of system stack pointer as a target of data event break.
17
MB91460R Series
■ BLOCK DIAGRAM
FR60 CPU
Core
EDSU/MPU
Bit search
RAM
16 Kbytes (0 wait) +
32 Kbytes (1 wait)
I-bus
32
D-bus
32
CAN
(2 channels)
RX0,RX1
TX0,TX1
32 ↔ 16
Bus adapter
Direct mapped
cache 8 Kbytes
Flash ROM
1088 bytes
Bus
Converter
RAM
16 Kbytes
DREQ0
DACK0
DEOP0
IOWR
IORD
DMAC
(5 channels)
External
bus
interface
SYSCLK
AS
RD
WR0
WR1
MCLKE
MCLKI
MCLKO
WE
BAA
BRQ
BGRNT
CS0 to CS4
R-bus
16
A23 to A00
D31 to D16
Interrupt
controller
Clock control
TRG0 to TRG3
PPG0 to PPG7
TIN0 to TIN3
TOT0 to TOT3
FRCK0 to FRCK3
PPG
(8 channels)
Reload Timer
(5 channels)
Free-run Timer
(4 channels)
ICU0 to ICU3
Input Capture
(4 channels)
OCU0 to OCU3
Output Compare
(4 channels)
External interrupt
(16 channels)
PORT
interface
NMI
INT0 to INT15
PORT
LIN-USART
(7 channels)
(including BRG)
SIN0 to SIN6
SOT0 to SOT6
SCK0 to SCK6
I2C
(3 channels)
SDA0 to SDA2
SCL0 to SCL2
RTC
18
A/D converter
(16 channels)
AN0 to AN15
ATG
MB91460R Series
■ CPU AND CONTROL UNIT
The FR family CPU is a high performance core that is designed based on the RISC architecture with advanced
instructions for embedded applications.
1. Features
• Adoption of RISC architecture
Basic instruction : 1 instruction per cycle
• General-purpose registers : 32-bit × 16 registers
• Linear memory space : 4 Gbytes
• Multiplier installed
32-bit × 32-bit multiplication 5 cycles
16-bit × 16-bit multiplication 3 cycles
• Enhanced interrupt processing function
- Quick response speed (6 cycles)
- Multiple-interrupt support
- Level mask function (16 levels)
• Enhanced instructions for I/O operation
- Memory-to-memory transfer instructions
- Bit processing instructions
• Basic instruction word length 16 bits
• Low-power consumption
Sleep mode/stop mode/shutdown mode
19
MB91460R Series
2. Internal architecture
The FR family CPU uses the Harvard architecture in which the instruction bus and data bus are independent of
each other.
A 32-bit ↔ 16-bit bus adapter is connected to the 32-bit bus (D-bus) to provide an interface between the CPU
and peripheral resources.
A Harvard ↔ Princeton bus converter is connected to both the I-bus and D-bus to provide an interface between
the CPU and the bus controller.
The following figure shows the internal architecture structure.
DSU
(debug support)
FR60 CPU
core
Bit search
Instruction
cache RAM
CAN
(2 channels)
D-bus
32
I-bus
32
RAM
16 Kbytes
Bus converter
32 ↔ 16
bus adapter
R-bus
16
External
bus
interface
DMAC
(5 channels)
Peripheral
resource
20
MB91460R Series
3. Programming model
• Basic programming model
32 bits
Initial value
R0
XXXX XXXXH
R1
...
General-purpose registers
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Program counter
PC
Program status
RS
Table base register
TBR
Return pointer
RP
System stack pointer
SSP
User stack pointer
USP
Multiply and divide result
registers
MDH
ILM
SCR
CCR
MDL
21
MB91460R Series
4. Registers
• General-purpose register
32 bits
Initial value
R0
XXXX XXXXH
R1
...
...
...
...
...
...
...
...
R12
R13
AC
...
R14
FP
XXXX XXXXH
R15
SP
0000 0000H
Registers R0 to R15 are general-purpose registers. These registers can be used as accumulators for computation
operations and as pointers for memory access.
Of the 16 registers, enhanced commands are provided for the following registers to enable their use for particular
applications.
R13 : Virtual accumulator
R14 : Frame pointer
R15 : Stack pointer
Initial values at reset are undefined for R0 to R14. The value for R15 is 00000000H (SSP value).
• PS (Program Status)
This register holds the program status, and is divided into three parts, ILM, SCR, and CCR.
All undefined bits (-) in the diagram are reserved bits. The read values are always “0”. Write access to these bits
is invalid.
Bit position → bit 31
bit 20
bit 16
ILM
22
bit 10 bit 8 bit 7
SCR
bit 0
CCR
MB91460R Series
• CCR (Condition Code Register)
bit 7
S
: Stack flag
I
: Interrupt enable flag
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
S
I
N
Z
V
C
Initial value
- - 00XXXXB
N : Negative enable flag
Z
: Zero flag
V
: Overflow flag
C : Carry flag
• SCR (System Condition Register)
bit 10 bit 9
D1
bit 8
D0
Initial value
T
XX0B
Flag for step multiplication (D1, D0)
This flag stores interim data during execution of step multiplication.
Step trace trap flag (T)
This flag indicates whether the step trace trap is enabled or disabled.
The step trace trap function is used by emulators. When an emulator is in use, it cannot be used in execution
of user programs.
• ILM
bit 20 bit 19 bit 18 bit 17 bit 16
Initial value
ILM4 ILM3 ILM2 ILM1 ILM0
01111B
This register stores interrupt level mask values, and the values stored in ILM4 to ILM0 are used for level masking.
The register is initialized to value “01111B” at reset.
• PC (Program Counter)
bit 31
bit 0
Initial value
XXXXXXXXH
The program counter indicates the address of the instruction that is being executed.
The initial value at reset is undefined.
23
MB91460R Series
• TBR (Table Base Register)
bit 31
bit 0
Initial value
000FFC00H
The table base register stores the starting address of the vector table used in EIT processing.
The initial value at reset is 000FFC00H.
• RP (Return Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The return pointer stores the address for return from subroutines.
During execution of a CALL instruction, the PC value is transferred to this RP register.
During execution of a RET instruction, the contents of the RP register are transferred to PC.
The initial value at reset is undefined.
• USP (User Stack Pointer)
bit 31
bit 0
Initial value
XXXXXXXXH
The user stack pointer, when the S flag is “1”, this register functions as the R15 register.
• The USP register can also be explicitly specified.
The initial value at reset is undefined.
• This register cannot be used with RETI instructions.
• Multiply & divide registers
bit 31
bit 0
MDH
MDL
These registers are for multiplication and division, and are each 32 bits in length.
The initial value at reset is undefined.
24
MB91460R Series
■ MODE SETTING
In the FR family, the mode pins (MD2, MD1, MD0) and the mode register (MODR) are used to set the operating
mode.
1. Mode pins
The three pins MD2, MD1, MD0 are used to specify the mode vector fetch related settings.
Settings other than shown in the table are not allowed.
Mode pins*
Reset vector
Mode name
access area
MD2 MD1 MD0
0
0
0
Internal ROM mode vector
Internal
0
0
1
External ROM mode vector
External
Remarks
Bus width is set by mode register.
* : Always use MD3 with “0”.
Note : The FR family does not support the external mode vector fetch using multiplex bus.
2. Mode register (MODR)
The data written to the mode register using mode vector fetch is called mode data.
After the mode register (MODR) is set, the device operates according to the operation mode set in this register.
The mode register is set by all reset sources. User programs cannot write data to the mode register.
Rewriting is allowed in the emulator mode. In this case, use an 8-bit length data transfer instruction.
A 16/32-bit length transfer instruction cannot be used for writing.
Description of the mode register is given below.
[Mode register description]
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
0
0
0
0
ROMA
WTH1
WTH0
Initial value
XXXXXXXXB
Operation mode setting bits
[bit7 to bit3] Reserved bits
Be sure to set these bits to “00000B”.
Operation is not guaranteed when any value other than “00000B” is set.
[bit2] ROMA (Internal enable bit)
The ROMA bit is used to set whether to enable the internal F-bus RAM and F-bus ROM areas.
ROMA
Function
Remarks
0
External ROM mode
Internal F-bus RAM becomes valid. The internal ROM area
(40000H to FFFFFH) is used as an external area.
1
Internal ROM mode
Internal F-bus RAM and F-bus ROM become valid.
25
MB91460R Series
[bit1, bit0] WTH1, WTH0 (Bus width setting bits)
These bits are used to set the bus width to be used in the external bus mode.
When the operation mode is the external bus mode, these values are set in bits BW1 and BW0 in AMD0 (CS0
area).
WTH1
WTH0
Function
Remarks
26
0
0
8-bit bus width
External bus mode
0
1
16-bit bus width
External bus mode
1
0
⎯
Setting disabled
1
1
Single chip mode
Single chip mode
MB91460R Series
■ MEMORY SPACE
1. Memory space
The FR family has 4 Gbytes of logical address space (232 addresses) available to the CPU by linear access.
• Direct addressing area
The following address space area is used for I/O.
This area is called direct addressing area, and the address of an operand can be specified directly in an
instruction.
The size of directly addressable area depends on the length of the data being accessed as shown below.
Byte data access : 000H to 0FFH
Half word access : 000H to 1FFH
Word data access : 000H to 3FFH
2. Memory map
Internal ROM
external bus mode
0000 0000H
I/O
0000 0400H
External ROM
external bus mode
Direct addressing
area
0000 0000H
I/O
0000 0400H
I/O
0002 4000H
I/O
0002 4000H
D-bus RAM
(1 wait)
D-bus RAM
(1 wait)
0002 C000H
0003 0000H
Direct addressing
area
0002 C000H
D-bus RAM
(0 wait)
0003 0000H
F-bus RAM
D-bus RAM
(0 wait)
F-bus RAM
0003 4000H
0003 4000H
0004 0000H
0004 0000H
Flash memory
External area
0015 0000H
External area*
FFFF FFFFH
FFFF FFFFH
* : The region from 150000H may not be able to be used as an external region, depending on the CS
region setting.
27
MB91460R Series
■ I/O MAP
Address
000000H
Register
+0
+1
+2
+3
PDR0 [R/W]B
XXXXXXXX
PDR1 [R/W]B
XXXXXXXX
PDR2 [R/W]B
XXXXXXXX
PDR3 [R/W]B
XXXXXXXX
Block
T-unit
port data register
Read/write attribute, Access unit
(B: Byte, H: Half word, W: Word)
Register initial value after reset
Register name (column 1 register at address 4n, column 2 register at
address 4n + 1...)
Leftmost register address (for word access, the register in column 1
becomes the MSB side of the data.)
Note : Initial values of register bits are represented as follows:
“ 1 ” : Initial value “ 1 ”
“ 0 ” : Initial value “ 0 ”
“ X ” : Initial value “ undefined ”
“ - ” : No physical register at this location
“ * ” : The same value as value of WTH bit
Access is barred with an undefined data access attribute.
28
MB91460R Series
Address
Register
+0
+1
+2
+3
000000H
PDR00 [R/W]
B, H
XXXXXXXX
PDR01 [R/W]
B, H
XXXXXXXX
000004H
Reserved
PDR05 [R/W]
B, H
XXXXXXXX
PDR06 [R/W]
B, H
XXXXXXXX
PDR07 [R/W]
B, H
XXXXXXXX
000008H
PDR08 [R/W]
B, H
XXXX - - XX
PDR09 [R/W]
B, H
- - - XXXXX
PDR10 [R/W]
B, H
- XXXXXXX
PDR11 [R/W]
B, H
- - - - - - XX
00000CH
Reserved
PDR13 [R/W]
B, H
- - - - - XXX
PDR14 [R/W]
B, H
- - - - XXXX
PDR15 [R/W]
B, H
- - - - XXXX
Reserved
000010H
PDR16 [R/W]
B, H
X-------
PDR17 [R/W]
B, H
XXXXXXXX
PDR18 [R/W]
B, H
- - - - - XXX
PDR19 [R/W]
B, H
- XXX - XXX
000014H
PDR20 [R/W]
B, H
- XXX - XXX
PDR21 [R/W]
B, H
- XXX - XXX
PDR22 [R/W]
B, H
XXXXXX - X
PDR23 [R/W]
B, H
- X - XXXXX
000018H
PDR24 [R/W]
B, H
XXXXXXXX
00001CH
PDR28 [R/W]
B, H
XXXXXXXX
000020H
to
00002CH
Block
Port Data
Register
Reserved
PDR29 [R/W]
B, H
XXXXXXXX
Reserved
Reserved
Reserved
000030H
EIRR0 [R/W] B
00000000
ENIR0 [R/W] B
00000000
ELVR0 [R/W] B, H
00000000 00000000
External Interrupt
(INT 0 to INT 7)
NMI
000034H
EIRR1 [R/W] B
00000000
ENIR1 [R/W] B
00000000
ELVR1 [R/W] B, H
00000000 00000000
External Interrupt
(INT 8 to INT 15)
000038H
DICR [R/W] B
-------0
HRCL [R/W] B
0 - - 11111
Reserved
DLYI/I-unit
00003CH
000040H
000044H
Reserved
Reserved
SCR00 [R/W, W] SMR00 [R/W, W] SSR00 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR00 [R/W]
B, H
00000X00
ECCR00
[R/W, R, W] B, H
-00000XX
RDR00/TDR00
[R/W] B, H, W
00000000
LIN-USART 0
Reserved
(Continued)
29
MB91460R Series
Address
000048H
00004CH
000050H
000054H
000058H
00005CH
000060H
000064H
000068H
00006CH
Register
+0
+1
+2
+3
SCR01 [R/W, W] SMR01 [R/W, W] SSR01 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR01 [R/W]
B, H
00000X00
ECCR01
[R/W, R, W] B, H
-00000XX
ECCR02
[R/W, R, W] B, H
-00000XX
ECCR03
[R/W, R, W] B, H
-00000XX
ECCR04
[R/W, R, W] B, H
-00000XX
FSR04 [R] B, H
- - - 00000
SCR05 [R/W, W] SMR05 [R/W, W] SSR05 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR05 [R/W]
B, H
00000X00
ECCR05
[R/W, R, W] B, H
-00000XX
RDR03/TDR03
[R/W] B, H, W
00000000
FSR05 [R] B, H
- - - 00000
RDR04/TDR04
[R/W] B, H, W
00000000
FCR04 [R/W]
B, H
0001 - 000
RDR05/TDR05
[R/W] B, H, W
00000000
FCR05 [R/W]
B, H
0001 - 000
000070H
SCR06 [R/W, W] SMR06 [R/W, W] SSR06 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
RDR06/TDR06
[R/W] B, H, W
00000000
000074H
ECCR06
[R/W, R, W]
B, H
-00000XX
FCR06 [R/W]
B, H
0001 - 000
000078H,
00007CH
ESCR06 [R/W]
B, H
00000X00
LIN-USART 2
LIN-USART 3
Reserved
SCR04 [R/W, W] SMR04 [R/W, W] SSR04 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR04 [R/W]
B, H
00000X00
RDR02/TDR02
[R/W] B, H, W
00000000
Reserved
SCR03 [R/W, W] SMR03 [R/W, W] SSR03 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR03 [R/W]
B, H
00000X00
LIN-USART 1
Reserved
SCR02 [R/W, W] SMR02 [R/W, W] SSR02 [R/W, R]
B, H, W
B, H, W
B, H, W
00000000
00000000
00001000
ESCR02 [R/W]
B, H
00000X00
RDR01/TDR01
[R/W] B, H, W
00000000
Block
FSR06 [R] B, H
- - - 00000
Reserved
LIN-USART 4
(FIFO)
LIN-USART 5
(FIFO)
LIN-USART 6
(FIFO)
Reserved
(Continued)
30
MB91460R Series
Address
Register
+0
+1
+2
+3
000080H
BGR100 [R/W]
B, H, W
00000000
BGR000 [R/W]
B, H, W
00000000
BGR101 [R/W]
B, H, W
00000000
BGR001 [R/W]
B, H, W
00000000
000084H
BGR104 [R/W]
B, H, W
00000000
BGR004 [R/W]
B, H, W
00000000
BGR105 [R/W]
B, H, W
00000000
BGR005 [R/W]
B, H, W
00000000
000088H
BGR106 [R/W]
B, H, W
00000000
BGR006 [R/W]
B, H, W
00000000
BGR107 [R/W]
B, H, W
00000000
BGR007 [R/W]
B, H, W
00000000
00008CH
BGR102 [R/W]
B, H, W
00000000
BGR002 [R/W]
B, H, W
00000000
000090H
to
0000CCH
Baud rate
Generator
LIN-USART
0 to 6
Reserved
Reserved
Reserved
0000D0H
IBCR0 [R/W]
B, H
00000000
IBSR0 [R] B, H
00000000
ITBAH0 [R/W]
B, H
- - - - - - 00
ITBAL0 [R/W]
B, H
00000000
0000D4H
ITMKH0 [R/W]
B, H
00 - - - - 11
ITMKL0 [R/W]
B, H
11111111
ISMK0 [R/W]
B, H
01111111
ISBA0 [R/W] B, H
- 0000000
0000D8H
Reserved
IDAR0 [R/W]
B, H
00000000
ICCR0 [R/W] B
- 0011111
Reserved
0000DCH
IBCR1 [R/W]
B, H
00000000
IBSR1 [R] B, H
00000000
ITBAH1 [R/W]
B, H
- - - - - - 00
ITBAL1 [R/W]
B, H
00000000
0000E0H
ITMKH1 [R/W]
B, H
00 - - - - 11
ITMKL1 [R/W]
B, H
11111111
ISMK1 [R/W]
B, H
01111111
ISBA1 [R/W] B, H
- 0000000
0000E4H
Reserved
IDAR1 [R/W]
B, H
00000000
ICCR1 [R/W] B
- 0011111
Reserved
0000E8H
to
0000FCH
Block
Reserved
I2C 0
I2C 1
Reserved
000100H
GCN10 [R/W] B, H
00110010 00010000
Reserved
GCN20 [R/W] B
- - - - 0000
PPG Control
0 to 3
000104H
GCN11 [R/W] B, H
00110010 00010000
Reserved
GCN21 [R/W] B
- - - - 0000
PPG Control
4 to 7
000108H,
00010CH
Reserved
Reserved
(Continued)
31
MB91460R Series
Address
Register
+0
+1
000110H
PTMR00 [R] H
11111111 11111111
000114H
PDUT00 [W] H
XXXXXXXX XXXXXXXX
000118H
PTMR01 [R] H
11111111 11111111
00011CH
PDUT01 [W] H
XXXXXXXX XXXXXXXX
000120H
PTMR02 [R] H
11111111 11111111
000124H
PDUT02 [W] H
XXXXXXXX XXXXXXXX
000128H
PTMR03 [R] H
11111111 11111111
00012CH
PDUT03 [W] H
XXXXXXXX XXXXXXXX
000130H
PTMR04 [R] H
11111111 11111111
000134H
PDUT04 [W] H
XXXXXXXX XXXXXXXX
000138H
PTMR05 [R] H
11111111 11111111
00013CH
PDUT05 [W] H
XXXXXXXX XXXXXXXX
000140H
PTMR06 [R] H
11111111 11111111
000144H
PDUT06 [W] H
XXXXXXXX XXXXXXXX
000148H
PTMR07 [R] H
11111111 11111111
00014CH
PDUT07 [W] H
XXXXXXXX XXXXXXXX
+2
+3
Block
PCSR00 [W] H
XXXXXXXX XXXXXXXX
PCNH00 [R/W]
B, H
0000000 -
PCNL00 [R/W]
B, H
000000 - 0
PPG 0
PCSR01 [W] H
XXXXXXXX XXXXXXXX
PCNH01 [R/W]
B, H
0000000 -
PCNL01 [R/W
B, H]
000000 - 0
PPG 1
PCSR02 [W] H
XXXXXXXX XXXXXXXX
PCNH02 [R/W]
B, H
0000000 -
PCNL02 [R/W]
B, H
000000 - 0
PPG 2
PCSR03 [W] H
XXXXXXXX XXXXXXXX
PCNH03 [R/W]
B, H
0000000 -
PCNL03 [R/W]
B, H
000000 - 0
PPG 3
PCSR04 [W] H
XXXXXXXX XXXXXXXX
PCNH04 [R/W]
B, H
0000000 -
PCNL04 [R/W]
B, H
000000 - 0
PPG 4
PCSR05 [W] H
XXXXXXXX XXXXXXXX
PCNH05 [R/W]
B, H
0000000 -
PCNL05 [R/W]
B, H
000000 - 0
PPG 5
PCSR06 [W] H
XXXXXXXX XXXXXXXX
PCNH06 [R/W]
B, H
0000000 -
PCNL06 [R/W]
B, H
000000 - 0
PPG 6
PCSR07 [W] H
XXXXXXXX XXXXXXXX
PCNH07 [R/W]
B, H
0000000 -
PCNL07 [R/W]
B, H
000000 - 0
PPG 7
(Continued)
32
MB91460R Series
Address
Register
+0
+1
000170H
to
00017CH
000180H
+2
+3
Reserved
Reserved
ICS01 [R/W] B
00000000
Reserved
Reserved
ICS23 [R/W] B
00000000
000184H
IPCP0 [R] H
XXXXXXXX XXXXXXXX
IPCP1 [R] H
XXXXXXXX XXXXXXXX
000188H
IPCP2 [R] H
XXXXXXXX XXXXXXXX
IPCP3 [R] H
XXXXXXXX XXXXXXXX
00018CH
OCS01 [R/W] H
- - - 0 - - 00 0000 - - 00
OCS23 [R/W] H
- - - 0 - - 00 0000 - - 00
000190H
OCCP0 [R/W] H
XXXXXXXX XXXXXXXX
OCCP1 [R/W] H
XXXXXXXX XXXXXXXX
000194H
OCCP2 [R/W] H
XXXXXXXX XXXXXXXX
OCCP3 [R/W] H
XXXXXXXX XXXXXXXX
000198H,
00019CH
0001A0H
Reserved
ADERH [R/W] B, H, W
00000000 00000000
ADCS0 [R/W]
B, H
00000000
ADCR1 [R] B, H
000000XX
ADCR0 [R] B, H
XXXXXXXX
0001A8H
ADCT1 [R/W]
B, H
00010000
ADCT0 [R/W]
B, H
00101100
ADSCH [R/W]
B, H
- - - 00000
ADECH [R/W]
B, H
- - - 00000
0001ACH
Reserved
ACSR0 [R/W]
B, H
- 11XXX00
0001B4H
Reserved
0001B8H
TMRLR1 [W] H
XXXXXXXX XXXXXXXX
0001BCH
Reserved
Output
Compare
0 to 3
ADERL [R/W] B, H, W
00000000 00000000
ADCS1 [R/W]
B, H
00000000
TMRLR0 [W] H
XXXXXXXX XXXXXXXX
Input Capture
0 to 3
Reserved
0001A4
0001B0H
Block
Reserved
TMR0 [R] H
XXXXXXXX XXXXXXXX
TMCSRH0
[R/W] B, H
- - - 00000
TMCSRL0
[R/W] B, H
0 - 000000
TMR1 [R] H
XXXXXXXX XXXXXXXX
TMCSRH1
[R/W] B, H
- - - 00000
TMCSRL1
[R/W] B, H
0 - 000000
A/D
Converter
Alarm Comparator 0
Reload Timer 0
(PPG 0, PPG 1)
Reload Timer 1
(PPG 2, PPG 3)
(Continued)
33
MB91460R Series
Address
0001C0H
Register
+0
+1
TMRLR2 [W] H
XXXXXXXX XXXXXXXX
0001C4H
Reserved
0001C8H
TMRLR3 [W] H
XXXXXXXX XXXXXXXX
0001CCH
Reserved
0001D0H
to
0001E4H
0001E8H
+2
+3
TMR2 [R] H
XXXXXXXX XXXXXXXX
TMCSRH2
[R/W] B, H
- - - 00000
TMCSRL2
[R/W] B, H
0 - 000000
TMR3 [R] H
XXXXXXXX XXXXXXXX
TMCSRH3
[R/W] B, H
- - - 00000
TMCSRL3
[R/W] B, H
0 - 000000
Reserved
TMRLR7 [W] H
XXXXXXXX XXXXXXXX
Block
Reload Timer 2
(PPG 4, PPG 5)
Reload Timer 3
(PPG 6, PPG 7)
Reserved
TMR7 [R] H
XXXXXXXX XXXXXXXX
TMCSRL7
[R/W] B, H
0 - 000000
Reload Timer 7
(A/D converter)
0001ECH
Reserved
TMCSRH7
[R/W] B, H
- - - 00000
0001F0H
TCDT0 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS0 [R/W]
00000000
Free Running
Timer 0
(ICU 0, ICU 1)
0001F4H
TCDT1 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS1 [R/W]
00000000
Free Running
Timer 1
(ICU 2, ICU 3)
0001F8H
TCDT2 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS2 [R/W]
00000000
Free Running
Timer 2
(OCU 0, OCU 1)
0001FCH
TCDT3 [R/W] H
XXXXXXXX XXXXXXXX
Reserved
TCCS3 [R/W]
00000000
Free Running
Timer 3
(OCU 2, OCU 3)
000200H
DMACA0 [R/W] B, H, W *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000204H
DMACB0 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000208H
DMACA1 [R/W] B, H, W *
00000000 0000XXXX XXXXXXXX XXXXXXXX
00020CH
DMACB1 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000210H
DMACA2 [R/W] B, H, W *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000214H
DMACB2 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
DMAC
(Continued)
34
MB91460R Series
Address
Register
+0
+1
+2
+3
000218H
DMACA3 [R/W] B, H, W *
00000000 0000XXXX XXXXXXXX XXXXXXXX
00021CH
DMACB3 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000220H
DMACA4 [R/W] B, H, W *
00000000 0000XXXX XXXXXXXX XXXXXXXX
000224H
DMACB4 [R/W] B, H, W
00000000 00000000 XXXXXXXX XXXXXXXX
000228H
to
00023CH
Reserved
000240H
DMACR [R/W]
B, H, W
00 - - 0000
DMAC
Reserved
000244H
to
000364H
Reserved
Reserved
000368H
IBCR2 [R/W]
B, H
00000000
IBSR2 [R] B, H
00000000
ITBAH2 [R/W]
B, H
- - - - - - 00
ITBAL2 [R/W]
B, H
00000000
00036CH
ITMKH2 [R/W]
B, H
00 - - - - 11
ITMKL2 [R/W]
B, H
11111111
ISMK2 [R/W]
B, H
01111111
ISBA2 [R/W] B, H
- 0000000
000370H
Reserved
IDAR2 [R/W]
B, H
00000000
ICCR2 [R/W] B
- 0011111
Reserved
000374H
to
00038CH
000390H
Block
Reserved
ROMS [R]
11111111 00000000
I2C 2
Reserved
Reserved
000394H
to
0003ECH
Reserved
0003F0H
BSD0 [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F4H
BSD1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003F8H
BSDC [W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
0003FCH
BSRR [R] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
ROM Select Register
Reserved
Bit Search Module
(Continued)
35
MB91460R Series
Address
Register
+0
+1
000400H
to
00043CH
+2
+3
Reserved
Reserved
000440H
ICR00 [R/W]
B, H, W
---11111
ICR01 [R/W]
B, H, W
---11111
ICR02 [R/W]
B, H, W
---11111
ICR03 [R/W]
B, H, W
---11111
000444H
ICR04 [R/W]
B, H, W
---11111
ICR05 [R/W]
B, H, W
---11111
ICR06 [R/W]
B, H, W
---11111
ICR07 [R/W]
B, H, W
---11111
000448H
ICR08 [R/W]
B, H, W
---11111
ICR09 [R/W]
B, H, W
---11111
Reserved
ICR11 [R/W]
B, H, W
---11111
00044CH
ICR12 [R/W]
B, H, W
---11111
ICR13 [R/W]
B, H, W
---11111
000450H
ICR16 [R/W]
B, H, W
---11111
000454H
ICR20 [R/W]
B, H, W
---11111
ICR21 [R/W]
B, H, W
---11111
ICR22 [R/W]
B, H, W
---11111
ICR23 [R/W]
B, H, W
---11111
000458H
Reserved
ICR25 [R/W]
B, H, W
---11111
ICR26 [R/W]
B, H, W
---11111
ICR27 [R/W]
B, H, W
---11111
00045CH
Reserved
ICR29 [R/W]
B, H, W
---11111
ICR19 [R/W]
B, H, W
---11111
Reserved
Reserved
000464H
Reserved
ICR38 [R/W]
B, H, W
---11111
000468H
Reserved
ICR42 [R/W]
B, H, W
---11111
00046CH
000470H
ICR39 [R/W]
B, H, W
---11111
ICR43 [R/W]
B, H, W
---11111
Interrupt
Control
Reserved
ICR48 [R/W]
B, H, W
---11111
ICR49 [R/W]
B, H, W
---11111
000474H
000478H
Interrupt
Control
Unit
Reserved
Reserved
000460H
Block
ICR50 [R/W]
B, H, W
---11111
ICR51 [R/W]
B, H, W
---11111
Reserved
Reserved
ICR58 [R/W]
B, H, W
---11111
ICR59 [R/W]
B, H, W
---11111
(Continued)
36
MB91460R Series
Address
Register
+0
+1
+2
+3
00047CH
Reserved
ICR61 [R/W]
B, H, W
---11111
ICR62 [R/W]
B, H, W
---11111
ICR63 [R/W]
B, H, W
---11111
000480H
RSRR [R/W]
B, H, W
10000000
STCR [R/W]
B, H, W
00110011
TBCR [R/W]
B, H, W
00XXX - 00
CTBR [W]
B, H, W
XXXXXXXX
CLKR [R/W]
B, H, W
---- 0000
WPR [W]
B, H, W
XXXXXXXX
DIVR0 [R/W]
B, H, W
00000011
DIVR1 [R/W]
B, H, W
00000000
000484H
000488H
Reserved
PLLDIVM [R/W] PLLDIVN [R/W] PLLDIVG [R/W]
B, H
B, H
B, H
- - - 00000
- - - 00000
- - - 00000
000490H
PLLCTRL [R/W]
B, H
- - - - 0000
PLLDIVG [W]
B, H
00000000
Reserved
0004A4H
Reserved
0004A8H
WTHR [R/W]
B, H
- - - 00000
WTCER [R/W]
B, H
- - - - - - 00
WTCR [R/W] B, H
00000000 000 - 00 - 0
WTBR [R/W] B, B, H
- - - XXXXX XXXXXXXX XXXXXXXX
WTMR [R/W]
B, H
- - 000000
WTSR [R/W] B
- - 000000
Reserved
CSCFG [R/W]
0X000000
CMCFG [R/W]
00000000
Reserved
0004B0H
CUCR [R/W]
- - - - - - - - - - - 0 - - 00
CUTD [R/W]
10000000 00000000
0004B4H
CUTR1 [R]
- - - - - - - - 00000000
CUTR2 [R]
00000000 00000000
0004B8H
CMPR [R/W]
- - 000010 11111101
0004BCH
CMT1 [R/W]
00000000 1 - - - 0000
CANPRE [R/W]
B, H
0 - - - 0000
0004C4H
LVSEL [R/W]
00000111
PLL Interface
Reserved
0004ACH
0004C0H
Clock
Control
Reserved
000494H
to
00049CH
Reserved
Interrupt
Control
Reserved
00048CH
0004A0H
Block
Reserved
CMCR [R/W]
- 001 - - 00
CMT2 [R/W]
- - 000000 - - 000000
Reserved
LVDET [R/W]
0000 0 - 00
Reserved
Real Time Clock
Clock Monitor
Calibration of Sub Clock
Clock
Modulation
CAN (Clock Control)
Low Voltage Detection
(Continued)
37
MB91460R Series
Address
Register
+0
+1
+2
+3
0004C8H
OSCRH [R/W]
000 - - 001
OSCRL [R/W]
- - - - - 000
WPCRH [R/W]
00 - - - 000
WPCRL [R/W]
- - - - - - 00
0004CCH
OSCCR [R/W]
-------0
0004D4H
SHDE [R/W] B
0-------
0004D8H
EXTE [R/W] B, H EXTF [R/W] B, H
00000000
00000000
EXTLV [R/W] B, H
00000000 00000000
0004DCH
to
00063CH
Reserved
000640H
ASR0 [R/W] B, H, W
00000000 00000000
ACR0 [R/W] B, H, W
1111**00 00100000
000644H
ASR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000648H
ASR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
00064CH
ASR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000650H
ASR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
ACR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR0 [R/W] B, H, W
01001111 11111011
AWR1 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000664H
AWR2 [R/W] B, H, W
XXXXXXXX XXXXXXXX
AWR3 [R/W] B, H, W
XXXXXXXX XXXXXXXX
000668H
AWR4 [R/W] B, H, W
XXXXXXXX XXXXXXXX
Reserved
00066CH
00067CH
Reserved
Reserved
MCRA [R/W]
B, H, W
XXXXXXXX
000674H
000678H
External Bus
Unit
Reserved
000660H
000670H
Shutdown control
Reserved
Reserved
000654H
to
00065CH
Main-/Sub-Oscillation
Stabilization Wait Timer
Main- Oscillation
Standby Control
Reserved
Reserved
Block
MCRB [R/W]
B, H, W
XXXXXXXX
Reserved
Reserved
IORW0 [R/W]
B, H, W
XXXXXXXX
IORW1 [R/W]
B, H, W
XXXXXXXX
IORW2 [R/W]
B, H, W
XXXXXXXX
External Bus
Unit
Reserved
Reserved
(Continued)
38
MB91460R Series
Address
000680H
000684H
Register
+0
+1
+2
+3
CSER [R/W]
B, H, W
00000001
CHER [R/W]
B, H, W
11111111
Reserved
TCR [R/W]
B, H, W
00000000
RCRH [R/W]
B, H, W
00XXXXXX
RCRL [R/W]
B, H, W
XXXX0XXX
000688H
to
0007F8H
0007FCH
000800H
to
000BFCH
000D04H
000D08H
000D0CH
MODR [W] B
XXXXXXXX
Reserved
IOS [R/W]
00000000
Reserved
PDRD00 [R] B, H PDRD01 [R] B, H
XXXXXXXX
XXXXXXXX
Reserved
I-Unit
Reserved
Reserved
PDRD05 [R] B, H PDRD06 [R] B, H PDRD07 [R] B, H
XXXXXXXX
XXXXXXXX
XXXXXXXX
PDRD08 [R] B, H PDRD09 [R] B, H PDRD10 [R] B, H PDRD11 [R] B, H
XXXX - - XX
- - - XXXXX
- XXXXXXX
- - - - - - XX
Reserved
PDRD13 [R] B, H PDRD14 [R] B, H PDRD15 [R] B, H
- - - - - XXX
- - - - XXXX
- - - - XXXX
000D10H
PDRD16 [R] B, H PDRD17 [R] B, H PDRD18 [R] B, H PDRD19 [R] B, H
X------XXXXXXXX
- - - - - XXX
- XXX - XXX
000D14H
PDRD20 [R] B, H PDRD21 [R] B, H PDRD22 [R] B, H PDRD23 [R] B, H
- XXX - XXX
- XXX - XXX
XXXXXX - X
- X - XXXXX
000D18H
PDRD24 [R] B, H
XXXXXXXX
000D1CH
PDRD28 [R] B, H PDRD29 [R] B, H
XXXXXXXX
XXXXXXXX
000D20H
to
000D3CH
Mode Register
Reserved
Reserved
000C04H
to
000CFCH
000D00H
Reserved
Reserved
000C00H
External Bus
Unit
Reserved
Reserved
Reserved
Block
Port Data
Direct Read
Register
Reserved
Reserved
Reserved
Reserved
(Continued)
39
MB91460R Series
Address
Register
+0
+1
000D40H
DDR00 [R/W]
B, H
00000000
DDR01 [R/W]
B, H
00000000
000D44H
Reserved
DDR05 [R/W]
B, H
00000000
DDR06 [R/W]
B, H
00000000
DDR07 [R/W]
B, H
00000000
000D48H
DDR08 [R/W]
B, H
0000 - - 00
DDR09 [R/W]
B, H
- - - 00000
DDR10 [R/W]
B, H
- 0000000
DDR11 [R/W]
B, H
- - - - - - 00
000D4CH
Reserved
DDR13 [R/W]
B, H
- - - - - 000
DDR14 [R/W]
B, H
- - - - 0000
DDR15 [R/W]
B, H
- - - - 0000
000D50H
DDR16 [R/W]
B, H
0-------
DDR17 [R/W]
B, H
00000000
DDR18 [R/W]
B, H
- - - - - 000
DDR19 [R/W]
B, H
- 000 - 000
000D54H
DDR20 [R/W]
B, H
- 000 - 000
DDR21 [R/W]
B, H
- 000 - 000
DDR22 [R/W]
B, H
000000 - 0
DDR23 [R/W]
B, H
- 0 - 00000
000D58H
DDR24 [R/W]
B, H
00000000
000D5CH
DDR28 [R/W]
B, H
00000000
000D60H
to
000D7CH
+2
+3
Block
Reserved
Port Direction
Register
Reserved
DDR29 [R/W]
B, H
00000000
Reserved
Reserved
Reserved
(Continued)
40
MB91460R Series
Address
Register
+0
+1
000D80H
PFR00 [R/W]
B, H
11111111
PFR01 [R/W]
B, H
11111111
000D84H
Reserved
PFR05 [R/W]
B, H
11111111
PFR06 [R/W]
B, H
11111111
PFR07 [R/W]
B, H
11111111
000D88H
PFR08 [R/W]
B, H
1111 - - 11
PFR09 [R/W]
B, H
- - - 11111
PFR10 [R/W]
B, H
- 1111111
PFR11 [R/W]
B, H
- - - - - - 00
000D8CH
Reserved
PFR13 [R/W]
B, H
- - - - - 000
PFR14 [R/W]
B, H
- - - - 0000
PFR15 [R/W]
B, H
- - - - 0000
000D90H
PFR16 [R/W]
B, H
0-------
PFR17 [R/W]
B, H
00000000
PFR18 [R/W]
B, H
- - - - - 000
PFR19 [R/W]
B, H
- 000 - 000
000D94H
PFR20 [R/W]
B, H
- 000 - 000
PFR21 [R/W]
B, H
- 000 - 000
PFR22 [R/W]
B, H
000000 - 0
PFR23 [R/W]
B, H
- 0 - 00000
000D98H
PFR24 [R/W]
B, H
00000000
000D9CH
PFR28 [R/W]
B, H
00000000
+3
Reserved
PFR29 [R/W]
B, H
00000000
Port Function
Register
Reserved
Reserved
Reserved
Reserved
EPFR10 [R/W]
B, H
- - 00 - - - 0
Reserved
000DCCH
Reserved
EPFR13 [R/W]
B, H
-----0--
EPFR14 [R/W]
B, H
- - - - 0000
EPFR15 [R/W]
B, H
- - - - 0000
000DD0H
EPFR16 [R/W]
B, H
0-------
Reserved
EPFR18 [R/W]
B, H
-----0--
EPFR19 [R/W]
B, H
-0---0--
000DD4H
EPFR20 [R/W]
B, H
-0---0--
EPFR21 [R/W]
B, H
-0---0--
000DD8H,
000DDCH
Block
Reserved
000DA0H
to
000DC4H
000DC8H
+2
Extended Port
Function Register
Reserved
Reserved
(Continued)
41
MB91460R Series
Address
Register
+0
000DE0H
to
000DFCH
+1
+2
+3
Reserved
Reserved
000E00H
PODR00 [R/W]
B, H
00000000
PODR01 [R/W]
B, H
00000000
000E04H
Reserved
PODR05 [R/W]
B, H
00000000
PODR06 [R/W]
B, H
00000000
PODR07 [R/W]
B, H
00000000
000E08H
PODR08 [R/W]
B, H
0000 - - 00
PODR09 [R/W]
B, H
- - - 00000
PODR10 [R/W]
B, H
- 0000000
PODR11 [R/W]
B, H
- - - - - - 00
000E0CH
Reserved
PODR13 [R/W]
B, H
- - - - - 000
PODR14 [R/W]
B, H
- - - - 0000
PODR15 [R/W]
B, H
- - - - 0000
Reserved
000E10H
PODR16 [R/W]
B, H
0-------
PODR17 [R/W]
B, H
00000000
PODR18 [R/W]
B, H
- - - - - 000
PODR19 [R/W]
B, H
- 000 - 000
000E14H
PODR20 [R/W]
B, H
- 000 - 000
PODR21 [R/W]
B, H
- 000 - 000
PODR22 [R/W]
B, H
000000 - 0
PODR23 [R/W]
B, H
- 0 - 00000
000E18H
PODR24 [R/W]
B, H
00000000
000E1CH
PODR28 [R/W]
B, H
00000000
000E20H
to
000E3CH
Block
Port Output Select
Register
Reserved
PODR29 [R/W]
B, H
00000000
Reserved
Reserved
Reserved
(Continued)
42
MB91460R Series
Address
Register
+0
+1
+2
000E40H
PILR00 [R/W]
B, H
00000000
PILR01 [R/W]
B, H
00000000
000E44H
Reserved
PILR05 [R/W]
B, H
00000000
PILR06 [R/W]
B, H
00000000
PILR07 [R/W]
B, H
00000000
000E48H
PILR08 [R/W]
B, H
0000 - - 00
PILR09 [R/W]
B, H
- - - 00000
PILR10 [R/W]
B, H
- 0000000
PILR11 [R/W]
B, H
- - - - - - 00
000E4CH
Reserved
PILR13 [R/W]
B, H
- - - - - 000
PILR14 [R/W]
B, H
- - - - 0000
PILR15 [R/W]
B, H
- - - - 0000
000E50H
PILR16 [R/W]
B, H
0-------
PILR17 [R/W]
B, H
00000000
PILR18 [R/W]
B, H
- - - - - 000
PILR19 [R/W]
B, H
- 000 - 000
000E54H
PILR20 [R/W]
B, H
- 000 - 000
PILR21 [R/W]
B, H
- 000 - 000
PILR22 [R/W]
B, H
000000 - 0
PILR23 [R/W]
B, H
- 0 - 00000
000E58H
PILR24 [R/W]
B, H
00000000
000E5CH
PILR28 [R/W]
B, H
00000000
Block
Reserved
Input Level Select
Register
Reserved
PILR29 [R/W]
B, H
00000000
Reserved
000E60H
to
000E7CH
Reserved
000E80H
to
000E88H
Reserved
000E8CH
+3
Reserved
Reserved
EPILR14 [R/W]
B, H
- - - - 0000
EPILR15 [R/W]
B, H
- - - - 0000
000E90H
Reserved
EPILR17 [R/W]
B, H
- - - - 0000
EPILR18 [R/W]
B, H
000000 - 0
EPILR19 [R/W]
B, H
- 000 - 000
000E94H
EPILR20 [R/W]
B, H
- 000 - 000
EPILR21 [R/W]
B, H
- 000 - 000
EPILR22 [R/W]
B, H
000000 - 0
EPILR23 [R/W]
B, H
- 0 - 00000
000E98H
EPILR24 [R/W]
B, H
00 - - 0000
Port Input Level Select
Register
Reserved
(Continued)
43
MB91460R Series
Address
Register
+0
000E9CH
to
000EBCH
+1
+2
+3
Reserved
Reserved
000EC0H
PPER00 [R/W]
B, H
00000000
PPER01 [R/W]
B, H
00000000
000EC4H
Reserved
PPER05 [R/W]
B, H
00000000
PPER06 [R/W]
B, H
00000000
PPER07 [R/W]
B, H
00000000
000EC8H
PPER08 [R/W]
B, H
0000 - - 00
PPER09 [R/W]
B, H
- - - 00000
PPER10 [R/W]
B, H
- 0000000
PPER11 [R/W]
B, H
- - - - - - 00
000ECCH
Reserved
PPER13 [R/W]
B, H
- - - - - 000
PPER14 [R/W]
B, H
- - - - 0000
PPER15 [R/W]
B, H
- - - - 0000
Reserved
000ED0H
PPER16 [R/W]
B, H
0-------
PPER17 [R/W]
B, H
00000000
PPER18 [R/W]
B, H
- - - - - 000
PPER19 [R/W]
B, H
- 000 - 000
000ED4H
PPER20 [R/W]
B, H
- 000 - 000
PPER21 [R/W]
B, H
- 000 - 000
PPER22 [R/W]
B, H
- - - - 00 - 0
PPER23 [R/W]
B, H
- 0 - 00000
000ED8H
PPER24 [R/W]
B, H
00 - - 0000
000EDCH
PPER28 [R/W]
B, H
00000000
000EE0H
to
000EFCH
Block
Port Pull-Up/Pull-Down
Enable Register
Reserved
PPER29 [R/W]
B, H
00000000
Reserved
Reserved
Reserved
000F00H
PPCR00 [R/W]
B, H
11111111
PPCR01 [R/W]
B, H
11111111
000F04H
Reserved
PPCR05 [R/W]
B, H
11111111
PPCR06 [R/W]
B, H
11111111
PPCR07 [R/W]
B, H
11111111
000F08H
PPCR08 [R/W]
B, H
1111 - -11
PPCR09 [R/W]
B, H
- - - 11111
PPCR10 [R/W]
B, H
- 1111111
PPCR11 [R/W]
B, H
- - - - - -11
Reserved
Port Pull-Up/Pull-Down
Control Register
(Continued)
44
MB91460R Series
Address
Register
+0
+1
+2
+3
000F0CH
Reserved
PPCR13 [R/W]
B, H
- - - - - 111
PPCR14 [R/W]
B, H
- - - - 1111
PPCR15 [R/W]
B, H
- - - - 1111
000F10H
PPCR16 [R/W]
B, H
1-------
PPCR17 [R/W]
B, H
11111111
PPCR18 [R/W]
B, H
- - - - - 111
PPCR19 [R/W]
B, H
- 111 - 111
000F14H
PPCR20 [R/W]
B, H
- 111 - 111
PPCR21 [R/W]
B, H
- 111 - 111
PPCR22 [R/W]
B, H
111111 - 1
PPCR23 [R/W]
B, H
- 1 - 11111
000F18H
PPCR24 [R/W]
B, H
11 - - 1111
000F1CH
PPCR28 [R/W]
B, H
11111111
Block
Port Pull-Up/Pull-Down
Control Register
Reserved
PPCR29 [R/W]
B, H
11111111
Reserved
000F20H
to
000F3CH
Reserved
001000H
DMASA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001004H
DMADA0 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001008H
DMASA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00100CH
DMADA1 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001010H
DMASA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001014H
DMADA2 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001018H
DMASA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00101CH
DMADA3 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001020H
DMASA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001024H
DMADA4 [R/W] W
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
001028H
to
005FFCH
Reserved
Reserved
DMAC
Reserved
(Continued)
45
MB91460R Series
Address
Register
+0
+1
006000H
to
006FFCH
007000H
007004H
+2
+3
Reserved
FMCS [R/W]
01101000
FMCR [R]
- - - 00000
FMWT [R/W]
11111111 11111111
Block
Reserved
FCHCR [R/W]
- - - - - - 00 10000011
FMWT2 [R]
- 001 - - - -
FMPS [R/W]
- - - - - 000
Flash Memory/
Cache Control
Register
007008H
FMAC [R]
00000000 00000000 00000000 00000000
00700CH
FCHA0 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
007010H
FCHA1 [R/W]
- - - - - - - - - - - 00000 00000000 00000000
I-Cache
Non-cacheable
area setting
Register
007014H
to
00BFFCH
Reserved
Reserved
00C000H
CTRLR0 [R/W] B, H
00000000 00000001
STATR0 [R/W] B, H
00000000 00000000
00C004H
ERRCNT0 [R] B, H, W
00000000 00000000
BTR0 [R/W] B, H, W
00100011 00000001
00C008H
INTR0 [R] B, H, W
00000000 00000000
TESTR0 [R/W] B, H, W
00000000 X0000000
00C00CH
BRPE0 [R/W] B, H, W
00000000 00000000
Reserved
00C010H
IF1CREQ0 [R/W] B, H
00000000 00000001
IF1CMSK0 [R/W] B, H
00000000 00000000
00C014H
IF1MSK20 [R/W] B, H, W
11111111 11111111
IF1MSK10 [R/W] B, H, W
11111111 11111111
00C018H
IF1ARB20 [R/W] B, H, W
00000000 00000000
IF1ARB10 [R/W] B, H, W
00000000 00000000
00C01CH
IF1MCTR0 [R/W] B, H, W
00000000 00000000
Reserved
00C020H
IF1DTA10 [R/W] B, H, W
00000000 00000000
IF1DTA20 [R/W] B, H, W
00000000 00000000
00C024H
IF1DTB10 [R/W] B, H
00000000 00000000
IF1DTB20 [R/W] B, H
00000000 00000000
00C028H,
00C02CH
00C030H
CAN 0
Control
Register
CAN 0
IF 1 Register
Reserved
IF1DTA20 [R/W] B, H, W
00000000 00000000
IF1DTA10 [R/W] B, H, W
00000000 00000000
(Continued)
46
MB91460R Series
Address
00C034H
Register
+0
+1
+2
IF1DTB20 [R/W] B, H, W
00000000 00000000
00C038H,
00C03CH
+3
IF1DTB10 [R/W] B, H, W
00000000 00000000
Reserved
00C040H
IF2CREQ0 [R/W] B, H
00000000 00000001
IF2CMSK0 [R/W] B, H
00000000 00000000
00C044H
IF2MSK20 [R/W] B, H, W
11111111 11111111
IF2MSK10 [R/W] B, H, W
11111111 11111111
00C048H
IF2ARB20 [R/W] B, H, W
00000000 00000000
IF2ARB10 [R/W] B, H, W
00000000 00000000
00C04CH
IF2MCTR0 [R/W] B, H, W
00000000 00000000
Reserved
00C050H
IF2DTA10 [R/W] B, H, W
00000000 00000000
IF2DTA20 [R/W] B, H, W
00000000 00000000
00C054H
IF2DTB10 [R/W] B, H, W
00000000 00000000
IF2DTB20 [R/W] B, H, W
00000000 00000000
00C058H,
00C05CH
IF2DTA20 [R/W] B, H, W
00000000 00000000
IF2DTA10 [R/W] B, H, W
00000000 00000000
00C064H
IF2DTB20 [R/W] B, H, W
00000000 00000000
IF2DTB10 [R/W] B, H, W
00000000 00000000
00C068H
to
00C07CH
TREQR20 [R] B, H, W
00000000 00000000
TREQR10 [R] B, H, W
00000000 00000000
Reserved
NEWDT20 [R] B, H, W
00000000 00000000
00C094H
to
00C09CH
00C0A0H
CAN 0
IF 2 Register
Reserved
00C084H
to
00C08CH
00C090H
CAN 0
IF 1 Register
Reserved
00C060H
00C080H
Block
NEWDT10 [R] B, H, W
00000000 00000000
CAN 0
Status Flags
Reserved
INTPND20 [R] B, H, W
00000000 00000000
INTPND10 [R] B, H, W
00000000 00000000
(Continued)
47
MB91460R Series
Address
Register
+0
+1
00C0A4H
to
00C0ACH
00C0B0H
+2
+3
Reserved
MSGVAL20 [R] B, H, W
00000000 00000000
00C0B4H
to
00C0FCH
MSGVAL10 [R] B, H, W
00000000 00000000
Reserved
CTRLR1 [R/W] B, H
00000000 00000001
STATR1 [R/W] B, H
00000000 00000000
00C104H
ERRCNT1 [R] B, H, W
00000000 00000000
BTR1 [R/W] B, H, W
00100011 00000001
00C108H
INTR1 [R] B, H, W
00000000 00000000
TESTR1 [R/W] B, H, W
00000000 X0000000
00C10CH
BRPE1 [R/W] B, H, W
00000000 00000000
Reserved
00C110H
IF1CREQ1 [R/W] B, H
00000000 00000001
IF1CMSK1 [R/W] B, H
00000000 00000000
00C114H
IF1MSK21 [R/W] B, H, W
11111111 11111111
IF1MSK11 [R/W] B, H, W
11111111 11111111
00C118H
IF1ARB21 [R/W] B, H, W
00000000 00000000
IF1ARB11 [R/W] B, H, W
00000000 00000000
00C11CH
IF1MCTR1 [R/W] B, H, W
00000000 00000000
Reserved
00C120H
IF1DTA11 [R/W] B, H, W
00000000 00000000
IF1DTA21 [R/W] B, H, W
00000000 00000000
00C124H
IF1DTB11 [R/W] B, H, W
00000000 00000000
IF1DTB21 [R/W] B, H, W
00000000 00000000
CAN 1
Control
Register
CAN 1
IF 1 Register
Reserved
00C130H
IF1DTA21 [R/W] B, H, W
00000000 00000000
IF1DTA11 [R/W] B, H, W
00000000 00000000
00C134H
IF1DTB21 [R/W] B, H, W
00000000 00000000
IF1DTB11 [R/W] B, H, W
00000000 00000000
00C138H,
00C13CH
CAN 0
Status Flags
Reserved
00C100H
00C128H,
00C12CH
Block
Reserved
(Continued)
48
MB91460R Series
Address
Register
+0
+1
+2
+3
00C140H
IF2CREQ1 [R/W] B, H
00000000 00000001
IF2CMSK1 [R/W] B, H
00000000 00000000
00C144H
IF2MSK21 [R/W] B, H, W
11111111 11111111
IF2MSK11 [R/W] B, H, W
11111111 11111111
00C148H
IF2ARB21 [R/W] B, H, W
00000000 00000000
IF2ARB11 [R/W] B, H, W
00000000 00000000
00C14CH
IF2MCTR1 [R/W] B, H, W
00000000 00000000
Reserved
00C150H
IF2DTA11 [R/W] B, H, W
00000000 00000000
IF2DTA21 [R/W] B, H, W
00000000 00000000
00C154H
IF2DTB11 [R/W] B, H, W
00000000 00000000
IF2DTB21 [R/W] B, H, W
00000000 00000000
00C158H,
00C15CH
Block
CAN 1
IF 2 Register
Reserved
00C160H
IF2DTA21 [R/W] B, H, W
00000000 00000000
IF2DTA11 [R/W] B, H, W
00000000 00000000
00C164H
IF2DTB21 [R/W] B, H, W
00000000 00000000
IF2DTB11 [R/W] B, H, W
00000000 00000000
00C168H
to
00C17CH
Reserved
00C180H
TREQR21 [R] B, H, W
00000000 00000000
TREQR11 [R] B, H, W
00000000 00000000
00C184H
TREQR41 [R] B, H, W
00000000 00000000
TREQR31 [R] B, H, W
00000000 00000000
00C188H,
00C18CH
Reserved
00C190H
NEWDT21 [R] B, H, W
00000000 00000000
NEWDT11 [R] B, H, W
00000000 00000000
00C194H
NEWDT41 [R] B, H, W
00000000 00000000
NEWDT31 [R] B, H, W
00000000 00000000
00C198H,
00C19CH
CAN 1
Status Flags
Reserved
00C1A0H
INTPND21 [R] B, H, W
00000000 00000000
INTPND11 [R] B, H, W
00000000 00000000
00C1A4H
INTPND41 [R] B, H, W
00000000 00000000
INTPND31 [R] B, H, W
00000000 00000000
(Continued)
49
MB91460R Series
Address
Register
+0
+1
00C1A8H,
00C1ACH
+2
+3
Block
Reserved
00C1B0H
MSGVAL21 [R] B, H, W
00000000 00000000
MSGVAL11 [R] B, H, W
00000000 00000000
00C1B4H
MSGVAL41 [R] B, H, W
00000000 00000000
MSGVAL31 [R] B, H, W
00000000 00000000
00C1B8H
to
00EFFCH
Reserved
00F000H
BCTRL [R/W]
- - - - - - - - - - - - - - - - 11111100 00000000
00F004H
BSTAT [R/W]
- - - - - - - - - - - - - 000 00000000 10 - - 0000
00F008H
BIAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F00CH
BOAC [R]
- - - - - - - - - - - - - - - - 00000000 00000000
00F010H
BIRQ [R/W]
- - - - - - - - - - - - - - - - 00000000 00000000
CAN 1
Status Flags
EDSU / MPU
00F014H
to
00F01CH
Reserved
00F020H
BCR0 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F024H
BCR1 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F028H
BCR2 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F02CH
BCR3 [R/W]
- - - - - - - - 00000000 00000000 00000000
00F030H
to
00F07CH
Reserved
00F080H
BAD0 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F084H
BAD1 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F088H
BAD2 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
Reserved
EDSU / MPU
(Continued)
50
MB91460R Series
Address
Register
+0
+1
+2
+3
Block
00F08CH
BAD3 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F090H
BAD4 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F094H
BAD5 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F098H
BAD6 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F09CH
BAD7 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A0H
BAD8 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A4H
BAD9 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0A8H
BAD10 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0ACH
BAD11 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B0H
BAD12 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B4H
BAD13 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0B8H
BAD14 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0BCH
BAD15 [R/W]
XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX
00F0C0H
to
027FFCH
Reserved
Reserved
024000H
to
02BFFCH
D-RAM 32 Kbytes : 024000H to 02BFFCH
(data : 1 wait)
D-RAM
32 Kbytes
02C000H
to
02FFFCH
D-RAM 16 Kbytes : 02C000H to 02FFFCH
(data : 0 wait)
D-RAM
16 Kbytes
030000H
to
033FFCH
I-/D-RAM size is 16 Kbytes : 030000H to 033FFCH
(instruction : 0 wait, data : 1 wait)
I-/D-RAM
16 Kbytes
034000H
to
03FFFCH
Reserved
Reserved
EDSU / MPU
(Continued)
51
MB91460R Series
(Continued)
Address
Register
+0
+1
+2
040000H
to
05FFFCH
ROMS00 area (128 Kbytes)
060000H
to
07FFFCH
ROMS01 area (128 Kbytes)
080000H
to
09FFFCH
ROMS02 area (128 Kbytes)
0A0000H
to
0BFFFCH
ROMS03 area (128 Kbytes)
0C0000H
to
0DFFFCH
ROMS04 area (128 Kbytes)
0E0000H
to
0FFFF4H
ROMS05 area (128 Kbytes)
0FFFF8H
Mode Vector
0FFFFCH
Reset Vector
100000H
to
13FFFCH
ROMS06 area (256 Kbytes)
140000H
to
17FFFCH
ROMS07 area (256 Kbytes)
180000H
to
4FFFFCH
Reserved
Block
+3
Memory area
Reset/Mode Vector
Memory area
* : The lower 16 bits (DTC15 to DTC0) of DMACA0 to DMACA4 cannot be accessed in bytes.
52
Reserved
MB91460R Series
■ INTERRUPT VECTOR TABLE
Interrupt number
Interrupt
Interrupt level
Interrupt vector*1
RN
Decimal
Hexadecimal
Setting
Register
Register
address
Offset
Default Vector
address
Reset
0
00
⎯
⎯
3FCH
000FFFFCH
Mode vector
1
01
⎯
⎯
3F8H
000FFFF8H
System reserved
2
02
⎯
⎯
3F4H
000FFFF4H
System reserved
3
03
⎯
⎯
3F0H
000FFFF0H
System reserved
4
04
⎯
⎯
3ECH
000FFFECH
CPU supervisor mode
(INT #5 instruction)
5
05
⎯
⎯
3E8H
000FFFE8H
Memory Protection
exception
6
06
⎯
⎯
3E4H
000FFFE4H
System reserved
7
07
⎯
⎯
3E0H
000FFFE0H
System reserved
8
08
⎯
⎯
3DCH
000FFFDCH
INTE instruction
9
09
⎯
⎯
3D8H
000FFFD8H
System reserved
10
0A
⎯
⎯
3D4H
000FFFD4H
System reserved
11
0B
⎯
⎯
3D0H
000FFFD0H
System reserved
12
0C
⎯
⎯
3CCH
000FFFCCH
System reserved
13
0D
⎯
⎯
3C8H
000FFFC8H
Undefined instruction
exception
14
0E
⎯
⎯
3C4H
000FFFC4H
NMI request
15
0F
3C0H
000FFFC0H
External Interrupt 0
16
10
3BCH
000FFFBCH
0
External Interrupt 1
17
11
3B8H
000FFFB8H
1
External Interrupt 2
18
12
3B4H
000FFFB4H
2
External Interrupt 3
19
13
3B0H
000FFFB0H
3
External Interrupt 4
20
14
3ACH
000FFFACH
External Interrupt 5
21
15
3A8H
000FFFA8H
External Interrupt 6
22
16
3A4H
000FFFA4H
External Interrupt 7
23
17
3A0H
000FFFA0H
External Interrupt 8
24
18
39CH
000FFF9CH
External Interrupt 9
25
19
398H
000FFF98H
External Interrupt 10
26
1A
394H
000FFF94H
External Interrupt 11
27
1B
390H
000FFF90H
15 (FH) fixed
ICR00
440H
ICR01
441H
ICR02
442H
ICR03
443H
ICR04
444H
ICR05
445H
(Continued)
53
MB91460R Series
Interrupt number
Interrupt
Decimal
Hexadecimal
External Interrupt 12
28
1C
External Interrupt 13
29
1D
External Interrupt 14
30
1E
External Interrupt 15
31
1F
Reload Timer 0
32
20
Reload Timer 1
33
21
Reload Timer 2
34
22
Reload Timer 3
35
23
System reserved
36
24
System reserved
37
25
System reserved
38
26
Reload Timer 7
39
27
Free Run Timer 0
40
28
Free Run Timer 1
41
29
Free Run Timer 2
42
2A
Free Run Timer 3
43
2B
System reserved
44
2C
System reserved
45
2D
System reserved
46
2E
System reserved
47
2F
CAN 0
48
30
CAN 1
49
31
System reserved
50
32
System reserved
51
33
System reserved
52
34
System reserved
53
35
LIN-USART 0 RX
54
36
LIN-USART 0 TX
55
37
LIN-USART 1 RX
56
38
LIN-USART 1 TX
57
39
LIN-USART 2 RX
58
3A
LIN-USART 2 TX
59
3B
LIN-USART 3 RX
60
3C
LIN-USART 3 TX
61
3D
Interrupt level
Setting
Register
Register
address
ICR06
446H
ICR07
447H
ICR08
448H
ICR09
449H
ICR10
44AH
ICR11
44BH
ICR12
44CH
ICR13
44DH
ICR14
44EH
ICR15
44FH
ICR16
450H
ICR17
451H
ICR18
452H
ICR19
453H
ICR20
454H
ICR21
455H
ICR22
456H
Interrupt vector*1
RN
Offset
Default Vector
address
38CH
000FFF8CH
388H
000FFF88H
384H
000FFF84H
380H
000FFF80H
37CH
000FFF7CH
4
378H
000FFF78H
5
374H
000FFF74H
370H
000FFF70H
36CH
000FFF6CH
368H
000FFF68H
364H
000FFF64H
360H
000FFF60H
35CH
000FFF5CH
358H
000FFF58H
354H
000FFF54H
350H
000FFF50H
34CH
000FFF4CH
348H
000FFF48H
344H
000FFF44H
340H
000FFF40H
33CH
000FFF3CH
338H
000FFF38H
334H
000FFF34H
330H
000FFF30H
32CH
000FFF2CH
328H
000FFF28H
324H
000FFF24H
6
320H
000FFF20H
7
31CH
000FFF1CH
8
318H
000FFF18H
9
314H
000FFF14H
310H
000FFF10H
30CH
000FFF0CH
308H
000FFF08H
(Continued)
54
MB91460R Series
Interrupt number
Interrupt
Decimal
Hexadecimal
System reserved
62
3E
Delayed Interrupt
63
3F
System reserved*2
64
40
2
65
41
LIN-USART4 (FIFO) RX
66
42
LIN-USART4 (FIFO) TX
67
43
LIN-USART5 (FIFO) RX
68
44
LIN-USART5 (FIFO) TX
69
45
LIN-USART6 (FIFO) RX
70
46
LIN-USART6 (FIFO) TX
71
47
System reserved
72
48
System reserved
73
49
IC0/IC2
74
4A
I2C 1
75
4B
System reserved
76
4C
System reserved
77
4D
System reserved
78
4E
System reserved
79
4F
System reserved
80
50
System reserved
81
51
System reserved
82
52
System reserved
83
53
System reserved
84
54
System reserved
85
55
System reserved
86
56
System reserved
87
57
System reserved
88
58
System reserved
89
59
System reserved
90
5A
System reserved
91
5B
Input Capture 0
92
5C
Input Capture 1
93
5D
Input Capture 2
94
5E
Input Capture 3
95
5F
System reserved*
2
2
Interrupt level
Setting
Register
Register
address
ICR23*3
457H
(ICR24)
(458H)
ICR25
459H
ICR26
45AH
ICR27
45BH
ICR28
45CH
ICR29
45DH
ICR30
45EH
ICR31
45FH
ICR32
460H
ICR33
461H
ICR34
462H
ICR35
463H
ICR36
464H
ICR37
465H
ICR38
466H
ICR39
467H
Interrupt vector*1
RN
Offset
Default Vector
address
304H
000FFF04H
300H
000FFF00H
2FCH
000FFEFCH
2F8H
000FFEF8H
2F4H
000FFEF4H
10
2F0H
000FFEF0H
11
2ECH
000FFEECH
12
2E8H
000FFEE8H
13
2E4H
000FFEE4H
2E0H
000FFEE0H
2DCH
000FFEDCH
2D8H
000FFED8H
2D4H
000FFED4H
2D0H
000FFED0H
2CCH
000FFECCH
2C8H
000FFEC8H
2C4H
000FFEC4H
2C0H
000FFEC0H
2BCH
000FFEBCH
2B8H
000FFEB8H
2B4H
000FFEB4H
2B0H
000FFEB0H
2ACH
000FFEACH
2A8H
000FFEA8H
2A4H
000FFEA4H
2A0H
000FFEA0H
29CH
000FFE9CH
298H
000FFE98H
294H
000FFE94H
290H
000FFE90H
28CH
000FFE8CH
288H
000FFE88H
284H
000FFE84H
280H
000FFE80H
(Continued)
55
MB91460R Series
Interrupt number
Interrupt
Decimal
Hexadecimal
System reserved
96
60
System reserved
97
61
System reserved
98
62
System reserved
99
63
Output Compare 0
100
64
Output Compare 1
101
65
Output Compare 2
102
66
Output Compare 3
103
67
System reserved
104
68
System reserved
105
69
System reserved
106
6A
System reserved
107
6B
System reserved
108
6C
System reserved
109
6D
System reserved
110
6E
System reserved
111
6F
Prog. Pulse Gen. 0
112
70
Prog. Pulse Gen. 1
113
71
Prog. Pulse Gen. 2
114
72
Prog. Pulse Gen. 3
115
73
Prog. Pulse Gen. 4
116
74
Prog. Pulse Gen. 5
117
75
Prog. Pulse Gen. 6
118
76
Prog. Pulse Gen. 7
119
77
System reserved
120
78
System reserved
121
79
System reserved
122
7A
System reserved
123
7B
System reserved
124
7C
System reserved
125
7D
System reserved
126
7E
System reserved
127
7F
System reserved
128
80
System reserved
129
81
Interrupt level
Setting
Register
Register
address
ICR40
468H
ICR41
469H
ICR42
46AH
ICR43
46BH
ICR44
46CH
ICR45
46DH
ICR46
46EH
ICR47*3
46FH
ICR48
470H
ICR49
471H
ICR50
472H
ICR51
473H
ICR52
474H
ICR53
475H
ICR54
476H
ICR55
477H
ICR56
478H
Interrupt vector*1
Offset
Default Vector
address
27CH
000FFE7CH
278H
000FFE78H
274H
000FFE74H
270H
000FFE70H
26CH
000FFE6CH
268H
000FFE68H
264H
000FFE64H
260H
000FFE60H
25CH
000FFE5CH
258H
000FFE58H
254H
000FFE54H
250H
000FFE50H
24CH
000FFE4CH
248H
000FFE48H
244H
000FFE44H
240H
000FFE40H
23CH
000FFE3CH
238H
000FFE38H
234H
000FFE34H
230H
000FFE30H
22CH
000FFE2CH
228H
000FFE28H
224H
000FFE24H
220H
000FFE20H
21CH
000FFE1CH
218H
000FFE18H
214H
000FFE14H
210H
000FFE10H
20CH
000FFE0CH
208H
000FFE08H
204H
000FFE04H
200H
000FFE00H
1FCH
000FFDFCH
1F8H
000FFDF8H
RN
15
(Continued)
56
MB91460R Series
(Continued)
Interrupt number
Interrupt
Decimal
Hexadecimal
System reserved
130
82
System reserved
131
83
Real Time Clock
132
84
Calibration Unit
133
85
A/D Converter 0
134
86
System reserved
135
87
System reserved
136
88
System reserved
137
89
Low Voltage Detection
138
8A
System reserved
139
8B
Timebase Overflow
140
8C
PLL Clock Gear
141
8D
DMA Controller
142
8E
Main/Sub OSC stability wait
143
8F
System reserved
144
Used by the INT
instruction.
145
to
255
Interrupt level
Setting
Register
Register
address
ICR57
479H
ICR58
47AH
ICR59
47BH
ICR60
47CH
ICR61
47DH
ICR62
47EH
ICR63
47FH
90
⎯
91
to
FF
⎯
Interrupt vector*1
Offset
Default Vector
address
1F4H
000FFDF4H
1F0H
000FFDF0H
1ECH
000FFDECH
1E8H
000FFDE8H
1E4H
000FFDE4H
1E0H
000FFDE0H
1DCH
000FFDDCH
1D8H
000FFDD8H
1D4H
000FFDD4H
1D0H
000FFDD0H
1CCH
000FFDCCH
1C8H
000FFDC8H
1C4H
000FFDC4H
1C0H
000FFDC0H
⎯
1BCH
000FFDBC
⎯
1B8H to
000H
000FFDB8H
to
000FFC00H
RN
14
*1 : The vector address for each EIT (exception, interrupt or trap) is calculated by adding the listed offset to the
table base register value (TBR) . The TBR specifies the top address of the EIT vector table. The default vector
address are for the default TBR value (000FFC00H) . The TBR is initialized to this value by a reset.
*2 : Used by REALOS
*3 : ICR23 and ICR47 can be exchanged by setting the REALOS compatibility bit (addr 0C03 : IOS[0])
57
MB91460R Series
■ ELECTRICAL CHARACTERISTICS
1. Absolute maximum rating
Parameter
Symbol
Power supply voltage 1*1
Rating
Unit
Min
Max
VCC3
Vss − 0.5
Vss + 4.0
V
Remarks
VCC5
Vss − 0.5
Vss + 6.0
V
1
AVCC3
Vss − 0.5
Vss + 4.0
V
*2
1
AVRH
Vss − 0.5
Vss + 4.0
V
*2
VI1
Vss − 0.3
Vcc3 + 0.3
V
VI2
Vss − 0.3
Vcc5 + 0.3
V
Power supply voltage 2*1
Analog power supply voltage*
Analog power supply voltage*
Input voltage 1*1
Input voltage 2*1
VIA
Vss − 0.3
AVcc3 + 0.3
V
1
VO1
Vss − 0.3
Vcc3 + 0.3
V
Output voltage 2*1
VO2
Vss − 0.3
Vcc5 + 0.3
V
ICLAMP
− 2.0
+ 2.0
mA
*3
Σ |ICLAMP|
⎯
20
mA
*3
IOL
⎯
10
mA
*4
“L” level average output current
IOLAV
⎯
8
mA
*5
“L” level total maximum output current
ΣIOL
⎯
100
mA
ΣIOLAV
⎯
50
mA
*6
IOH
⎯
− 10
mA
*6
“H” level average output current
IOHAV
⎯
−4
mA
*5
“H” level total maximum output current
ΣIOH
⎯
− 50
mA
“H” level total average output current
ΣIOHAV
⎯
− 20
mA
Power consumption
PD
⎯
1000
mW
Operation ambient temperature
TA
− 40
+ 85
°C
Tstg
− 55
+ 125
°C
Analog pin input voltage*
Output voltage 1*
1
Maximum clamp current
Total maximum clamp current
“L” level maximum output current
“L” level total average output current
“H” level maximum output current
Storage temperature
*6
*1 : The parameter is based on VSS = AVSS = 0.0 V.
*2 : Be careful not to exceed “VCC + 0.3 V”, for example, when the power is turned on. Also, do not let
AVCC3 exceed VCC3.
*3 : •
•
•
•
Relevant pins : Pins that are used as I/O ports or that are shared as I/O ports
Use within recommended operating conditions.
Use at DC voltage (current).
The +B signal is an input signal exceeding VCC voltage. The +B signal should always be applied a limiting
resistance placed between the +B signal and the microcontroller.
• The value of the limiting resistance should be set so that when the +B signal is applied the input current to
the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods.
• Note that, when the microcontroller drive current is low as in low power consumption mode, the +B input
potential can increase the potential at the VCC pin via a protective diode, possibly affecting other devices.
• Note that, if the +B signal is input exists when the microcontroller is off (not fixed at 0 V) , power is supplied
through the pin, possibly causing the microcontroller to operate imperfectly.
(Continued)
58
MB91460R Series
(Continued)
• Note that, if the +B input exists when the power supply is turned on, power is supplied through the pin,
possibly resulting in a power-supply voltage at which a power-on reset does not work.
• Be careful not to let the +B input pin open.
• Example of recommended circuit :
• Input/output equivalent circuit
Protective diode
VCC
Limiting
resistor
P-ch
+B input (0 V to 16 V)
N-ch
R
*4 : The maximum output current is the peak value for a single pin.
*5 : The average output current is the average current for a single pin over a period of 100 ms.
*6 : The total average output current is the average current for all pins over a period of 100 ms.
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current,
temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
59
MB91460R Series
2. Recommended operating conditions
(VSS = AVSS = 0.0 V)
Parameter
Power supply voltage
Symbol
Value
Unit
Min
Typ
Max
VCC5
4.5
⎯
5.5
V
VCC3
3.0
⎯
3.6
V
AVCC3
3.0
⎯
3.6
V
Smoothing capacitor
CS
⎯
4.7
(accuracy
within ± 50%)
⎯
µF
Operating temperature
TA
− 40
⎯
+ 85
°C
Remarks
Use a ceramic capacitor or a
capacitor having the similar
frequency characteristic. For a
smoothing capacitor of VCC5
pin (VCC3 pin) , use one having a capacitance
value greater than CS.
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the
semiconductor device. All of the device’s electrical characteristics are warranted when the device is
operated within these ranges.
Always use semiconductor devices within their recommended operating condition ranges. Operation
outside these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representatives beforehand.
C_1
VSS
CS
60
C_2
AVSS
CS
MB91460R Series
3. DC characteristics
(VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V)
Parameter
“H” level
input voltage
“L” level
Symbol
Value
Min
Typ
Max
Unit Remarks
CMOS
hysteresis
input
⎯
0.8 × VCC
⎯
VCC + 0.3
V
VIH2
CMOS
hysteresis
input
⎯
0.7 × VCC
⎯
VCC + 0.3
V
VIH3
CMOS input
⎯
0.7 × VCC
⎯
VCC + 0.3
V
VIH4
Automotive
input
⎯
0.8 × VCC
⎯
VCC + 0.3
V
VIH5
I2C input
⎯
0.7 × VCC3
⎯
VCC5 + 0.3
V
VIL1
CMOS
hysteresis
input
⎯
VSS − 0.3
⎯
0.2 × VCC
V
VIL2
CMOS
hysteresis
input
⎯
VSS − 0.3
⎯
0.3 × VCC
V
VIL3
CMOS input
⎯
VSS − 0.3
⎯
0.3 × VCC
V
VIL4
Automotive
input
⎯
VSS − 0.3
⎯
0.5 × VCC
V
VIL5
I2C input
⎯
VSS − 0.3
⎯
0.3 × VCC3
V
VOH1
3.3 V, 5 V
switch pin
VCC = 5.0 V,
IOH = 5.0 mA/
VCC = 3.3 V,
IOH = 2.0 mA
VCC − 0.5
⎯
⎯
V
VOH2
3.3 V
dedicated pin
VCC3 = 3.3 V,
IOH = 4.0 mA
VCC3 − 0.5
⎯
⎯
V
VOL1
3.3 V, 5 V
switch pin
VCC = 5.0 V,
IOL = 5.0 mA/
VCC = 3.3 V,
IOL = 2.0 mA
⎯
⎯
0.4
V
VOL2
3.3 V
dedicated pin
VCC3 = 3.3 V,
IOL = 4.0 mA
⎯
⎯
0.4
V
VOL3
I2C pin
VCC3 = 3.3 V,
IOL = 3.0 mA
⎯
⎯
0.4
V
Input pin
VCC = AVCC = 5.0 V,
VSS < VI < VCC
−5
⎯
+5
µA
⎯
25
50
100
kΩ
output voltage
“L” level
output voltage
Condition
VIH1
input voltage
“H” level
Pin name
Input leak
current
IIL
Pull-up
resistance
value
RUP
INIT, pull-up pin
*2
*1
*2
*1
(Continued)
61
MB91460R Series
(Continued)
Parameter
Pull-down
resistance
value
(VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V)
Symbol
RDOWN
Pin name
INIT,
pull-up pin
Value
Typ
Max
⎯
25
50
100
kΩ
⎯
120
150
mA
Remarks
ICC3
VCC3
ICC5
VCC5
⎯
⎯
15
20
mA
ICCH
VCC3
+ 85 °C
⎯
1
3
mA
At stop
ICCH
VCC3
+ 85 °C
⎯
10
50
µA
At shutdown
CIN
Except VCC,
VSS,
AVCC3,
AVSS, AVRH
⎯
⎯
5
15
pF
*1 : Only 3.3 V pins and MD0 pin, MD1 pin and MD2 pin as I/O power supply
*2 : Including the INIT pin, MD3 pin, and NMI pin.
62
Unit
Min
CPU core : 80 MHz,
External bus :
40 MHz (no-load) ,
Peripheral macro :
10 MHz,
CAN : 20 MHz
Power supply
current
Input
capacitance
Condition
MB91460R Series
4. AC characteristics
(1) Clock timing
(VCC3 = 3.0 V to 3.6 V, VCC5 = 3.0 V to 5.5 V, VSS = AVSS = 0 V, TA = − 40 °C to + 85 °C)
Parameter
Symbol
Pin name
fC
Clock cycle time
Value
Unit
Remarks
Min
Typ
Max
X0
X1
3.4
⎯
4.2
tC
X0
X1
238
⎯
294
ns
Clock frequency
fCS
X0A
X1A
32
⎯
100
kHz
Clock cycle time
tCS
X0A
X1A
10
⎯
31.25
µs
fCP
0.032
⎯
80
MHz CPU
fCPP
0.032
⎯
20
MHz Peripheral
0.032
⎯
40
MHz External bus
fCAN
⎯
⎯
20
MHz
tCP
12.5
⎯
31250
ns
CPU
tCPP
50
⎯
31250
ns
Peripheral
25
⎯
31250
ns
External bus
50
⎯
⎯
ns
Clock after divided by
CAN prescaler
Clock frequency
Internal operation clock
frequency
Internal operation clock
cycle time
fCPT
tCPT
⎯
⎯
tCAN
MHz
Main clock
Sub clock
Clock after divided by
CAN prescaler
• Conditions for measuring the clock timing ratings
tC, tCS
Output pin
X0, X0A
X1, X1A
0.8 VCC
C = 50 pF
63
MB91460R Series
(2) Clock output timing
(VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = − 40 °C to + 85 °C)
Parameter
Value
Symbol Pin name Condition
Cycle time
tCYC
SYSCLK
SYSCLK↑→SYSCLK↓
tCHCL
SYSCLK
SYSCLK↓→SYSCLK↑
tCLCH
SYSCLK
⎯
Unit
Min
Max
tCPT
⎯
ns
12.5
108.5
ns
12.5
108.5
ns
Remarks
*
* : tCYC is the frequency of 1 clock cycle.
tCYC
tCHCL
tCLCH
VOH
VOH
VOL
SYSCLK
(3) Reset input ratings
(VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = − 40 °C to + 85 °C)
Parameter
INIT input time
(at power-on, at return from
shutdown mode)
Symbol
tINTL
Pin name
Condition
tINTL
64
Unit
Min
Max
8
⎯
ms
20
⎯
µs
⎯
INIT
INIT input time
(other than the above)
INIT
Value
0.2 VCC
MB91460R Series
(4) Normal bus access read/write operation
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
CS0 to CS4 setup
CS0 to CS4 hold
Address setup
Address hold
Valid address/valid data
input time
WR0, WR1 delay time
Symbol
Pin name
Condition
tCSLCH
tCSDLCH
SYSCLK
CS0 to CS4
tCHCSH
Value
Unit Remarks
Min
Max
3
⎯
ns
−3
⎯
ns
3
tCYC/2 + 6
ns
tASCH
SYSCLK
A23 to A00
3
⎯
ns
tASWL
WR0, WR1
A23 to A00
3
⎯
ns
tASRL
RD
A23 to A00
3
⎯
ns
tCHAX
SYSCLK
A23 to A00
3
tCYC/2 + 6
ns
tWHAX
WR0, WR1
A23 to A00
3
⎯
ns
tRHAX
RD
A23 to A00
3
⎯
ns
tAVDV
A23 to A00
D31 to D16
⎯
3/2 × tCYC − 15
ns
⎯
6
ns
⎯
6
ns
tCHWL
tCHWH
SYSCLK
WR0, WR1
⎯
Data setup time
(WRn rising)
tDSWH
D31 to D16
WR0, WR1
tCYC − 3
⎯
ns
Data hold time
(WRn rising)
tWHDX
D31 to D16
WR0, WR1
3
⎯
ns
WR0, WR1 minimum pulse
width
tWLWH
WR0, WR1
tCYC − 3
⎯
ns
tCHRL
SYSCLK
RD
⎯
6
ns
⎯
6
ns
RD delay time
tCHRH
Data setup time (RD rising)
tDSRH
D31 to D16
RD
20
⎯
ns
Data hold time (RD rising)
tRHDX
D31 to D16
RD
0
⎯
ns
RD minimum pulse width
tRLRH
RD
tCYC − 3
⎯
ns
AS setup time
tASLCH
3
⎯
ns
AS hold time
tCHASH
SYSCLK
AS
3
tCYC/2 + 6
ns
*
* : When the bus timing is delayed by automatic wait insertion or RDY input, add the time (tCYC × the number of
cycles added for the delay) to this rating.
65
MB91460R Series
tCYC
VOH
VOH
VOH
VOH
SYSCLK
tASLCH
tCHASH
AS
VOH
VOL
tCHCSH
tCSLCH
CS0 to CS4
VOH
VOL
tCHAX
tASCH
A23 to A00
VOH
VOL
VOH
VOL
tCHRH
tCHRL
tRLRH
RD
VOH
VOL
tASRL
tRHAX
tDSRH
tRHDX
tAVDV
VIH
Read
D31 to D16
VIL
VIH
VIL
tCHWH
tCHWL
tWLWH
VOH
VOL
WR0, WR1
tWHAX
tASWL
tWHDX
tDSWH
D31 to D16
66
VOH
VOL
Write
VOH
VOL
MB91460R Series
(5) Ready input timing
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
RDY setup time
→ SYSCLK↓
tRDYS
SYSCLK
RDY
SYSCLK↑
→ RDY hold time
tRDYH
SYSCLK
RDY
Value
Condition
Unit
Min
Max
10
⎯
ns
0
⎯
ns
⎯
tCYC
VOH
SYSCLK
VOH
VOL
VOL
tRDYS tRDYH
When RDY
wait is
applied
When RDY
wait is not
applied
tRDYS tRDYH
VOH
VOH
VOL
VOL
VOH
VOH
VOL
VOL
67
MB91460R Series
(6) Hold timing
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
tCHBGL
tCHBGH
SYSCLK
BGRNT
BGRNT rising from pin floating
tXHAL
⎯
BGRNT rising from pin valid
tHAHV
BGRNT
BGRNT delay time
Condition
⎯
Value
Max
⎯
10
ns
3
10
ns
tCYC − 10
tCYC + 10
ns
tCYC − 10
tCYC + 10
ns
Note : After a BRQ is captured, a minimum of 1 cycle is required before BGRNT changes.
tCYC
SYSCLK
VOH
VOH
VOH
VOH
BRQ
tCHBGL
BGRNT
tCHBGH
VOL
tXHAL
High impedance
68
VOH
tHAHV
Each pin
Unit
Min
MB91460R Series
(7) LIN-UART timing
(VCC3 = 3.0 V to 3.6 V, VCC5 = 4.5 V to 5.5 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Symbol
Pin name
Serial clock cycle time
tSCYC
SCK↓ → SOT delay time
Condition
Value
Unit
Min
Max
SCK0 to SCK6
5tCYCP
⎯
ns
tSLOV
SCK0 to SCK6,
SOT0 to SOT6
− 50
+ 50
ns
Valid SIN → SCK↑
tIVSH
SCK0 to SCK6,
SIN0 to SIN6
tCYCP + 80
⎯
ns
SCK↑ → valid SIN hold time
tSHIX
SCK0 to SCK6,
SIN0 to SIN6
0
⎯
ns
Serial clock “H” pulse width
tSHSL
SCK0 to SCK6
tCYCP + 10
⎯
ns
Serial clock “L” pulse width
tSLSH
SCK0 to SCK6
3tCYCP
⎯
ns
SCK↓ → SOT delay time
tSLOV
SCK0 to SCK6,
SOT0 to SOT6
⎯
150
ns
Valid SIN → SCK↑
tIVSH
SCK0 to SCK6,
SIN0 to SIN6
30
⎯
ns
SCK↑ → valid SIN hold time
tSHIX
SCK0 to SCK6,
SIN0 to SIN6
tCYCP + 30
⎯
ns
SCK rising time
tF
SCK0 to SCK6
⎯
10
ns
SCK falling time
tR
SCK0 to SCK6
⎯
10
ns
Internal shift
clock mode
External
shift clock
mode
Notes : • Above values are AC characteristics for CLK synchronous mode.
• tCYCP is the cycle time of the peripheral clock.
69
MB91460R Series
• Internal shift clock mode
tSCYC
SCK0 to SCK6
VOH
VOL
VOL
tSLOV
VOH
VOL
SOT0 to SOT6
tIVSH
tSHIX
VOH
VOL
SIN0 to SIN6
VOH
VOL
• External shift clock mode
tSLSH
SCK0 to SCK6
tSHSL
VOL
VOL
VOH
VOL
tSLOV
SOT0 to SOT6
VOH
VOL
tIVSH
SIN0 to SIN6
70
VOH
VOL
tSHIX
VOH
VOL
MB91460R Series
(8) DMA controller timing
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
DREQ0 input pulse
DACK0 delay time
DEOP0 delay time
IORD delay time
IOWR delay time
Symbol
Pin name
tDRWH
DREQ0
tCLDL
Value
Condition
DACK0
tCLDH
tCLEL
DEOP0
tCLEH
tCHIRL
⎯
IORD
tCHIRH
tCHIWL
IOWR
tCHIWH
Unit
Min
Max
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
⎯
10
ns
tCYC
SYSCLK
VOH
VOH
VOH
tCLDL
DACK0
VOH
tCLDH
VOH
VOL
tCLEL
tCLEH
VOH
DEOP0
VOL
tCHIRL
IORD
tCHIRH
VOH
VOL
tCHIWL
IOWR
tCHIWH
VOL
VOH
tDRWH
DREQ0
VOL
VOH
71
MB91460R Series
(9) Free-run timer clock
(VCC3 = 3.0 V to 3.6 V, VCC5 = 4.0 V to 5.5 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Input pulse width
Symbol
Pin name
Condition
tTIWH,
tTIWL
FRCK0 to FRCK3
⎯
Value
Min
Max
4tCYCP
⎯
Unit
ns
Note : tCYCP is the cycle time of the peripheral clock.
FRCK0 to FRCK3
tTIWH
tTIWL
(10) Trigger input timing
(VCC3 = 3.0 V to 3.6 V, VCC5 = 4.0 V to 5.5 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Input capture input trigger
A/D converter trigger
Symbol
Pin name
Condition
tINP
ICU0 to ICU3
tATGX
ATG
Note : tCYCP is the cycle time of the peripheral clock.
tATGX, tINP
ICU0 to ICU3,
ATG
72
Value
Unit
Min
Max
⎯
5tCYCP
⎯
ns
⎯
5tCYCP
⎯
ns
MB91460R Series
5. Electrical characteristics for A/D converter
(VCC3 = 3.0 V to 3.6 V, Vss = AVss = 0 V, TA = −40 °C to + 85 °C)
Parameter
Resolution
1
Total error*
Linearity error*
1
Differential linearity
error*1
Zero transition voltage*1
Full transition voltage*
1
Symbol
Pin name
⎯
Value
Unit
Min
Typ
Max
⎯
⎯
⎯
10
bit
⎯
⎯
⎯
⎯
±3
LSB
⎯
⎯
⎯
⎯
±2.5
LSB
⎯
⎯
⎯
⎯
±1.9
LSB
VOT
AN0 to AN15
VFST
AN0 to AN15 AVRH−3.5
AVRH−1.5 AVRH + 0.5 LSB
⎯
⎯
µs
⎯
⎯
10
µA
AN0 to AN15
AVSS
⎯
AVRH
V
AVRH
AVSS
⎯
AVCC3
V
⎯
1.5
2.5
mA
⎯
⎯
10
µA
⎯
⎯
1*
Analog port input
current
IAIN
AN0 to AN15
Analog input voltage
VAIN
Reference voltage
⎯
Analog power supply
current
(analog + digital)
IA
IAH*3
At AVcc3 = 3.3 V,
AVRH = 3.3 V
AVRL−1.5 AVRL + 0.5 AVRL + 2.5 LSB
Conversion time
AVCC3
Remarks
2
Analog input equivalent
capacity
Cin
AN0 to AN15
⎯
⎯
14.7
pF
Analog input equivalent
resistance
Rin
AN0 to AN15
⎯
⎯
1.9
kΩ
Output impedance of
analog signal source
Rext
⎯
⎯
⎯
1.9
kΩ
Including
reference
supply
*1 : Standard value in the CPU sleep state
*2 : Set the peripheral clock and conversion time setting register to set a time equal to or longer than this time.
*3 : The current when A/D converter is not operating, or in the CPU stop mode (at VCC3 = AVCC3 = AVRH = 3.3 V).
73
MB91460R Series
(2) Cautions Relating to the A/D Converter
The diagram below shows the equivalent circuit of the sampling circuit in the A/D converter.
The output impedance of the external circuit connected to the analog input must satisfy the following criteria.
• The recommended output impedance for the external circuit is 1.9 kΩ or less.
• If an external capacitor is used, remember to consider the capacitive voltage divider effect due to the external
capacitor and the internal capacitor in the chip. Accordingly, an external capacitance several thousand times
that of the internal capacitance is recommended.
• The analog voltage sampling period may be too short if the output impedance of the external circuit is high.
In this case, select Rext and Tsamp such that they satisfy the following condition.
Rext = Tsamp/ (7 × Cin) − Rin
Rext
Tsamp
Cin
Rin
: Output impedance of the analog signal source
: Sampling time
: Equivalent capacitance of analog input
: Equivalent resistance of analog input
• Input impedance
Analog
signal source
Rext
Analog
input pin
Rin:1.9 kΩ (Max)
Analog SW
Cin:14.7 pF (Max)
Device internal circuit
74
A/D converter
MB91460R Series
Definition of A/D converter terms
• Resolution
Analog variation that is recognizable by an A/D converter.
• Linearity error
Deviation between actual conversion characteristics and a straight line connecting zero transition point
(“00 0000 0000B” ↔ “00 0000 0001B”) and full scale transition point (“11 1111 1110B ”↔ “11 1111 1111B”).
• Differential linearity error
Deviation of input voltage, which is required for changing output code by 1 LSB, from an ideal value.
• Total error
This error indicates the difference between actual and theoretical values, including the zero transition error/
full scale transition error/linearity error.
Linearity error
3FFH
Differential linearity error
Actual conversion characteristics
Actual conversion characteristics
3FEH
(N+1)H
{1 LSB' (N − 1) + VOT}
VFST
(measurement value)
004H
Digital output
Digital output
3FDH
VNT
(measurement value)
003H
Ideal
characteristics
NH
(N-1)H
V (N+1) T
Actual conversion
characteristics
002H
VNT
(measurement value)
Ideal characteristics
(N-2)H
001H
Actual conversion
characteristics
VOT (measurement value)
AVSS
AVRH
Analog input
Linearity error of digital output N =
(measurement value)
AVSS
AVRH
Analog input
VNT − {1LSB’ × (N − 1) + VOT} [LSB]
1LSB’
Differential linearity error of digital output N = V (N + 1) T − VNT [LSB]
1LSB’
1LSB =
N
VOT
VFST
VNT
VFST − VOT
1022
[V]
: A/D converter digital output value
: A voltage at which digital output transits from (000) H to (001) H
: A voltage at which digital output transits from (3FE) H to (3FF) H
: A voltage at which digital output transitions from (N−1) Hto NH
(Continued)
75
MB91460R Series
(Continued)
Total error
3FFH
Digital output
3FEH
3FDH
1.5 LSB'
Actual conversion
characteristics
{1 LSB'
(N − 1) + 0.5 LSB'}
004H
VNT
(measurement value)
003H
Actual conversion
characteristics
002H
Ideal characteristics
001H
0.5 LSB'
AVSS
AVRH
Analog input
1LSB' (ideal value) = AVRH − AVSS
1024
[V]
Total error of digital output N = VNT − {1 LSB' × (N − 1) + 0.5 LSB'}
1 LSB'
N : A/D converter digital output value
VNT : A voltage at which digital output transits from (N + 1) H to NH
VOT' (ideal value) = AVSS + 0.5 LSB' [V]
VFST' (ideal value) = AVRH − 1.5 LSB' [V]
76
MB91460R Series
■ ORDERING INFORMATION
Part number
MB91F467RPMC-GSE1
Package
176-pin plastic LQFP
(FPT-176P-M07)
Remarks
Lead-free package
77
MB91460R Series
■ PACKAGE DIMENSION
176-pin plastic LQFP
Lead pitch
0.50 mm
Package width ×
package length
24.0 × 24.0 mm
Lead shape
Gullwing
Sealing method
Plastic mold
Mounting height
1.70 mm MAX
Code
(Reference)
P-LQFP-0176-2424-0.50
(FPT-176P-M07)
176-pin plastic LQFP
(FPT-176P-M07)
Note 1) * : Values do not include resin protrusion.
Resin protrusion is +0.25(.010)Max(each side).
Note 2) Pins width and pins thickness include plating thickness
Note 3) Pins width do not include tie bar cutting remainder.
26.00±0.20(1.024±.008)SQ
*24.00±0.10(.945±.004)SQ
0.145±0.055
(.006±.002)
132
89
133
88
0.08(.003)
Details of "A" part
+0.20
1.50 –0.10
+.008
(Mounting height)
.059 –.004
0˚~8˚
0.10±0.10
(.004±.004)
(Stand off)
INDEX
176
45
"A"
LEAD No.
1
44
0.50(.020)
C
0.22±0.05
(.009±.002)
0.08(.003)
0.25(.010)
M
2004 FUJITSU LIMITED F176013S-c-1-1
Please confirm the latest Package dimension by following URL.
http://edevice.fujitsu.com/fj/DATASHEET/ef-ovpklv.html
78
0.50±0.20
(.020±.008)
0.60±0.15
(.024±.006)
Dimensions in mm (inches).
Note: The values in parentheses are reference values.
MB91460R Series
The information for microcontroller supports is shown in the following homepage.
http://www.fujitsu.com/global/services/microelectronics/product/micom/support/index.html
FUJITSU LIMITED
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The contents of this document are subject to change without notice.
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representatives before ordering.
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circuit examples, in this document are presented solely for the
purpose of reference to show examples of operations and uses of
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operation of the device with respect to use based on such
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device based on such information, you must assume any
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function and schematic diagrams, shall not be construed as license
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