MC100E210 5VECL Dual 1:4, 1:5 Differential Fanout Buffer The MC100E210 is a low voltage, low skew dual differential ECL fanout buffer designed with clock distribution in mind. The device features two fanout buffers, a 1:4 and a 1:5 buffer, on a single chip. The device features fully differential clock paths to minimize both device and system skew. The dual buffer allows for the fanout of two signals through a single chip, thus reducing the skew between the two fundamental signals from a part−to−part skew down to an output−to−output skew. This capability reduces the skew by a factor of 4 as compared to using two LVE111’s to accomplish the same task. The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10−20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10−20 pS increase in TPD, so the relative skew between any two output pairs remains about 25 nS. For more information on using PECL, designers should refer to Application Note AN1406/D. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 F capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. • Dual Differential Fanout Buffers • 200 ps Part−to−Part Skew • 50 ps Typical Output−to−Output Skew • Low Voltage ECL/PECL Compatible • The 100 Series Contains Temperature Compensation • 28−lead PLCC Packaging • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V with VEE = 0 V • NECL Mode Operating Range: VCC = 0 V with VEE = −4.2 V to −5.7 V • Internal Input 75 K Pulldown Resistors • Q Output will Default LOW with Inputs Open or at VEE • ESD Protection: Human Body Model; >2 KV, Machine Model; >200 V • Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test • Moisture Sensitivity Level 1 For Additional Information, see Application Note AND8003/D • Flammability Rating: UL 94 V−0 @ 0.125 in, Oxygen Index: 28 to 34 • Transistor Count = 179 devices Semiconductor Components Industries, LLC, 2003 October, 2003 − Rev. 2 1 http://onsemi.com MARKING DIAGRAM 1 28 MC100E210FN AWLYYWW PLCC−28 FN SUFFIX CASE 776 A WL YY WW = Assembly Location = Wafer Lot = Year = Work Week *For additional information, see Application Note AND8002/D ORDERING INFORMATION Package Shipping† MC100E210FN PLCC−28 37 Units / Rail MC100E210FNR2 PLCC−28 500 Tape & Reel Device †For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. Publication Order Number: MC100E210/D MC100E210 LOGIC DIAGRAM AND PINOUT ASSIGNMENT Qa0 Qa0 Qa1 VCCO Qa1 Qa2 Qa2 25 24 23 22 21 20 19 VEE 26 18 Qa3 VBB 27 17 Qa3 CLKa 28 16 Qb0 15 VCCO VCC 28−Lead PLCC (Top View) 1 CLKa 2 14 Qb0 CLKb 3 13 Qb1 CLKb 4 12 Qb1 LOGIC SYMBOL Qa0 Qa0 CLKa Qa1 CLKa Qa1 Qa2 Qa2 Qa3 5 6 7 8 9 10 Qa3 11 Qb0 Qb4 Qb4 Qb3 VCCO Qb3 Qb2 Qb2 Qb0 Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. CLKb Qb1 CLKb Qb1 Qb2 PIN DESCRIPTION PIN FUNCTION CLKa, CLKb CLKa, CLKb Qa0:3, Qb0:4 Qa0:3, Qb0:4 VBB VCC, VCCO VEE ECL Differential Input Pairs ECL Differential Input Pairs ECL Differential Outputs ECL Differential Outputs Reference Output Voltage Positive Supply Negative Supply Qb2 Qb3 Qb3 Qb4 Qb4 VBB MAXIMUM RATINGS (Note 1) Symbol Parameter Condition 1 Condition 2 Rating Unit VCC PECL Mode Power Supply VEE = 0 V 8 V VEE NECL Mode Power Supply VCC = 0 V −8 V VI PECL Mode Input Voltage NECL Mode Input Voltage VEE = 0 V VCC = 0 V 6 −6 V V Iout Output Current Continuous Surge 50 100 mA mA IBB VBB Sink/Source ± 0.5 mA TA Operating Temperature Range 0 to +85 °C Tstg Storage Temperature Range −65 to +150 °C JA Thermal Resistance (Junction−to−Ambient) 0 LFPM 500 LFPM 28 PLCC 28 PLCC 63.5 43.5 °C/W °C/W JC Thermal Resistance (Junction−to−Case) Standard Board 28 PLCC 22 to 26 °C/W VEE PECL Operating Range NECL Operating Range 4.2 to 5.7 −5.7 to −4.2 V V Tsol Wave Solder 265 °C <2 to 3 sec @ 248°C 1. Maximum Ratings are those values beyond which device damage may occur. http://onsemi.com 2 VI VCC VI VEE MC100E210 PECL DC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V (Note 2) −40°C Symbol Characteristic Min 25°C Typ Max Min Typ 55 85°C Max Min Typ 55 Max Unit 65 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 3) 3915 3995 4120 3975 4050 4120 3975 4050 4120 mV VOL Output LOW Voltage (Note 3) 3170 3305 3445 3190 3255 3380 3190 3260 3380 mV VIH Input HIGH Voltage (Single−Ended) 3835 3975 4120 3835 3975 4120 3835 3975 4120 mV VIL Input LOW Voltage (Single−Ended) 3190 3355 3525 3190 3355 3525 3190 3355 3525 mV VBB Output Voltage Reference 3.62 3.74 3.62 3.74 3.62 3.74 V VIHCMR Input HIGH Voltage Common Mode Range (Differential) (Note 4) 2.7 4.6 2.7 4.6 2.7 4.6 V IIH Input HIGH Current 150 A IIL Input LOW Current 150 0.5 0.3 150 0.5 0.25 0.5 A 0.2 NOTE: Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 2. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 3. Outputs are terminated through a 50 resistor to VCC − 2 volts. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. NECL DC CHARACTERISTICS VCCx= 0.0 V; VEE= −5.0 V (Note 5) −40°C Symbol Characteristic Min Typ 25°C Max Min Typ 55 85°C Max Min Typ 55 Max Unit 65 mA IEE Power Supply Current VOH Output HIGH Voltage (Note 6) −1085 −1005 −880 −1025 −950 −880 −1025 −950 −880 mV VOL Output LOW Voltage (Note 6) −1830 −1695 −1555 −1810 −1745 −1620 −1810 −1740 −1620 mV VIH Input HIGH Voltage (Single−Ended) −1165 −1025 −880 −1165 −1025 −880 −1165 −1025 −880 mV VIL Input LOW Voltage (Single−Ended) −1810 −1645 −1475 −1810 −1645 −1475 −1810 −1645 −1475 mV VBB Output Voltage Reference −1.38 −1.26 −1.38 −1.26 −1.38 −1.26 V VIHCMR Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 7) −2.3 −0.4 −2.3 −0.4 −2.3 −0.4 V IIH Input HIGH Current 150 A IIL Input LOW Current 150 0.5 0.3 NOTE: 150 0.5 0.25 0.5 0.2 A Devices are designed to meet the DC specifications shown in the above table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 lfpm is maintained. 5. Input and output parameters vary 1:1 with VCC. VEE can vary −0.46 V / +0.8 V. 6. Outputs are terminated through a 50 resistor to VCC − 2 volts. 7. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. http://onsemi.com 3 MC100E210 AC CHARACTERISTICS VCCx= 5.0 V; VEE= 0.0 V or VCCx= 0.0 V; VEE= −5.0 V (Note 8) −40°C Symbol Characteristic Min Typ fMAX Maximum Toggle Frequency tPLH tPHL Propagation Delay to Output IN (differential) (Note 9) IN (single−ended) (Note 10) tskew Within−Device Skew Qa to Qb Qa to Qa,Qb to Qb Part−to−Part Skew (Differential) (Note 11) 50 50 tJITTER Random Clock Jitter (RMS) <1 VPP Input Voltage Swing (Differential Configuration) (Note 12) 500 tr / tf Output Rise/Fall Time (20%−80%) 200 25°C Max Min 700 Typ 85°C Max Min 700 Typ Max 700 Unit MHz ps 475 400 675 700 500 450 75 75 200 700 750 50 30 500 450 75 50 200 50 30 <1 200 75 50 200 <1 500 600 700 750 ps 500 600 200 ps mV 600 ps 8. VEE can vary −0.46 V / +0.8 V. 9. The differential propagation delay is defined as the delay from the crossing points of the differential input signals to the crossing point of the differential output signals. 10. The single-ended propagation delay is defined as the delay from the 50% point of the input signal to the 50% point of the output signal. 11. The within−device skew is defined as the worst case difference between any two similar delay paths within a single device. 12. VPP(min) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. The VPP(min) is AC limited for the E210 as a differential input as low as 50 mV will still produce full ECL levels at the output. http://onsemi.com 4 MC100E210 Q D Receiver Device Driver Device Q D 50 50 V TT VTT = VCC − 2.0 V Figure 1. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020 − Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 − ECLinPS Circuit Performance at Non−Standard VIH Levels AN1405 − ECL Clock Distribution Techniques AN1406 − Designing with PECL (ECL at +5.0 V) AN1503 − ECLinPS I/O SPICE Modeling Kit AN1504 − Metastability and the ECLinPS Family AN1568 − Interfacing Between LVDS and ECL AN1596 − ECLinPS Lite Translator ELT Family SPICE I/O Model Kit AN1650 − Using Wire−OR Ties in ECLinPS Designs AN1672 − The ECL Translator Guide AND8001 − Odd Number Counters Design AND8002 − Marking and Date Codes AND8020 − Termination of ECL Logic Devices http://onsemi.com 5 MC100E210 PACKAGE DIMENSIONS PLCC−28 FN SUFFIX PLASTIC PLCC PACKAGE CASE 776−02 ISSUE E 0.007 (0.180) B Y BRK -N- T L −M M M 0.007 (0.180) U S N T L −M S S N S D Z -L- -M- D W X V 28 1 G1 0.010 (0.250) S T L −M S N S VIEW D-D Z C A 0.007 (0.180) R 0.007 (0.180) M M T L −M S T L −M S N S N S H M 0.007 (0.180) T L −M N S K1 E 0.004 (0.100) G J S K SEATING PLANE F VIEW S G1 0.010 (0.250) -T- T L −M S N 0.007 (0.180) VIEW S S NOTES: 1. DATUMS -L-, -M-, AND -N- DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIM G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIM R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.250) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635). DIM A B C E F G H J K R U V W X Y Z G1 K1 http://onsemi.com 6 INCHES MIN MAX 0.485 0.495 0.485 0.495 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 0.025 0.450 0.456 0.450 0.456 0.042 0.048 0.042 0.048 0.042 0.056 0.020 10° 2° 0.410 0.430 0.040 MILLIMETERS MIN MAX 12.32 12.57 12.32 12.57 4.57 4.20 2.79 2.29 0.48 0.33 1.27 BSC 0.81 0.66 0.51 0.64 11.58 11.43 11.58 11.43 1.21 1.07 1.21 1.07 1.42 1.07 0.50 10° 2° 10.42 10.92 1.02 M T L −M S N S S MC100E210 Notes http://onsemi.com 7 MC100E210 ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. 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