SEMICONDUCTOR TECHNICAL DATA The MC10181 is a high–speed arithmetic logic unit capable of performing 16 logic operations and 16 arithmetic operations on two four–bit words. Full internal carry is incorporated for ripple through operation. Arithmetic logic operations are selected by applying the appropriate binary word to the select inputs (S0 through S3) as indicated in the tables of arithmetic/logic functions. Group carry propagate (PG) and carry generate (GG) are provided to allow fast operations on very long words using a second order look ahead. The internal carry is enabled by applying a low level voltage to the mode control input (M). L SUFFIX CERAMIC PACKAGE CASE 623–05 PD = 600 mW typ/pkg (No Load) tpd (typ): A1 to F = 6.5 ns Cn to Cn + 4 = 3.1 ns A1 to PG = 5.0 ns A1 to GG = 4.5 ns A1 to Cn + 4 = 5.0 PIN ASSIGNMENT LOGIC DIAGRAM 13 15 17 14 VCC1 = PIN 1 VCC2 = PIN 24 VEE = PIN 12 S0 S1 S2 S3 21 20 18 19 16 11 10 9 22 23 A0 B0 A1 B1 A2 B2 A3 B3 Cn M S3 S2 S1 S0 Logic Functions M is High C = D.C. F L L L L L L L L H H H H H H H H L L L L H H H H L L L L H H H H L L H H L L H H L L H H L L H H L H L H L H L H L H L H L H L H F=A F=A+B F=A+B F = Logical “1” F=A•B F=B F=A B F=A+B F=A•B F=A B F=B F=A+B F = Logical “0” F=A•B F=A•B F=A Function Select 1 24 VCC2 F0 2 23 M F1 3 22 CN GG 4 21 A0 CN + 4 5 20 B0 F3 6 19 B1 F0 2 F1 3 F2 7 F3 6 F2 7 18 A1 GG 4 PG 8 17 S1 PG 8 B3 9 16 A2 Cn+4 5 A3 10 15 S2 B2 11 14 S0 VEE 12 13 S3 Arithmetic Operation M is Low Cn is low F F=A F = A plus (A • B) F = A plus (A • B) F = A times 2 F = (A + B) plus 0 F = (A + B) plus (A • B) F = A plus B F = A plus (A + B) F = (A + B) plus 0 F = A minus B minus 1 F = (A + B) plus (A • B) F = A plus (A + B) F = minus 1 (two’s complement) F = (A • B) minus 1 F = (A • B) minus 1 F = A minus 1 9/96 Motorola, Inc. 1996 VCC1 3–141 REV 6 MC10181 S3 13 POSITIVE LOGIC DIAGRAM S2 15 S1 17 S0 14 2 F0 B0 20 A0 21 3 F1 B1 19 A1 18 7 F2 B2 11 A2 16 6 F3 B3 9 8 PG A3 10 4 GG 5 Cn+4 Cn 22 M 23 MOTOROLA 3–142 MECL Data DL122 — Rev 6 MC10181 ELECTRICAL CHARACTERISTICS Test Limits Symbol Pin Pi Under Test IE 12 159 Input Current IinH 9 10 11 13 14 15 16 17 18 19 20 21 22 23 390 350 390 320 425 425 350 425 350 390 390 350 460 320 Input Leakage Current IinL 9 10 11 13 14 15 16 17 18 19 20 21 22 23 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Characteristic Power Supply Drain Current –30°C Min +25°C Max Min Typ +85°C Max Unit 145 159 mAdc 245 220 245 200 265 265 220 265 220 245 245 220 290 200 245 220 245 200 265 265 220 265 220 245 245 220 290 200 µAdc Max 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 Min µAdc 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 0.3 Output Voltage Logic 1 VOH * –1.060 –0.890 –0.960 –0.810 –0.890 –0.700 Vdc Output Voltage Logic 0 VOL * –2.000 –1.675 –1.990 –1.650 –1.920 –1.615 Vdc Threshold Voltage Logic 1 VOHA * –1.080 –0.980 Threshold Voltage Logic 0 VOLA * –1.655 * Test all input–output combinations according to Function Table. ** For threshold level test, apply threshold input level to only one input pin at a time. MECL Data DL122 — Rev 6 3–143 –0.910 –1.630 Vdc –1.595 Vdc MOTOROLA MC10181 ELECTRICAL CHARACTERISTICS (continued) TEST VOLTAGE VALUES (Volts) @ Test Temperature VIHmax VILmin VIHAmin VILAmax VEE –30°C –0.890 –1.890 –1.205 –1.500 –5.2 +25°C –0.810 –1.850 –1.105 –1.475 –5.2 +85°C –0.700 –1.825 –1.035 –1.440 –5.2 Symbol Pin Under Test IE 12 Input Current IinH 9 10 11 13 14 15 16 17 18 19 20 21 22 23 Input Leakage Current IinL 9 10 11 13 14 15 16 17 18 19 20 21 22 23 VOH * Characteristic Power Supply Drain Current Output Voltage Logic 1 Output Voltage Logic 0 VOL * Threshold Voltage Logic 1 VOHA * TEST VOLTAGE APPLIED TO PINS LISTED BELOW VEE (VCC) Gnd 12 1, 24 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 9 10 11 13 14 15 16 17 18 19 20 21 22 23 12 12 12 12 12 12 12 12 12 12 12 12 12 12 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 1, 24 * * 12 1, 24 * * VIHmax VILmin VIHAmin VILAmax 9 10 11 13 14 15 16 17 18 19 20 21 22 23 Threshold Voltage Logic 0 VOLA * * Test all input–output combinations according to Function Table. ** For threshold level test, apply threshold input level to only one input pin at a time. 12 1, 24 ** ** 12 1, 24 ** ** 12 1, 24 Each MECL 10,000 series circuit has been designed to meet the dc specifications shown in the test table, after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse air flow greater than 500 linear fpm is maintained. Outputs are terminated through a 50–ohm resistor to –2.0 volts. Test procedures are shown for only one gate. The other gates are tested in the same manner. MOTOROLA 3–144 MECL Data DL122 — Rev 6 MC10181 AC Switching Characteristics –30°C * +25°C +85°C * Symbol Input Output Conditions† Min Max Min Typ Max Min Max Unit Propagation Delay Rise Time, Fall Time t++,t– – t+,t– Cn Cn Cn+4 Cn+4 A0,A1,A2,A3 A0,A1,A2,A3 1.0 1.0 5.1 3.2 1.1 1.0 3.1 2.0 5.0 3.0 1.1 1.0 5.4 3.2 ns ns Propagation Delay t++,t+– t–+,t– – t+,t– Cn Cn Cn F1 F1 F1 A0 A0 A0 1.7 1.7 1.3 7.2 7.2 5.3 2.0 2.0 1.5 4.5 4.5 3.0 7.0 7.0 5.0 2.0 2.0 1.5 7.5 7.5 5.3 ns ns ns Rise Time, Fall Time t++,t+– t–+,t– – t+,t– A1 A1 A1 F1 F1 F1 — — — 2.6 2.6 1.3 10.4 10.4 5.4 3.0 3.0 1.5 6.5 6.5 3.0 10 10 5.0 3.0 3.0 1.5 10.8 10.8 5.3 ns ns ns Propagation Delay Rise Time, Fall Time t++,t– – t+,t– A1 A1 PG PG S0,S3 S0,S3 1.6 0.8 7.0 3.7 2.0 1.1 5.0 2.0 6.5 3.5 2.0 1.1 7.0 3.8 ns ns Propagation Delay Rise Time, Fall Time t++,t– – t+,t– A1 A1 GG GG A0,A2,A3,Cn A0,A2,A3,Cn 1.1 1.2 7.4 5.1 2.0 1.5 4.5 4.0 7.0 5.0 1.3 1.2 7.7 5.3 ns ns Propagation Delay Rise Time, Fall Time t+–,t–+ t+,t– A1 A1 Cn+4 Cn+4 A0,A2,A3,Cn A0,A2,A3,Cn 1.7 1.0 7.3 3.1 2.0 1.0 5.0 2.0 7.0 3.0 2.0 1.0 7.8 3.2 ns ns Propagation Delay Rise Time, Fall Time t++,t–+ t+,t– B1 B1 F1 F1 S3,Cn S3,Cn 2.7 1.2 11.3 5.3 3.0 1.5 8.0 3.5 11 5.0 3.0 1.5 11.9 5.3 ns ns Propagation Delay Rise Time, Fall Time t++,t– – t+,t– B1 B1 PG PG S0,A1 S0,A1 1.6 1.0 7.7 3.6 2.0 1.1 6.0 2.0 7.5 3.5 2.0 1.1 8.0 3.9 ns ns Propagation Delay Rise Time, Fall Time t++,t– – t+,t– B1 B1 GG GG S3,Cn S3,Cn 1.7 1.4 8.2 5.2 2.0 1.5 6.0 3.0 8.0 5.0 2.0 1.2 8.6 5.4 ns ns Propagation Delay Rise Time, Fall Time t+–,t–+ t+,t– B1 B1 Cn+4 Cn+4 S3,Cn S3,Cn 1.8 0.9 8.2 3.1 2.0 1.0 6.0 2.0 8.0 3.0 2.0 1.0 8.7 3.2 ns ns Propagation Delay Rise Time, Fall Time t++,t+– t+,t– M M F1 F1 — — 2.4 1.1 10.3 5.1 3.0 1.5 6.5 4.0 10 5.0 3.0 1.5 10.8 5.3 ns ns Propagation Delay Rise Time, Fall Time t+–,t–+ t+,t– S1 S1 F1 F1 A1,B1 A1,B1 2.5 1.0 10.7 5.4 3.0 1.5 6.5 3.0 10 5.0 3.0 1.5 10.8 5.4 ns ns Propagation Delay Rise Time, Fall Time t–+,t+– t+,t– S1 S1 PG PG A3,B3 A3,B3 1.7 0.8 8.3 5.1 2.0 1.1 6.0 3.0 8.0 5.0 2.0 1.1 8.4 5.2 ns ns Propagation Delay Rise Time, Fall Time t+–,t–+ t+,t– S1 S1 Cn+4 Cn+4 A3,B3 A3,B3 1.6 0.9 9.3 5.3 2.0 1.1 6.0 3.0 9.0 5.0 2.0 1.0 9.9 5.2 ns ns Propagation Delay Rise Time, Fall Time t+–,t–+ t+,t– S1 S1 GG GG A3,B3 A3,B3 1.5 0.8 9.6 6.2 2.0 0.8 6.0 3.0 9.0 6.0 1.9 0.8 9.7 6.5 ns ns Characteristic Rise Time, Fall Time Propagation Delay † Logic high level (+1.11 Vdc) applied to pins listed. All other input pins are left floating or tied to +0.31 Vdc. VCC1 = VCC2 = +2.0 Vdc, VEE = –3.2 Vdc MECL Data DL122 — Rev 6 * L Suffix Only 3–145 MOTOROLA MC10181 OUTLINE DIMENSIONS L SUFFIX CERAMIC PACKAGE CASE 623–05 ISSUE M 24 NOTES: 1. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 2. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION (WHEN FORMED PARALLEL). 13 B 1 12 DIM A B C D F G J K L M N A F C SEATING PLANE L G N D K MILLIMETERS MIN MAX 31.24 32.77 12.70 15.49 4.06 5.59 0.41 0.51 1.27 1.52 2.54 BSC 0.20 0.30 3.18 4.06 15.24 BSC 0_ 15 _ 0.51 1.27 INCHES MIN MAX 1.230 1.290 0.500 0.610 0.160 0.220 0.016 0.020 0.050 0.060 0.100 BSC 0.008 0.012 0.125 0.160 0.600 BSC 0_ 15_ 0.020 0.050 J M Motorola reserves the right to make changes without further notice to any products herein. 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