MC14521B
24-Stage Frequency Divider
The MC14521B consists of a chain of 24 flip–flops with an input
circuit that allows three modes of operation. The input will function as
a crystal oscillator, an RC oscillator, or as an input buffer for an
external oscillator. Each flip–flop divides the frequency of the
previous flip–flop by two, consequently this part will count up to 224 =
16,777,216. The count advances on the negative going edge of the
clock. The outputs of the last seven–stages are available for added
flexibility.
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MARKING
DIAGRAMS
• All Stages are Resettable
• Reset Disables the RC Oscillator for Low Standby Power Drain
• RC and Crystal Oscillator Outputs Are Capable of Driving External
•
•
•
•
16
PDIP–16
P SUFFIX
CASE 648
Loads
Test Mode to Reduce Test Time
VDD′ and VSS′ Pins Brought Out on Crystal Oscillator Inverter to
Allow the Connection of External Resistors for Low–Power
Operation
Supply Voltage Range = 3.0 Vdc to 18 Vdc
Capable of Driving Two Low–power TTL Loads or One Low–power
Schottky TTL Load over the Rated Temperature Range.
1
16
SOIC–16
D SUFFIX
CASE 751B
VDD
Vin, Vout
Iin, Iout
PD
Parameter
16
SOEIAJ–16
F SUFFIX
CASE 966
Unit
– 0.5 to +18.0
V
– 0.5 to VDD + 0.5
V
Input or Output Current
(DC or Transient) per Pin
± 10
mA
Power Dissipation,
per Package (Note 3.)
500
mW
Input or Output Voltage Range
(DC or Transient)
TA
Ambient Temperature Range
– 55 to +125
°C
Tstg
Storage Temperature Range
– 65 to +150
°C
TL
Lead Temperature
(8–Second Soldering)
260
°C
2. Maximum Ratings are those values beyond which damage to the device
may occur.
3. Temperature Derating:
Plastic “P and D/DW” Packages: – 7.0 mW/_C From 65_C To 125_C
This device contains protection circuitry to guard against damage due to high
static voltages or electric fields. However, precautions must be taken to avoid
applications of any voltage higher than maximum rated voltages to this
high–impedance circuit. For proper operation, Vin and Vout should be constrained
(Vin or Vout)
VDD.
to the range VSS
Unused inputs must always be tied to an appropriate logic voltage level (e.g.,
either VSS or VDD). Unused outputs must be left open.
v
A
= Assembly Location
WL or L = Wafer Lot
YY or Y = Year
WW or W = Work Week
ORDERING INFORMATION
Device
Package
Shipping
MC14521BCP
PDIP–16
2000/Box
MC14521BD
SOIC–16
48/Rail
MC14521BDR2
SOIC–16
2500/Tape & Reel
MC14521BF
SOEIAJ–16
See Note 1.
MC14521BFEL
SOEIAJ–16
See Note 1.
MC14521BFR2
SOEIAJ–16
See Note 1.
1. For ordering information on the EIAJ version of
the SOIC packages, please contact your local
ON Semiconductor representative.
v
Semiconductor Components Industries, LLC, 2000
March, 2000 – Rev. 3
MC14521B
AWLYWW
1
Value
DC Supply Voltage Range
14521B
AWLYWW
1
MAXIMUM RATINGS (Voltages Referenced to VSS) (Note 2.)
Symbol
MC14521BCP
AWLYYWW
1
Publication Order Number:
MC14521B/D
MC14521B
PIN ASSIGNMENT
VDD
Q24
1
16
RESET
2
15
Q23
VSS′
3
14
Q22
OUT 2
4
13
Q21
VDD′
5
12
Q20
IN 2
6
11
Q19
7
10
Q18
8
9
IN 1
VSS
BLOCK DIAGRAM
RESET
2
9
IN 1
STAGES
1 THRU 17
6
IN 2
7
OUT 1
5
VDD′
3
VSS′
4
OUT2
STAGES
18 THRU 24
Q18 Q19 Q20 Q21 Q22 Q23 Q24
VDD = PIN 16
VSS = PIN 8
10
11
12
13
14
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2
15
1
Output
Count Capacity
Q18
Q19
Q20
Q21
Q22
Q23
Q24
218 = 262,144
219 = 524,288
220 = 1,048,576
221 = 2,097,152
222 = 4,194,304
223 = 8,388,608
224 = 16,777,216
MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ELECTRICAL CHARACTERISTICS (Voltages Referenced to VSS)
Characteristic
Symbol
Output Voltage
Vin = VDD or 0
– 55_C
25_C
125_C
VDD
Vdc
Min
Max
Min
Typ (4.)
Max
Min
Max
Unit
“0” Level
VOL
5.0
10
15
—
—
—
0.05
0.05
0.05
—
—
—
0
0
0
0.05
0.05
0.05
—
—
—
0.05
0.05
0.05
Vdc
“1” Level
VOH
5.0
10
15
4.95
9.95
14.95
—
—
—
4.95
9.95
14.95
5.0
10
15
—
—
—
4.95
9.95
14.95
—
—
—
Vdc
Input Voltage
“0” Level
(VO = 4.5 or 0.5 Vdc)
(VO = 9.0 or 1.0 Vdc)
(VO = 13.5 or 1.5 Vdc)
VIL
5.0
10
15
—
—
—
1.5
3.0
4.0
—
—
—
2.25
4.50
6.75
1.5
3.0
4.0
—
—
—
1.5
3.0
4.0
“1” Level
VIH
5.0
10
15
3.5
7.0
11
—
—
—
3.5
7.0
11
2.75
5.50
8.25
—
—
—
3.5
7.0
11
—
—
—
Source
Pins 4 & 7
5.0
5.0
10
15
– 1.2
– 0.25
– 0.62
– 1.8
—
—
—
—
– 1.0
– 0.2
– 0.5
– 1.5
– 1.7
– 0.36
– 0.9
– 3.5
—
—
—
—
– 0.7
– 0.14
– 0.35
– 1.1
—
—
—
—
(VOH = 2.5 Vdc)
Source
(VOH = 4.6 Vdc)
Pins 1, 10,
(VOH = 9.5 Vdc) 11, 12, 13, 14
(VOH = 13.5 Vdc)
and 15
5.0
5.0
10
15
– 3.0
– 0.64
– 1.6
– 4.2
—
—
—
—
– 2.4
– 0.51
– 1.3
– 3.4
– 4.2
– 0.88
– 2.25
– 8.8
—
—
—
—
– 1.7
– 0.36
– 0.9
– 2.4
—
—
—
—
mAdc
IOL
5.0
10
15
0.64
1.6
4.2
—
—
—
0.51
1.3
3.4
0.88
2.25
8.8
—
—
—
0.36
0.9
2.4
—
—
—
mAdc
Input Current
Iin
15
—
± 0.1
—
± 0.00001
± 0.1
—
± 1.0
µAdc
Input Capacitance
(Vin = 0)
Cin
—
—
—
—
5.0
7.5
—
—
pF
Quiescent Current
(Per Package)
IDD
5.0
10
15
—
—
—
5.0
10
20
—
—
—
0.005
0.010
0.015
5.0
10
20
—
—
—
150
300
600
µAdc
IT
5.0
10
15
Vin = 0 or VDD
(VO = 0.5 or 4.5 Vdc)
(VO = 1.0 or 9.0 Vdc)
(VO = 1.5 or 13.5 Vdc)
Output Drive Current
(VOH = 2.5 Vdc)
(VOH = 4.6 Vdc)
(VOH = 9.5 Vdc)
(VOH = 13.5 Vdc)
(VOL = 0.4 Vdc)
(VOL = 0.5 Vdc)
(VOL = 1.5 Vdc)
Vdc
Vdc
IOH
Sink
Total Supply Current (5.) (6.)
(Dynamic plus Quiescent,
Per Package)
(CL = 50 pF on all outputs, all
buffers switching)
mAdc
IT = (0.42 µA/kHz) f + IDD
IT = (0.85 µA/kHz) f + IDD
IT = (1.40 µA/kHz) f + IDD
4. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
5. The formulas given are for the typical characteristics only at 25_C.
6. To calculate total supply current at loads other than 50 pF:
IT(CL) = IT(50 pF) + (CL – 50) Vfk
where: IT is in µA (per package), CL in pF, V = (VDD – VSS) in volts, f in kHz is input frequency, and k = 0.003.
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3
µAdc
MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
SWITCHING CHARACTERISTICS (7.) (CL = 50 pF, TA = 25_C)
Characteristic
Symbol
Output Rise and Fall Time (Counter Outputs)
tTLH, tTHL = (1.5 ns/pF) CL + 25 ns
tTLH, tTHL = (0.75 ns/pF) CL + 12.5 ns
tTLH, tTHL = (0.55 ns/pF) CL + 12.5 ns
tTLH, tTHL
Propagation Delay Time
Clock to Q18
tPHL, tPLH = (1.7 ns/pF) CL + 4415 ns
tPHL, tPLH = (0.66 ns/pF) CL + 1667 ns
tPHL, tPLH = (0.5 ns/pF) CL + 1275 ns
tPHL, tPLH
Min
Typ (8.)
Max
5.0
10
15
—
—
—
100
50
40
200
100
80
Unit
ns
µs
Clock to Q24
tPHL, tPLH = (1.7 ns/pF) CL + 5915 ns
tPHL, tPLH = (0.66 ns/pF) CL + 2167 ns
tPHL, tPLH = (0.5 ns/pF) CL + 1675 ns
Propagation Delay Time
Reset to Qn
tPHL = (1.7 ns/pF) CL + 1215 ns
tPHL = (0.66 ns/pF) CL + 467 ns
tPHL = (0.5 ns/pF) CL + 350 ns
VDD
Vdc
5.0
10
15
—
—
—
4.5
1.7
1.3
9.0
3.5
2.7
5.0
10
15
—
—
—
6.0
2.2
1.7
12
4.5
3.5
tPHL
5.0
10
15
—
—
—
1300
500
375
2600
1000
750
tWH(cl)
5.0
10
15
385
150
120
140
55
40
—
—
—
ns
fcl
5.0
10
15
—
—
—
3.5
9.0
12
2.0
5.0
6.5
MHz
tTLH, tTHL
5.0
10
15
—
—
—
—
—
—
15
5.0
4.0
µs
tWH(R)
5.0
10
15
1400
600
450
700
300
225
—
—
—
ns
trem
5.0
10
15
30
0
– 40
– 200
– 160
– 110
—
—
—
ns
Clock Pulse Width
Clock Pulse Frequency
Clock Rise and Fall Time
ns
Reset Pulse Width
Reset Removal Time
7. The formulas given are for the typical characteristics only at 25_C.
8. Data labelled “Typ” is not to be used for design purposes but is intended as an indication of the IC’s potential performance.
VDD
500 µF
VDD
PULSE
GENERATOR
0.01 µF
CERAMIC
ID
IN 2
R
VSS
VDD
Q18
Q19
Q20
Q21
Q22
Q23
Q24
CL
CL
Vin
CL
20 ns
90%
50%
10%
50% DUTY CYCLE
CL
CL
CL
CL
VSS
Figure 1. Power Dissipation Test Circuit and Waveform
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4
20 ns
VDD
0V
MC14521B
VDD
VDD′
VDD
PULSE
GENERATOR
IN 2
R
20 ns
CL
CL
tWL
CL
CL
Qn
CL
50%
20 ns
90%
50%
10%
CL
VSS′
VSS
20 ns
IN 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
tWH
90%
10%
tPLH
tTLH
CL
tPHL
tTHL
Figure 2. Switching Time Test Circuit and Waveforms
500 kHz
Circuit
50 kHz
Circuit
Unit
Crystal Characteristics
Resonant Frequency
Equivalent Resistance, RS
500
1.0
50
6.2
kHz
kΩ
External Resistor/Capacitor Values
Ro
CT
CS
47
82
20
750
82
20
kΩ
pF
pF
+ 6.0
+ 2.0
+ 2.0
+ 2.0
ppm
ppm
– 4.0
+ 100
– 2.0
+ 120
ppm
ppm
– 2.0
– 160
– 2.0
– 560
ppm
ppm
Characteristic
VDD
Ro
18 M
CS
CT
VDD
R*
VDD′
IN 1 OUT 1
OUT 2
Q18
Q19
IN 2
Q20
Q21
Q22
Q23
R
Q24
VSS
VSS′
R*
* Optional for low power operation,
10 kΩ ≤ R ≤ 70 kΩ.
Figure 3. Crystal Oscillator Circuit
Frequency Stability
Frequency Change as a Function
of VDD (TA = 25_C)
VDD Change from 5.0 V to 10 V
VDD Change from 10 V to 15 V
Frequency Change as a Function
of Temperature (VDD = 10 V)
TA Change from – 55_C to + 25_C
MC14521 only
Complete Oscillator*
TA Change from + 25_C to + 125_C
MC14521 only
Complete Oscillator*
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
*Complete oscillator includes crystal, capacitors, and resistors.
Figure 4. Typical Data for Crystal Oscillator Circuit
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5
MC14521B
f, OSCILLATOR FREQUENCY (kHz)
100
8.0
FREQUENCY DEVIATION (%)
VDD = 15 V
4.0
TEST CIRCUIT
FIGURE 7
0
10 V
–4.0
–8.0
5.0 V
20
f AS A FUNCTION
OF RTC
(C = 1000 pF)
(RS ≈ 2RTC)
10
5.0
2.0
1.0
TEST CIRCUIT
FIGURE 7
VDD = 10 V
50
f AS A FUNCTION
OF C
(RTC = 56 kΩ)
(RS = 120 k)
0.5
0.2
–12
RTC = 56 kΩ,
C = 1000 pF
–16
–55
0.1
RS = 0, f = 10.15 kHz @ VDD = 10 V, TA = 25°C
RS = 120 kΩ, f = 7.8 kHz @ VDD = 10 V, TA = 25°C
{
–25
0
25
50
75
100
TA, AMBIENT TEMPERATURE (°C), DEVICE ONLY
1.0 k
125
0.0001
Figure 5. RC Oscillator Stability
RS
RTC
10 k
100 k
RTC, RESISTANCE (OHMS)
0.001
0.01
C, CAPACITANCE (µF)
1.0 m
0.1
Figure 6. RC Oscillator Frequency as a
Function of RTC and C
VDD
VDD
C
VDD
VDD′
VDD′
IN 1
IN 1
IN 2
R
OUT 1
OUT 2
Q18
Q19
Q20
Q21
Q22
Q23
Q24
VSS
PULSE
GENERATOR
Q18
Q19
Q20
Q21
IN 2
Q22
Q23
Q24
OUT 1
R
OUT 2
VSS
VSS′
Figure 7. RC Oscillator Circuit
VSS
Figure 8. Functional Test Circuit
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6
MC14521B
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ
FUNCTIONAL TEST SEQUENCE
Inputs
A test function (see Figure 8) has been
included for the reduction of test time required to
exercise all 24 counter stages. This test function
divides the counter into three 8–stage sections,
and 255 counts are loaded in each of the
8–stage sections in parallel. All flip–flops are
now at a logic
g “1”. The counter is now returned
to the normal 24–stages in series configuration.
One more pulse is entered into Input 2 (In 2)
which will cause the counter to ripple from an all
“1” state to an all “0” state.
Outputs
Comments
Reset
In 2
Out 2
VSS′
VDD′
Q18 thru
Q24
1
0
0
VDD
Gnd
0
0
1
1
First “0” to “1” transition
on In 2, Out 2 node.
0
1
—
—
—
0
1
—
—
—
255 “0” to “1” transitions
are clocked into this In 2,
Out 2 node.
1
1
1
0
0
0
0
1
1
1
0
1
0
G d
Gnd
The 255th “0” to “1”
transition.
1
Counter converted back to
24–stages in series mode.
0
1
Out 2 converts back to an
output.
1
0
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7
Counter is in three 8–stage
sections in parallel mode
Counter is reset. In 2 and
Out 2 are connected
together
VDD
Counter ripples from an all
“1” state to an all “0” stage.
MC14521B
LOGIC DIAGRAM
VDD
5
RESET
2
9
1
2
IN 1
3
VSS
9
17
18
19
10
Q18
8
4
OUT 2
6
IN 2
7
OUT 1
STAGES
3 THRU 7
20
11
Q19
21
12
Q20
22
10
23
13
Q21
14
Q22
16
24
15
Q23
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8
STAGES
11 THRU 15
1
Q24
VDD = PIN 16
VSS = PIN 8
MC14521B
PACKAGE DIMENSIONS
PDIP–16
P SUFFIX
PLASTIC DIP PACKAGE
CASE 648–08
ISSUE R
–A–
16
9
1
8
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEADS WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD FLASH.
5. ROUNDED CORNERS OPTIONAL.
B
F
C
L
S
–T–
SEATING
PLANE
K
H
G
D
M
J
16 PL
0.25 (0.010)
M
T A
M
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9
DIM
A
B
C
D
F
G
H
J
K
L
M
S
INCHES
MIN
MAX
0.740
0.770
0.250
0.270
0.145
0.175
0.015
0.021
0.040
0.70
0.100 BSC
0.050 BSC
0.008
0.015
0.110
0.130
0.295
0.305
0_
10 _
0.020
0.040
MILLIMETERS
MIN
MAX
18.80
19.55
6.35
6.85
3.69
4.44
0.39
0.53
1.02
1.77
2.54 BSC
1.27 BSC
0.21
0.38
2.80
3.30
7.50
7.74
0_
10 _
0.51
1.01
MC14521B
PACKAGE DIMENSIONS
SOIC–16
D SUFFIX
PLASTIC SOIC PACKAGE
CASE 751B–05
ISSUE J
–A–
16
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
9
–B–
1
P
8 PL
0.25 (0.010)
8
M
B
S
G
R
K
F
X 45 _
C
–T–
SEATING
PLANE
J
M
D
16 PL
0.25 (0.010)
M
T B
S
A
S
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10
DIM
A
B
C
D
F
G
J
K
M
P
R
MILLIMETERS
MIN
MAX
9.80
10.00
3.80
4.00
1.35
1.75
0.35
0.49
0.40
1.25
1.27 BSC
0.19
0.25
0.10
0.25
0_
7_
5.80
6.20
0.25
0.50
INCHES
MIN
MAX
0.386
0.393
0.150
0.157
0.054
0.068
0.014
0.019
0.016
0.049
0.050 BSC
0.008
0.009
0.004
0.009
0_
7_
0.229
0.244
0.010
0.019
MC14521B
PACKAGE DIMENSIONS
SOEIAJ–16
F SUFFIX
PLASTIC EIAJ SOIC PACKAGE
CASE 966–01
ISSUE O
16
LE
9
Q1
M_
E HE
1
L
8
DETAIL P
Z
D
e
VIEW P
A
A1
b
0.13 (0.005)
c
M
0.10 (0.004)
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11
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSIONS D AND E DO NOT INCLUDE
MOLD FLASH OR PROTRUSIONS AND ARE
MEASURED AT THE PARTING LINE. MOLD FLASH
OR PROTRUSIONS SHALL NOT EXCEED 0.15
(0.006) PER SIDE.
4. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
5. THE LEAD WIDTH DIMENSION (b) DOES NOT
INCLUDE DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08 (0.003)
TOTAL IN EXCESS OF THE LEAD WIDTH
DIMENSION AT MAXIMUM MATERIAL CONDITION.
DAMBAR CANNOT BE LOCATED ON THE LOWER
RADIUS OR THE FOOT. MINIMUM SPACE
BETWEEN PROTRUSIONS AND ADJACENT LEAD
TO BE 0.46 ( 0.018).
DIM
A
A1
b
c
D
E
e
HE
L
LE
M
Q1
Z
MILLIMETERS
MIN
MAX
–––
2.05
0.05
0.20
0.35
0.50
0.18
0.27
9.90
10.50
5.10
5.45
1.27 BSC
7.40
8.20
0.50
0.85
1.10
1.50
10 _
0_
0.70
0.90
–––
0.78
INCHES
MIN
MAX
–––
0.081
0.002
0.008
0.014
0.020
0.007
0.011
0.390
0.413
0.201
0.215
0.050 BSC
0.291
0.323
0.020
0.033
0.043
0.059
10 _
0_
0.028
0.035
–––
0.031
MC14521B
ON Semiconductor and
are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes
without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular
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12
MC14521B/D